1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
2 /*
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
4 */
5
6 #ifndef _STM32PROG_H_
7 #define _STM32PROG_H_
8
9 /* - phase defines ------------------------------------------------*/
10 #define PHASE_FLASHLAYOUT 0x00
11 #define PHASE_FIRST_USER 0x10
12 #define PHASE_LAST_USER 0xF0
13 #define PHASE_CMD 0xF1
14 #define PHASE_OTP 0xF2
15 #define PHASE_PMIC 0xF4
16 #define PHASE_END 0xFE
17 #define PHASE_RESET 0xFF
18 #define PHASE_DO_RESET 0x1FF
19
20 #define DEFAULT_ADDRESS 0xFFFFFFFF
21
22 #define CMD_SIZE 512
23 #define OTP_SIZE 1024
24 #define PMIC_SIZE 8
25
26 enum stm32prog_target {
27 STM32PROG_NONE,
28 STM32PROG_MMC,
29 STM32PROG_NAND,
30 STM32PROG_NOR,
31 STM32PROG_SPI_NAND,
32 STM32PROG_RAM
33 };
34
35 enum stm32prog_link_t {
36 LINK_SERIAL,
37 LINK_USB,
38 LINK_UNDEFINED,
39 };
40
41 enum stm32prog_header_t {
42 HEADER_NONE,
43 HEADER_STM32IMAGE,
44 HEADER_FIP,
45 };
46
47 struct image_header_s {
48 enum stm32prog_header_t type;
49 u32 image_checksum;
50 u32 image_length;
51 };
52
53 struct raw_header_s {
54 u32 magic_number;
55 u32 image_signature[64 / 4];
56 u32 image_checksum;
57 u32 header_version;
58 u32 image_length;
59 u32 image_entry_point;
60 u32 reserved1;
61 u32 load_address;
62 u32 reserved2;
63 u32 version_number;
64 u32 option_flags;
65 u32 ecdsa_algorithm;
66 u32 ecdsa_public_key[64 / 4];
67 u32 padding[83 / 4];
68 u32 binary_type;
69 };
70
71 #define BL_HEADER_SIZE sizeof(struct raw_header_s)
72
73 /* partition type in flashlayout file */
74 enum stm32prog_part_type {
75 PART_BINARY,
76 PART_SYSTEM,
77 PART_FILESYSTEM,
78 RAW_IMAGE
79 };
80
81 /* device information */
82 struct stm32prog_dev_t {
83 enum stm32prog_target target;
84 char dev_id;
85 u32 erase_size;
86 struct mmc *mmc;
87 struct mtd_info *mtd;
88 /* list of partition for this device / ordered in offset */
89 struct list_head part_list;
90 bool full_update;
91 };
92
93 /* partition information build from FlashLayout and device */
94 struct stm32prog_part_t {
95 /* FlashLayout information */
96 int option;
97 int id;
98 enum stm32prog_part_type part_type;
99 enum stm32prog_target target;
100 char dev_id;
101
102 /* partition name
103 * (16 char in gpt, + 1 for null terminated string
104 */
105 char name[16 + 1];
106 u64 addr;
107 u64 size;
108 enum stm32prog_part_type bin_nb; /* SSBL repeatition */
109
110 /* information on associated device */
111 struct stm32prog_dev_t *dev; /* pointer to device */
112 s16 part_id; /* partition id in device */
113 int alt_id; /* alt id in usb/dfu */
114
115 struct list_head list;
116 };
117
118 #define STM32PROG_MAX_DEV 5
119 struct stm32prog_data {
120 /* Layout information */
121 int dev_nb; /* device number*/
122 struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */
123 int part_nb; /* nb of partition */
124 struct stm32prog_part_t *part_array; /* array of partition */
125 #ifdef CONFIG_STM32MP15x_STM32IMAGE
126 bool tee_detected;
127 #endif
128 bool fsbl_nor_detected;
129
130 /* command internal information */
131 unsigned int phase;
132 u32 offset;
133 char error[255];
134 struct stm32prog_part_t *cur_part;
135 u32 *otp_part;
136 u8 pmic_part[PMIC_SIZE];
137
138 /* SERIAL information */
139 u32 cursor;
140 u32 packet_number;
141 u8 *buffer; /* size = USART_RAM_BUFFER_SIZE*/
142 int dfu_seq;
143 u8 read_phase;
144
145 /* bootm information */
146 u32 uimage;
147 u32 dtb;
148 u32 initrd;
149 u32 initrd_size;
150 };
151
152 extern struct stm32prog_data *stm32prog_data;
153
154 /* OTP access */
155 int stm32prog_otp_write(struct stm32prog_data *data, u32 offset,
156 u8 *buffer, long *size);
157 int stm32prog_otp_read(struct stm32prog_data *data, u32 offset,
158 u8 *buffer, long *size);
159 int stm32prog_otp_start(struct stm32prog_data *data);
160
161 /* PMIC access */
162 int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset,
163 u8 *buffer, long *size);
164 int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset,
165 u8 *buffer, long *size);
166 int stm32prog_pmic_start(struct stm32prog_data *data);
167
168 /* generic part*/
169 void stm32prog_header_check(struct raw_header_s *raw_header,
170 struct image_header_s *header);
171 int stm32prog_dfu_init(struct stm32prog_data *data);
172 void stm32prog_next_phase(struct stm32prog_data *data);
173 void stm32prog_do_reset(struct stm32prog_data *data);
174
175 char *stm32prog_get_error(struct stm32prog_data *data);
176
177 #define stm32prog_err(args...) {\
178 if (data->phase != PHASE_RESET) { \
179 sprintf(data->error, args); \
180 data->phase = PHASE_RESET; \
181 log_err("Error: %s\n", data->error); } \
182 }
183
184 /* Main function */
185 int stm32prog_init(struct stm32prog_data *data, ulong addr, ulong size);
186 void stm32prog_clean(struct stm32prog_data *data);
187
188 #ifdef CONFIG_CMD_STM32PROG_SERIAL
189 int stm32prog_serial_init(struct stm32prog_data *data, int link_dev);
190 bool stm32prog_serial_loop(struct stm32prog_data *data);
191 #else
stm32prog_serial_init(struct stm32prog_data * data,int link_dev)192 static inline int stm32prog_serial_init(struct stm32prog_data *data, int link_dev)
193 {
194 return -ENOSYS;
195 }
196
stm32prog_serial_loop(struct stm32prog_data * data)197 static inline bool stm32prog_serial_loop(struct stm32prog_data *data)
198 {
199 return false;
200 }
201 #endif
202
203 #ifdef CONFIG_CMD_STM32PROG_USB
204 bool stm32prog_usb_loop(struct stm32prog_data *data, int dev);
205 #else
stm32prog_usb_loop(struct stm32prog_data * data,int dev)206 static inline bool stm32prog_usb_loop(struct stm32prog_data *data, int dev)
207 {
208 return false;
209 }
210 #endif
211
212 #endif
213