1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Xilinx Zynq MPSoC Firmware driver 4 * 5 * Copyright (C) 2018-2019 Xilinx, Inc. 6 */ 7 8 #ifndef _ZYNQMP_FIRMWARE_H_ 9 #define _ZYNQMP_FIRMWARE_H_ 10 11 enum pm_api_id { 12 PM_GET_API_VERSION = 1, 13 PM_SET_CONFIGURATION = 2, 14 PM_GET_NODE_STATUS = 3, 15 PM_GET_OPERATING_CHARACTERISTIC = 4, 16 PM_REGISTER_NOTIFIER = 5, 17 /* API for suspending */ 18 PM_REQUEST_SUSPEND = 6, 19 PM_SELF_SUSPEND = 7, 20 PM_FORCE_POWERDOWN = 8, 21 PM_ABORT_SUSPEND = 9, 22 PM_REQUEST_WAKEUP = 10, 23 PM_SET_WAKEUP_SOURCE = 11, 24 PM_SYSTEM_SHUTDOWN = 12, 25 PM_REQUEST_NODE = 13, 26 PM_RELEASE_NODE = 14, 27 PM_SET_REQUIREMENT = 15, 28 PM_SET_MAX_LATENCY = 16, 29 /* Direct control API functions: */ 30 PM_RESET_ASSERT = 17, 31 PM_RESET_GET_STATUS = 18, 32 PM_MMIO_WRITE = 19, 33 PM_MMIO_READ = 20, 34 PM_PM_INIT_FINALIZE = 21, 35 PM_FPGA_LOAD = 22, 36 PM_FPGA_GET_STATUS = 23, 37 PM_GET_CHIPID = 24, 38 /* ID 25 is been used by U-boot to process secure boot images */ 39 /* Secure library generic API functions */ 40 PM_SECURE_SHA = 26, 41 PM_SECURE_RSA = 27, 42 PM_PINCTRL_REQUEST = 28, 43 PM_PINCTRL_RELEASE = 29, 44 PM_PINCTRL_GET_FUNCTION = 30, 45 PM_PINCTRL_SET_FUNCTION = 31, 46 PM_PINCTRL_CONFIG_PARAM_GET = 32, 47 PM_PINCTRL_CONFIG_PARAM_SET = 33, 48 PM_IOCTL = 34, 49 PM_QUERY_DATA = 35, 50 PM_CLOCK_ENABLE = 36, 51 PM_CLOCK_DISABLE = 37, 52 PM_CLOCK_GETSTATE = 38, 53 PM_CLOCK_SETDIVIDER = 39, 54 PM_CLOCK_GETDIVIDER = 40, 55 PM_CLOCK_SETRATE = 41, 56 PM_CLOCK_GETRATE = 42, 57 PM_CLOCK_SETPARENT = 43, 58 PM_CLOCK_GETPARENT = 44, 59 PM_SECURE_IMAGE = 45, 60 PM_FPGA_READ = 46, 61 PM_SECURE_AES = 47, 62 PM_CLOCK_PLL_GETPARAM = 49, 63 /* PM_REGISTER_ACCESS API */ 64 PM_REGISTER_ACCESS = 52, 65 PM_EFUSE_ACCESS = 53, 66 PM_FEATURE_CHECK = 63, 67 PM_API_MAX, 68 }; 69 70 enum pm_node_id { 71 NODE_UNKNOWN = 0, 72 NODE_APU = 1, 73 NODE_APU_0 = 2, 74 NODE_APU_1 = 3, 75 NODE_APU_2 = 4, 76 NODE_APU_3 = 5, 77 NODE_RPU = 6, 78 NODE_RPU_0 = 7, 79 NODE_RPU_1 = 8, 80 NODE_PLD = 9, 81 NODE_FPD = 10, 82 NODE_OCM_BANK_0 = 11, 83 NODE_OCM_BANK_1 = 12, 84 NODE_OCM_BANK_2 = 13, 85 NODE_OCM_BANK_3 = 14, 86 NODE_TCM_0_A = 15, 87 NODE_TCM_0_B = 16, 88 NODE_TCM_1_A = 17, 89 NODE_TCM_1_B = 18, 90 NODE_L2 = 19, 91 NODE_GPU_PP_0 = 20, 92 NODE_GPU_PP_1 = 21, 93 NODE_USB_0 = 22, 94 NODE_USB_1 = 23, 95 NODE_TTC_0 = 24, 96 NODE_TTC_1 = 25, 97 NODE_TTC_2 = 26, 98 NODE_TTC_3 = 27, 99 NODE_SATA = 28, 100 NODE_ETH_0 = 29, 101 NODE_ETH_1 = 30, 102 NODE_ETH_2 = 31, 103 NODE_ETH_3 = 32, 104 NODE_UART_0 = 33, 105 NODE_UART_1 = 34, 106 NODE_SPI_0 = 35, 107 NODE_SPI_1 = 36, 108 NODE_I2C_0 = 37, 109 NODE_I2C_1 = 38, 110 NODE_SD_0 = 39, 111 NODE_SD_1 = 40, 112 NODE_DP = 41, 113 NODE_GDMA = 42, 114 NODE_ADMA = 43, 115 NODE_NAND = 44, 116 NODE_QSPI = 45, 117 NODE_GPIO = 46, 118 NODE_CAN_0 = 47, 119 NODE_CAN_1 = 48, 120 NODE_EXTERN = 49, 121 NODE_APLL = 50, 122 NODE_VPLL = 51, 123 NODE_DPLL = 52, 124 NODE_RPLL = 53, 125 NODE_IOPLL = 54, 126 NODE_DDR = 55, 127 NODE_IPI_APU = 56, 128 NODE_IPI_RPU_0 = 57, 129 NODE_GPU = 58, 130 NODE_PCIE = 59, 131 NODE_PCAP = 60, 132 NODE_RTC = 61, 133 NODE_LPD = 62, 134 NODE_VCU = 63, 135 NODE_IPI_RPU_1 = 64, 136 NODE_IPI_PL_0 = 65, 137 NODE_IPI_PL_1 = 66, 138 NODE_IPI_PL_2 = 67, 139 NODE_IPI_PL_3 = 68, 140 NODE_PL = 69, 141 NODE_GEM_TSU = 70, 142 NODE_SWDT_0 = 71, 143 NODE_SWDT_1 = 72, 144 NODE_CSU = 73, 145 NODE_PJTAG = 74, 146 NODE_TRACE = 75, 147 NODE_TESTSCAN = 76, 148 NODE_PMU = 77, 149 NODE_MAX = 78, 150 }; 151 152 enum tap_delay_type { 153 PM_TAPDELAY_INPUT = 0, 154 PM_TAPDELAY_OUTPUT = 1, 155 }; 156 157 enum dll_reset_type { 158 PM_DLL_RESET_ASSERT = 0, 159 PM_DLL_RESET_RELEASE = 1, 160 PM_DLL_RESET_PULSE = 2, 161 }; 162 163 enum pm_query_id { 164 PM_QID_INVALID = 0, 165 PM_QID_CLOCK_GET_NAME = 1, 166 PM_QID_CLOCK_GET_TOPOLOGY = 2, 167 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, 168 PM_QID_CLOCK_GET_PARENTS = 4, 169 PM_QID_CLOCK_GET_ATTRIBUTES = 5, 170 PM_QID_PINCTRL_GET_NUM_PINS = 6, 171 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, 172 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, 173 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, 174 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, 175 PM_QID_PINCTRL_GET_PIN_GROUPS = 11, 176 PM_QID_CLOCK_GET_NUM_CLOCKS = 12, 177 PM_QID_CLOCK_GET_MAX_DIVISOR = 13, 178 }; 179 180 enum zynqmp_pm_reset_action { 181 PM_RESET_ACTION_RELEASE = 0, 182 PM_RESET_ACTION_ASSERT = 1, 183 PM_RESET_ACTION_PULSE = 2, 184 }; 185 186 enum zynqmp_pm_reset { 187 ZYNQMP_PM_RESET_START = 1000, 188 ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, 189 ZYNQMP_PM_RESET_PCIE_BRIDGE = 1001, 190 ZYNQMP_PM_RESET_PCIE_CTRL = 1002, 191 ZYNQMP_PM_RESET_DP = 1003, 192 ZYNQMP_PM_RESET_SWDT_CRF = 1004, 193 ZYNQMP_PM_RESET_AFI_FM5 = 1005, 194 ZYNQMP_PM_RESET_AFI_FM4 = 1006, 195 ZYNQMP_PM_RESET_AFI_FM3 = 1007, 196 ZYNQMP_PM_RESET_AFI_FM2 = 1008, 197 ZYNQMP_PM_RESET_AFI_FM1 = 1009, 198 ZYNQMP_PM_RESET_AFI_FM0 = 1010, 199 ZYNQMP_PM_RESET_GDMA = 1011, 200 ZYNQMP_PM_RESET_GPU_PP1 = 1012, 201 ZYNQMP_PM_RESET_GPU_PP0 = 1013, 202 ZYNQMP_PM_RESET_GPU = 1014, 203 ZYNQMP_PM_RESET_GT = 1015, 204 ZYNQMP_PM_RESET_SATA = 1016, 205 ZYNQMP_PM_RESET_ACPU3_PWRON = 1017, 206 ZYNQMP_PM_RESET_ACPU2_PWRON = 1018, 207 ZYNQMP_PM_RESET_ACPU1_PWRON = 1019, 208 ZYNQMP_PM_RESET_ACPU0_PWRON = 1020, 209 ZYNQMP_PM_RESET_APU_L2 = 1021, 210 ZYNQMP_PM_RESET_ACPU3 = 1022, 211 ZYNQMP_PM_RESET_ACPU2 = 1023, 212 ZYNQMP_PM_RESET_ACPU1 = 1024, 213 ZYNQMP_PM_RESET_ACPU0 = 1025, 214 ZYNQMP_PM_RESET_DDR = 1026, 215 ZYNQMP_PM_RESET_APM_FPD = 1027, 216 ZYNQMP_PM_RESET_SOFT = 1028, 217 ZYNQMP_PM_RESET_GEM0 = 1029, 218 ZYNQMP_PM_RESET_GEM1 = 1030, 219 ZYNQMP_PM_RESET_GEM2 = 1031, 220 ZYNQMP_PM_RESET_GEM3 = 1032, 221 ZYNQMP_PM_RESET_QSPI = 1033, 222 ZYNQMP_PM_RESET_UART0 = 1034, 223 ZYNQMP_PM_RESET_UART1 = 1035, 224 ZYNQMP_PM_RESET_SPI0 = 1036, 225 ZYNQMP_PM_RESET_SPI1 = 1037, 226 ZYNQMP_PM_RESET_SDIO0 = 1038, 227 ZYNQMP_PM_RESET_SDIO1 = 1039, 228 ZYNQMP_PM_RESET_CAN0 = 1040, 229 ZYNQMP_PM_RESET_CAN1 = 1041, 230 ZYNQMP_PM_RESET_I2C0 = 1042, 231 ZYNQMP_PM_RESET_I2C1 = 1043, 232 ZYNQMP_PM_RESET_TTC0 = 1044, 233 ZYNQMP_PM_RESET_TTC1 = 1045, 234 ZYNQMP_PM_RESET_TTC2 = 1046, 235 ZYNQMP_PM_RESET_TTC3 = 1047, 236 ZYNQMP_PM_RESET_SWDT_CRL = 1048, 237 ZYNQMP_PM_RESET_NAND = 1049, 238 ZYNQMP_PM_RESET_ADMA = 1050, 239 ZYNQMP_PM_RESET_GPIO = 1051, 240 ZYNQMP_PM_RESET_IOU_CC = 1052, 241 ZYNQMP_PM_RESET_TIMESTAMP = 1053, 242 ZYNQMP_PM_RESET_RPU_R50 = 1054, 243 ZYNQMP_PM_RESET_RPU_R51 = 1055, 244 ZYNQMP_PM_RESET_RPU_AMBA = 1056, 245 ZYNQMP_PM_RESET_OCM = 1057, 246 ZYNQMP_PM_RESET_RPU_PGE = 1058, 247 ZYNQMP_PM_RESET_USB0_CORERESET = 1059, 248 ZYNQMP_PM_RESET_USB1_CORERESET = 1060, 249 ZYNQMP_PM_RESET_USB0_HIBERRESET = 1061, 250 ZYNQMP_PM_RESET_USB1_HIBERRESET = 1062, 251 ZYNQMP_PM_RESET_USB0_APB = 1063, 252 ZYNQMP_PM_RESET_USB1_APB = 1064, 253 ZYNQMP_PM_RESET_IPI = 1065, 254 ZYNQMP_PM_RESET_APM_LPD = 1066, 255 ZYNQMP_PM_RESET_RTC = 1067, 256 ZYNQMP_PM_RESET_SYSMON = 1068, 257 ZYNQMP_PM_RESET_AFI_FM6 = 1069, 258 ZYNQMP_PM_RESET_LPD_SWDT = 1070, 259 ZYNQMP_PM_RESET_FPD = 1071, 260 ZYNQMP_PM_RESET_RPU_DBG1 = 1072, 261 ZYNQMP_PM_RESET_RPU_DBG0 = 1073, 262 ZYNQMP_PM_RESET_DBG_LPD = 1074, 263 ZYNQMP_PM_RESET_DBG_FPD = 1075, 264 ZYNQMP_PM_RESET_APLL = 1076, 265 ZYNQMP_PM_RESET_DPLL = 1077, 266 ZYNQMP_PM_RESET_VPLL = 1078, 267 ZYNQMP_PM_RESET_IOPLL = 1079, 268 ZYNQMP_PM_RESET_RPLL = 1080, 269 ZYNQMP_PM_RESET_GPO3_PL_0 = 1081, 270 ZYNQMP_PM_RESET_GPO3_PL_1 = 1082, 271 ZYNQMP_PM_RESET_GPO3_PL_2 = 1083, 272 ZYNQMP_PM_RESET_GPO3_PL_3 = 1084, 273 ZYNQMP_PM_RESET_GPO3_PL_4 = 1085, 274 ZYNQMP_PM_RESET_GPO3_PL_5 = 1086, 275 ZYNQMP_PM_RESET_GPO3_PL_6 = 1087, 276 ZYNQMP_PM_RESET_GPO3_PL_7 = 1088, 277 ZYNQMP_PM_RESET_GPO3_PL_8 = 1089, 278 ZYNQMP_PM_RESET_GPO3_PL_9 = 1090, 279 ZYNQMP_PM_RESET_GPO3_PL_10 = 1091, 280 ZYNQMP_PM_RESET_GPO3_PL_11 = 1092, 281 ZYNQMP_PM_RESET_GPO3_PL_12 = 1093, 282 ZYNQMP_PM_RESET_GPO3_PL_13 = 1094, 283 ZYNQMP_PM_RESET_GPO3_PL_14 = 1095, 284 ZYNQMP_PM_RESET_GPO3_PL_15 = 1096, 285 ZYNQMP_PM_RESET_GPO3_PL_16 = 1097, 286 ZYNQMP_PM_RESET_GPO3_PL_17 = 1098, 287 ZYNQMP_PM_RESET_GPO3_PL_18 = 1099, 288 ZYNQMP_PM_RESET_GPO3_PL_19 = 1100, 289 ZYNQMP_PM_RESET_GPO3_PL_20 = 1101, 290 ZYNQMP_PM_RESET_GPO3_PL_21 = 1102, 291 ZYNQMP_PM_RESET_GPO3_PL_22 = 1103, 292 ZYNQMP_PM_RESET_GPO3_PL_23 = 1104, 293 ZYNQMP_PM_RESET_GPO3_PL_24 = 1105, 294 ZYNQMP_PM_RESET_GPO3_PL_25 = 1106, 295 ZYNQMP_PM_RESET_GPO3_PL_26 = 1107, 296 ZYNQMP_PM_RESET_GPO3_PL_27 = 1108, 297 ZYNQMP_PM_RESET_GPO3_PL_28 = 1109, 298 ZYNQMP_PM_RESET_GPO3_PL_29 = 1110, 299 ZYNQMP_PM_RESET_GPO3_PL_30 = 1111, 300 ZYNQMP_PM_RESET_GPO3_PL_31 = 1112, 301 ZYNQMP_PM_RESET_RPU_LS = 1113, 302 ZYNQMP_PM_RESET_PS_ONLY = 1114, 303 ZYNQMP_PM_RESET_PL = 1115, 304 ZYNQMP_PM_RESET_PS_PL0 = 1116, 305 ZYNQMP_PM_RESET_PS_PL1 = 1117, 306 ZYNQMP_PM_RESET_PS_PL2 = 1118, 307 ZYNQMP_PM_RESET_PS_PL3 = 1119, 308 ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 309 }; 310 311 enum pm_ioctl_id { 312 IOCTL_GET_RPU_OPER_MODE = 0, 313 IOCTL_SET_RPU_OPER_MODE = 1, 314 IOCTL_RPU_BOOT_ADDR_CONFIG = 2, 315 IOCTL_TCM_COMB_CONFIG = 3, 316 IOCTL_SET_TAPDELAY_BYPASS = 4, 317 IOCTL_SET_SGMII_MODE = 5, 318 IOCTL_SD_DLL_RESET = 6, 319 IOCTL_SET_SD_TAPDELAY = 7, 320 IOCTL_SET_PLL_FRAC_MODE = 8, 321 IOCTL_GET_PLL_FRAC_MODE = 9, 322 IOCTL_SET_PLL_FRAC_DATA = 10, 323 IOCTL_GET_PLL_FRAC_DATA = 11, 324 IOCTL_WRITE_GGS = 12, 325 IOCTL_READ_GGS = 13, 326 IOCTL_WRITE_PGGS = 14, 327 IOCTL_READ_PGGS = 15, 328 /* IOCTL for ULPI reset */ 329 IOCTL_ULPI_RESET = 16, 330 /* Set healthy bit value*/ 331 IOCTL_SET_BOOT_HEALTH_STATUS = 17, 332 IOCTL_AFI = 18, 333 /* Probe counter read/write */ 334 IOCTL_PROBE_COUNTER_READ = 19, 335 IOCTL_PROBE_COUNTER_WRITE = 20, 336 IOCTL_OSPI_MUX_SELECT = 21, 337 /* IOCTL for USB power request */ 338 IOCTL_USB_SET_STATE = 22, 339 /* IOCTL to get last reset reason */ 340 IOCTL_GET_LAST_RESET_REASON = 23, 341 /* AIE ISR Clear */ 342 IOCTL_AIE_ISR_CLEAR = 24, 343 }; 344 345 #define PM_SIP_SVC 0xc2000000 346 347 #define ZYNQMP_PM_VERSION_MAJOR 1 348 #define ZYNQMP_PM_VERSION_MINOR 0 349 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 350 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF 351 352 #define ZYNQMP_PM_VERSION \ 353 ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ 354 ZYNQMP_PM_VERSION_MINOR) 355 356 #define ZYNQMP_PM_VERSION_INVALID ~0 357 358 #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) 359 360 /* 361 * Return payload size 362 * Not every firmware call expects the same amount of return bytes, however the 363 * firmware driver always copies 5 bytes from RX buffer to the ret_payload 364 * buffer. Therefore allocating with this defined value is recommended to avoid 365 * overflows. 366 */ 367 #define PAYLOAD_ARG_CNT 5U 368 369 unsigned int zynqmp_firmware_version(void); 370 void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); 371 int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, 372 u32 arg3, u32 *ret_payload); 373 374 #endif /* _ZYNQMP_FIRMWARE_H_ */ 375