1 /*
2  * Arm SCP/MCP Software
3  * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  *
7  * Description:
8  *      SCMI Clock Management Protocol Support
9  */
10 
11 #ifndef INTERNAL_SCMI_CLOCK_H
12 #define INTERNAL_SCMI_CLOCK_H
13 
14 #include <mod_clock.h>
15 
16 #define SCMI_PROTOCOL_VERSION_CLOCK UINT32_C(0x10000)
17 
18 /*
19  * Identifiers for the type of request being processed
20  */
21 enum scmi_clock_request_type {
22     SCMI_CLOCK_REQUEST_GET_STATE,
23     SCMI_CLOCK_REQUEST_GET_RATE,
24     SCMI_CLOCK_REQUEST_SET_RATE,
25     SCMI_CLOCK_REQUEST_SET_STATE,
26     SCMI_CLOCK_REQUEST_COUNT,
27 };
28 
29 /*
30  * Identifiers of the internal events
31  */
32 enum scmi_clock_event_idx {
33     SCMI_CLOCK_EVENT_IDX_GET_STATE,
34     SCMI_CLOCK_EVENT_IDX_GET_RATE,
35     SCMI_CLOCK_EVENT_IDX_SET_RATE,
36     SCMI_CLOCK_EVENT_IDX_SET_STATE,
37     SCMI_CLOCK_EVENT_IDX_COUNT,
38 };
39 
40 /*
41  * Container for the data when 'set_rate' operation is requested
42  */
43 struct event_set_rate_request_data {
44     uint32_t rate[2];
45     enum mod_clock_round_mode round_mode;
46 };
47 
48 /*
49  * Container for the data when 'set_state' operation is requested
50  */
51 struct event_set_state_request_data {
52     enum mod_clock_state state;
53 };
54 
55 /*
56  * Container for the data when 'set_' operation is requested
57  */
58 union event_request_data {
59     struct event_set_rate_request_data set_rate_data;
60     struct event_set_state_request_data set_state_data;
61 };
62 
63 /*
64  * Parameters of the event being processed
65  */
66 struct scmi_clock_event_request_params {
67     fwk_id_t clock_dev_id;
68     union event_request_data request_data;
69 };
70 
71 /*
72  * Generic p2a
73  */
74 struct scmi_clock_generic_p2a {
75     int32_t status;
76 };
77 
78 /*
79  * Protocol Attributes
80  */
81 
82 #define SCMI_CLOCK_PROTOCOL_ATTRIBUTES_MAX_PENDING_TRANSITIONS_POS  16
83 #define SCMI_CLOCK_PROTOCOL_ATTRIBUTES_CLOCK_COUNT_POS              0
84 
85 #define SCMI_CLOCK_PROTOCOL_ATTRIBUTES_MAX_PENDING_TRANSITIONS_MASK \
86     (UINT32_C(0xFF) << \
87     SCMI_CLOCK_PROTOCOL_ATTRIBUTES_MAX_PENDING_TRANSITIONS_POS)
88 #define SCMI_CLOCK_PROTOCOL_ATTRIBUTES_CLOCK_COUNT_MASK   \
89     (UINT32_C(0xFFFF) << SCMI_CLOCK_PROTOCOL_ATTRIBUTES_CLOCK_COUNT_POS)
90 
91 #define SCMI_CLOCK_PROTOCOL_ATTRIBUTES(MAX_PENDING_TRANSACTIONS, CLOCK_COUNT) \
92     ( \
93         ((MAX_PENDING_TRANSACTIONS << \
94             SCMI_CLOCK_PROTOCOL_ATTRIBUTES_MAX_PENDING_TRANSITIONS_POS) & \
95             SCMI_CLOCK_PROTOCOL_ATTRIBUTES_MAX_PENDING_TRANSITIONS_MASK) | \
96         (((CLOCK_COUNT) << SCMI_CLOCK_PROTOCOL_ATTRIBUTES_CLOCK_COUNT_POS) & \
97             SCMI_CLOCK_PROTOCOL_ATTRIBUTES_CLOCK_COUNT_MASK) \
98     )
99 
100 /*
101  * Clock Attributes
102  */
103 
104 #define SCMI_CLOCK_ATTRIBUTES_ENABLED_POS    0
105 
106 #define SCMI_CLOCK_ATTRIBUTES_ENABLED_MASK   \
107     (UINT32_C(0x1) << SCMI_CLOCK_ATTRIBUTES_ENABLED_POS)
108 
109 #define SCMI_CLOCK_ATTRIBUTES(ENABLED) \
110     ( \
111         (((ENABLED) << SCMI_CLOCK_ATTRIBUTES_ENABLED_POS) & \
112             SCMI_CLOCK_ATTRIBUTES_ENABLED_MASK) \
113     )
114 
115 struct scmi_clock_attributes_a2p {
116     uint32_t clock_id;
117 };
118 
119 #define SCMI_CLOCK_NAME_LENGTH_MAX 16
120 
121 struct scmi_clock_attributes_p2a {
122     int32_t status;
123     uint32_t attributes;
124     char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX];
125 };
126 
127 /*
128  * Clock Rate Get
129  */
130 
131 struct scmi_clock_rate_get_a2p {
132     uint32_t clock_id;
133 };
134 
135 struct scmi_clock_rate_get_p2a {
136     int32_t status;
137     uint32_t rate[2];
138 };
139 
140 /*
141  * Clock Rate Set
142  */
143 
144 /* If set, set the new clock rate asynchronously */
145 #define SCMI_CLOCK_RATE_SET_ASYNC_POS 0U
146 /* If set, do not send a delayed asynchronous response */
147 #define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS 1U
148 /* Round up, if set, otherwise round down */
149 #define SCMI_CLOCK_RATE_SET_ROUND_UP_POS 2U
150 /* If set, the platform chooses the appropriate rounding mode */
151 #define SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS 3U
152 
153 #define SCMI_CLOCK_RATE_SET_ASYNC_MASK \
154     (UINT32_C(0x1) << SCMI_CLOCK_RATE_SET_ASYNC_POS)
155 #define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_MASK \
156     (UINT32_C(0x1) << SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS)
157 #define SCMI_CLOCK_RATE_SET_ROUND_UP_MASK \
158     (UINT32_C(0x1) << SCMI_CLOCK_RATE_SET_ROUND_UP_POS)
159 #define SCMI_CLOCK_RATE_SET_ROUND_AUTO_MASK \
160     (UINT32_C(0x1) << SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS)
161 #define SCMI_CLOCK_RATE_SET_FLAGS_MASK \
162     (SCMI_CLOCK_RATE_SET_ASYNC_MASK | \
163      SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_MASK | \
164      SCMI_CLOCK_RATE_SET_ROUND_UP_MASK | SCMI_CLOCK_RATE_SET_ROUND_AUTO_MASK)
165 
166 struct scmi_clock_rate_set_a2p {
167     uint32_t flags;
168     uint32_t clock_id;
169     uint32_t rate[2];
170 };
171 
172 struct scmi_clock_rate_set_p2a {
173     int32_t status;
174 };
175 
176 /*
177  * Clock Config Set
178  */
179 
180 #define SCMI_CLOCK_CONFIG_SET_ENABLE_POS 0U
181 
182 #define SCMI_CLOCK_CONFIG_SET_ENABLE_MASK \
183     (UINT32_C(0x1) << SCMI_CLOCK_CONFIG_SET_ENABLE_POS)
184 
185 struct scmi_clock_config_set_a2p {
186     uint32_t clock_id;
187     uint32_t attributes;
188 };
189 
190 struct scmi_clock_config_set_p2a {
191     int32_t status;
192 };
193 
194 /*
195  * Clock Describe Rates
196  */
197 
198 #define SCMI_CLOCK_RATE_FORMAT_RANGE 1U
199 #define SCMI_CLOCK_RATE_FORMAT_LIST  0U
200 
201 #define SCMI_CLOCK_NUM_OF_RATES_RANGE 3U
202 
203 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS 16U
204 #define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS    12U
205 #define SCMI_CLOCK_DESCRIBE_RATES_COUNT_POS     0U
206 
207 #define SCMI_CLOCK_DESCRIBE_RATES_NUM_RATES_FLAGS( \
208     RATE_COUNT, RETURN_FORMAT, REMAINING_RATES) \
209     ( \
210         ((RATE_COUNT << \
211             SCMI_CLOCK_DESCRIBE_RATES_COUNT_POS) & \
212             SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK) | \
213         ((REMAINING_RATES << SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS) & \
214             SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK) | \
215         ((RETURN_FORMAT << SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS) & \
216             SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK) \
217     )
218 
219 #define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK \
220     (UINT32_C(0xFFFF) << SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS)
221 #define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK \
222     (UINT32_C(0x1) << SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS)
223 #define SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK \
224     (UINT32_C(0xFFF) << SCMI_CLOCK_DESCRIBE_RATES_COUNT_POS)
225 
226 #define SCMI_CLOCK_RATES_MAX(MAILBOX_SIZE) \
227     ((sizeof(struct scmi_clock_describe_rates_p2a) < (MAILBOX_SIZE))  ? \
228      (((MAILBOX_SIZE) - sizeof(struct scmi_clock_describe_rates_p2a))   \
229         / sizeof(struct scmi_clock_rate)) : 0)
230 
231 struct scmi_clock_rate {
232     uint32_t low;
233     uint32_t high;
234 };
235 
236 struct scmi_clock_describe_rates_a2p {
237     uint32_t clock_id;
238     uint32_t rate_index;
239 };
240 
241 struct scmi_clock_describe_rates_p2a {
242     int32_t status;
243     uint32_t num_rates_flags;
244     struct scmi_clock_rate rates[];
245 };
246 
247 #endif /* INTERNAL_SCMI_CLOCK_H */
248