1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
4 *
5 * Based on the r8180 driver, which is:
6 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
7 *
8 * Contact Information: wlanfae <wlanfae@realtek.com>
9 */
10 #include "rtl_core.h"
11 #include "r8192E_phy.h"
12 #include "r8192E_phyreg.h"
13 #include "r8190P_rtl8256.h"
14 #include "r8192E_cmdpkt.h"
15 #include "rtl_dm.h"
16 #include "rtl_wx.h"
17
18 static int WDCAPARA_ADD[] = {EDCAPARA_BE, EDCAPARA_BK, EDCAPARA_VI,
19 EDCAPARA_VO};
20
rtl92e_start_beacon(struct net_device * dev)21 void rtl92e_start_beacon(struct net_device *dev)
22 {
23 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
24 struct rtllib_network *net = &priv->rtllib->current_network;
25 u16 BcnTimeCfg = 0;
26 u16 BcnCW = 6;
27 u16 BcnIFS = 0xf;
28
29 rtl92e_irq_disable(dev);
30
31 rtl92e_writew(dev, ATIMWND, 2);
32
33 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
34 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
35 rtl92e_writew(dev, BCN_DMATIME, 256);
36
37 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
38
39 BcnTimeCfg |= BcnCW<<BCN_TCFG_CW_SHIFT;
40 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
41 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
42 rtl92e_irq_enable(dev);
43 }
44
_rtl92e_update_msr(struct net_device * dev)45 static void _rtl92e_update_msr(struct net_device *dev)
46 {
47 struct r8192_priv *priv = rtllib_priv(dev);
48 u8 msr;
49 enum led_ctl_mode LedAction = LED_CTL_NO_LINK;
50
51 msr = rtl92e_readb(dev, MSR);
52 msr &= ~MSR_LINK_MASK;
53
54 switch (priv->rtllib->iw_mode) {
55 case IW_MODE_INFRA:
56 if (priv->rtllib->state == RTLLIB_LINKED)
57 msr |= MSR_LINK_MANAGED;
58 LedAction = LED_CTL_LINK;
59 break;
60 case IW_MODE_ADHOC:
61 if (priv->rtllib->state == RTLLIB_LINKED)
62 msr |= MSR_LINK_ADHOC;
63 break;
64 case IW_MODE_MASTER:
65 if (priv->rtllib->state == RTLLIB_LINKED)
66 msr |= MSR_LINK_MASTER;
67 break;
68 default:
69 break;
70 }
71
72 rtl92e_writeb(dev, MSR, msr);
73 if (priv->rtllib->LedControlHandler)
74 priv->rtllib->LedControlHandler(dev, LedAction);
75 }
76
rtl92e_set_reg(struct net_device * dev,u8 variable,u8 * val)77 void rtl92e_set_reg(struct net_device *dev, u8 variable, u8 *val)
78 {
79 struct r8192_priv *priv = rtllib_priv(dev);
80
81 switch (variable) {
82 case HW_VAR_BSSID:
83 /* BSSIDR 2 byte alignment */
84 rtl92e_writew(dev, BSSIDR, *(u16 *)val);
85 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(val + 2));
86 break;
87
88 case HW_VAR_MEDIA_STATUS:
89 {
90 enum rt_op_mode OpMode = *((enum rt_op_mode *)(val));
91 u8 btMsr = rtl92e_readb(dev, MSR);
92
93 btMsr &= 0xfc;
94
95 switch (OpMode) {
96 case RT_OP_MODE_INFRASTRUCTURE:
97 btMsr |= MSR_INFRA;
98 break;
99
100 case RT_OP_MODE_IBSS:
101 btMsr |= MSR_ADHOC;
102 break;
103
104 case RT_OP_MODE_AP:
105 btMsr |= MSR_AP;
106 break;
107
108 default:
109 btMsr |= MSR_NOLINK;
110 break;
111 }
112
113 rtl92e_writeb(dev, MSR, btMsr);
114
115 }
116 break;
117
118 case HW_VAR_CECHK_BSSID:
119 {
120 u32 RegRCR, Type;
121
122 Type = val[0];
123 RegRCR = rtl92e_readl(dev, RCR);
124 priv->receive_config = RegRCR;
125
126 if (Type)
127 RegRCR |= (RCR_CBSSID);
128 else
129 RegRCR &= (~RCR_CBSSID);
130
131 rtl92e_writel(dev, RCR, RegRCR);
132 priv->receive_config = RegRCR;
133
134 }
135 break;
136
137 case HW_VAR_SLOT_TIME:
138
139 priv->slot_time = val[0];
140 rtl92e_writeb(dev, SLOT_TIME, val[0]);
141
142 break;
143
144 case HW_VAR_ACK_PREAMBLE:
145 {
146 u32 regTmp;
147
148 priv->short_preamble = (bool)*val;
149 regTmp = priv->basic_rate;
150 if (priv->short_preamble)
151 regTmp |= BRSR_AckShortPmb;
152 rtl92e_writel(dev, RRSR, regTmp);
153 break;
154 }
155
156 case HW_VAR_CPU_RST:
157 rtl92e_writel(dev, CPU_GEN, ((u32 *)(val))[0]);
158 break;
159
160 case HW_VAR_AC_PARAM:
161 {
162 u8 pAcParam = *val;
163 u32 eACI = pAcParam;
164 u8 u1bAIFS;
165 u32 u4bAcParam;
166 u8 mode = priv->rtllib->mode;
167 struct rtllib_qos_parameters *qop =
168 &priv->rtllib->current_network.qos_data.parameters;
169
170 u1bAIFS = qop->aifs[pAcParam] *
171 ((mode&(IEEE_G|IEEE_N_24G)) ? 9 : 20) + aSifsTime;
172
173 rtl92e_dm_init_edca_turbo(dev);
174
175 u4bAcParam = (le16_to_cpu(qop->tx_op_limit[pAcParam]) <<
176 AC_PARAM_TXOP_LIMIT_OFFSET) |
177 ((le16_to_cpu(qop->cw_max[pAcParam])) <<
178 AC_PARAM_ECW_MAX_OFFSET) |
179 ((le16_to_cpu(qop->cw_min[pAcParam])) <<
180 AC_PARAM_ECW_MIN_OFFSET) |
181 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET);
182
183 switch (eACI) {
184 case AC1_BK:
185 rtl92e_writel(dev, EDCAPARA_BK, u4bAcParam);
186 break;
187
188 case AC0_BE:
189 rtl92e_writel(dev, EDCAPARA_BE, u4bAcParam);
190 break;
191
192 case AC2_VI:
193 rtl92e_writel(dev, EDCAPARA_VI, u4bAcParam);
194 break;
195
196 case AC3_VO:
197 rtl92e_writel(dev, EDCAPARA_VO, u4bAcParam);
198 break;
199
200 default:
201 netdev_info(dev, "SetHwReg8185(): invalid ACI: %d !\n",
202 eACI);
203 break;
204 }
205 priv->rtllib->SetHwRegHandler(dev, HW_VAR_ACM_CTRL,
206 &pAcParam);
207 break;
208 }
209
210 case HW_VAR_ACM_CTRL:
211 {
212 struct rtllib_qos_parameters *qos_parameters =
213 &priv->rtllib->current_network.qos_data.parameters;
214 u8 pAcParam = *val;
215 u32 eACI = pAcParam;
216 union aci_aifsn *pAciAifsn = (union aci_aifsn *)&
217 (qos_parameters->aifs[0]);
218 u8 acm = pAciAifsn->f.acm;
219 u8 AcmCtrl = rtl92e_readb(dev, ACM_HW_CTRL);
220
221 if (acm) {
222 switch (eACI) {
223 case AC0_BE:
224 AcmCtrl |= ACM_HW_BEQ_EN;
225 break;
226
227 case AC2_VI:
228 AcmCtrl |= ACM_HW_VIQ_EN;
229 break;
230
231 case AC3_VO:
232 AcmCtrl |= ACM_HW_VOQ_EN;
233 break;
234 }
235 } else {
236 switch (eACI) {
237 case AC0_BE:
238 AcmCtrl &= (~ACM_HW_BEQ_EN);
239 break;
240
241 case AC2_VI:
242 AcmCtrl &= (~ACM_HW_VIQ_EN);
243 break;
244
245 case AC3_VO:
246 AcmCtrl &= (~ACM_HW_BEQ_EN);
247 break;
248
249 default:
250 break;
251 }
252 }
253 rtl92e_writeb(dev, ACM_HW_CTRL, AcmCtrl);
254 break;
255 }
256
257 case HW_VAR_SIFS:
258 rtl92e_writeb(dev, SIFS, val[0]);
259 rtl92e_writeb(dev, SIFS+1, val[0]);
260 break;
261
262 case HW_VAR_RF_TIMING:
263 {
264 u8 Rf_Timing = *val;
265
266 rtl92e_writeb(dev, rFPGA0_RFTiming1, Rf_Timing);
267 break;
268 }
269
270 default:
271 break;
272 }
273
274 }
275
_rtl92e_read_eeprom_info(struct net_device * dev)276 static void _rtl92e_read_eeprom_info(struct net_device *dev)
277 {
278 struct r8192_priv *priv = rtllib_priv(dev);
279 const u8 bMac_Tmp_Addr[ETH_ALEN] = {0x00, 0xe0, 0x4c, 0x00, 0x00, 0x01};
280 u8 tempval;
281 u8 ICVer8192, ICVer8256;
282 u16 i, usValue, IC_Version;
283 u16 EEPROMId;
284
285 EEPROMId = rtl92e_eeprom_read(dev, 0);
286 if (EEPROMId != RTL8190_EEPROM_ID) {
287 netdev_err(dev, "%s(): Invalid EEPROM ID: %x\n", __func__,
288 EEPROMId);
289 priv->autoload_fail_flag = true;
290 } else {
291 priv->autoload_fail_flag = false;
292 }
293
294 if (!priv->autoload_fail_flag) {
295 priv->eeprom_vid = rtl92e_eeprom_read(dev, EEPROM_VID >> 1);
296 priv->eeprom_did = rtl92e_eeprom_read(dev, EEPROM_DID >> 1);
297
298 usValue = rtl92e_eeprom_read(dev,
299 (EEPROM_Customer_ID >> 1)) >> 8;
300 priv->eeprom_customer_id = usValue & 0xff;
301 usValue = rtl92e_eeprom_read(dev,
302 EEPROM_ICVersion_ChannelPlan>>1);
303 priv->eeprom_chnl_plan = usValue&0xff;
304 IC_Version = (usValue & 0xff00)>>8;
305
306 ICVer8192 = IC_Version & 0xf;
307 ICVer8256 = (IC_Version & 0xf0)>>4;
308 if (ICVer8192 == 0x2) {
309 if (ICVer8256 == 0x5)
310 priv->card_8192_version = VERSION_8190_BE;
311 }
312 switch (priv->card_8192_version) {
313 case VERSION_8190_BD:
314 case VERSION_8190_BE:
315 break;
316 default:
317 priv->card_8192_version = VERSION_8190_BD;
318 break;
319 }
320 } else {
321 priv->card_8192_version = VERSION_8190_BD;
322 priv->eeprom_vid = 0;
323 priv->eeprom_did = 0;
324 priv->eeprom_customer_id = 0;
325 priv->eeprom_chnl_plan = 0;
326 }
327
328 if (!priv->autoload_fail_flag) {
329 u8 addr[ETH_ALEN];
330
331 for (i = 0; i < 6; i += 2) {
332 usValue = rtl92e_eeprom_read(dev,
333 (EEPROM_NODE_ADDRESS_BYTE_0 + i) >> 1);
334 *(u16 *)(&addr[i]) = usValue;
335 }
336 eth_hw_addr_set(dev, addr);
337 } else {
338 eth_hw_addr_set(dev, bMac_Tmp_Addr);
339 }
340
341 if (priv->card_8192_version > VERSION_8190_BD)
342 priv->tx_pwr_data_read_from_eeprom = true;
343 else
344 priv->tx_pwr_data_read_from_eeprom = false;
345
346 priv->rf_type = RTL819X_DEFAULT_RF_TYPE;
347
348 if (priv->card_8192_version > VERSION_8190_BD) {
349 if (!priv->autoload_fail_flag) {
350 tempval = (rtl92e_eeprom_read(dev,
351 (EEPROM_RFInd_PowerDiff >> 1))) & 0xff;
352 priv->eeprom_legacy_ht_tx_pwr_diff = tempval & 0xf;
353
354 if (tempval&0x80)
355 priv->rf_type = RF_1T2R;
356 else
357 priv->rf_type = RF_2T4R;
358 } else {
359 priv->eeprom_legacy_ht_tx_pwr_diff = 0x04;
360 }
361
362 if (!priv->autoload_fail_flag)
363 priv->eeprom_thermal_meter = ((rtl92e_eeprom_read(dev,
364 (EEPROM_ThermalMeter>>1))) &
365 0xff00) >> 8;
366 else
367 priv->eeprom_thermal_meter = EEPROM_Default_ThermalMeter;
368 priv->tssi_13dBm = priv->eeprom_thermal_meter * 100;
369
370 if (priv->epromtype == EEPROM_93C46) {
371 if (!priv->autoload_fail_flag) {
372 usValue = rtl92e_eeprom_read(dev,
373 EEPROM_TxPwDiff_CrystalCap >> 1);
374 priv->eeprom_ant_pwr_diff = usValue & 0x0fff;
375 priv->eeprom_crystal_cap = (usValue & 0xf000)
376 >> 12;
377 } else {
378 priv->eeprom_ant_pwr_diff =
379 EEPROM_Default_AntTxPowerDiff;
380 priv->eeprom_crystal_cap =
381 EEPROM_Default_TxPwDiff_CrystalCap;
382 }
383
384 for (i = 0; i < 14; i += 2) {
385 if (!priv->autoload_fail_flag)
386 usValue = rtl92e_eeprom_read(dev,
387 (EEPROM_TxPwIndex_CCK + i) >> 1);
388 else
389 usValue = EEPROM_Default_TxPower;
390 *((u16 *)(&priv->eeprom_tx_pwr_level_cck[i])) =
391 usValue;
392 }
393 for (i = 0; i < 14; i += 2) {
394 if (!priv->autoload_fail_flag)
395 usValue = rtl92e_eeprom_read(dev,
396 (EEPROM_TxPwIndex_OFDM_24G + i) >> 1);
397 else
398 usValue = EEPROM_Default_TxPower;
399 *((u16 *)(&priv->eeprom_tx_pwr_level_ofdm24g[i]))
400 = usValue;
401 }
402 }
403 if (priv->epromtype == EEPROM_93C46) {
404 for (i = 0; i < 14; i++) {
405 priv->tx_pwr_level_cck[i] =
406 priv->eeprom_tx_pwr_level_cck[i];
407 priv->tx_pwr_level_ofdm_24g[i] =
408 priv->eeprom_tx_pwr_level_ofdm24g[i];
409 }
410 priv->legacy_ht_tx_pwr_diff =
411 priv->eeprom_legacy_ht_tx_pwr_diff;
412 priv->antenna_tx_pwr_diff[0] = priv->eeprom_ant_pwr_diff & 0xf;
413 priv->antenna_tx_pwr_diff[1] = (priv->eeprom_ant_pwr_diff &
414 0xf0) >> 4;
415 priv->antenna_tx_pwr_diff[2] = (priv->eeprom_ant_pwr_diff &
416 0xf00) >> 8;
417 priv->crystal_cap = priv->eeprom_crystal_cap;
418 priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf;
419 priv->thermal_meter[1] = (priv->eeprom_thermal_meter &
420 0xf0) >> 4;
421 } else if (priv->epromtype == EEPROM_93C56) {
422 priv->legacy_ht_tx_pwr_diff =
423 priv->eeprom_legacy_ht_tx_pwr_diff;
424 priv->antenna_tx_pwr_diff[0] = 0;
425 priv->antenna_tx_pwr_diff[1] = 0;
426 priv->antenna_tx_pwr_diff[2] = 0;
427 priv->crystal_cap = priv->eeprom_crystal_cap;
428 priv->thermal_meter[0] = priv->eeprom_thermal_meter & 0xf;
429 priv->thermal_meter[1] = (priv->eeprom_thermal_meter &
430 0xf0) >> 4;
431 }
432 }
433
434 rtl92e_init_adaptive_rate(dev);
435
436 priv->rf_chip = RF_8256;
437
438 if (priv->reg_chnl_plan == 0xf)
439 priv->chnl_plan = priv->eeprom_chnl_plan;
440 else
441 priv->chnl_plan = priv->reg_chnl_plan;
442
443 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
444 priv->customer_id = RT_CID_DLINK;
445
446 switch (priv->eeprom_customer_id) {
447 case EEPROM_CID_DEFAULT:
448 priv->customer_id = RT_CID_DEFAULT;
449 break;
450 case EEPROM_CID_CAMEO:
451 priv->customer_id = RT_CID_819x_CAMEO;
452 break;
453 case EEPROM_CID_RUNTOP:
454 priv->customer_id = RT_CID_819x_RUNTOP;
455 break;
456 case EEPROM_CID_NetCore:
457 priv->customer_id = RT_CID_819X_NETCORE;
458 break;
459 case EEPROM_CID_TOSHIBA:
460 priv->customer_id = RT_CID_TOSHIBA;
461 if (priv->eeprom_chnl_plan & 0x80)
462 priv->chnl_plan = priv->eeprom_chnl_plan & 0x7f;
463 else
464 priv->chnl_plan = 0x0;
465 break;
466 case EEPROM_CID_Nettronix:
467 priv->customer_id = RT_CID_Nettronix;
468 break;
469 case EEPROM_CID_Pronet:
470 priv->customer_id = RT_CID_PRONET;
471 break;
472 case EEPROM_CID_DLINK:
473 priv->customer_id = RT_CID_DLINK;
474 break;
475
476 case EEPROM_CID_WHQL:
477 break;
478 default:
479 break;
480 }
481
482 if (priv->chnl_plan > CHANNEL_PLAN_LEN - 1)
483 priv->chnl_plan = 0;
484 priv->chnl_plan = COUNTRY_CODE_WORLD_WIDE_13;
485
486 if (priv->eeprom_vid == 0x1186 && priv->eeprom_did == 0x3304)
487 priv->rtllib->bSupportRemoteWakeUp = true;
488 else
489 priv->rtllib->bSupportRemoteWakeUp = false;
490 }
491
rtl92e_get_eeprom_size(struct net_device * dev)492 void rtl92e_get_eeprom_size(struct net_device *dev)
493 {
494 u16 curCR;
495 struct r8192_priv *priv = rtllib_priv(dev);
496
497 curCR = rtl92e_readw(dev, EPROM_CMD);
498 priv->epromtype = (curCR & EPROM_CMD_9356SEL) ? EEPROM_93C56 :
499 EEPROM_93C46;
500 _rtl92e_read_eeprom_info(dev);
501 }
502
_rtl92e_hwconfig(struct net_device * dev)503 static void _rtl92e_hwconfig(struct net_device *dev)
504 {
505 u32 regRATR = 0, regRRSR = 0;
506 u8 regBwOpMode = 0, regTmp = 0;
507 struct r8192_priv *priv = rtllib_priv(dev);
508
509 switch (priv->rtllib->mode) {
510 case WIRELESS_MODE_B:
511 regBwOpMode = BW_OPMODE_20MHZ;
512 regRATR = RATE_ALL_CCK;
513 regRRSR = RATE_ALL_CCK;
514 break;
515 case WIRELESS_MODE_A:
516 regBwOpMode = BW_OPMODE_5G | BW_OPMODE_20MHZ;
517 regRATR = RATE_ALL_OFDM_AG;
518 regRRSR = RATE_ALL_OFDM_AG;
519 break;
520 case WIRELESS_MODE_G:
521 regBwOpMode = BW_OPMODE_20MHZ;
522 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
523 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
524 break;
525 case WIRELESS_MODE_AUTO:
526 case WIRELESS_MODE_N_24G:
527 regBwOpMode = BW_OPMODE_20MHZ;
528 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
529 RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
530 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
531 break;
532 case WIRELESS_MODE_N_5G:
533 regBwOpMode = BW_OPMODE_5G;
534 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS |
535 RATE_ALL_OFDM_2SS;
536 regRRSR = RATE_ALL_OFDM_AG;
537 break;
538 default:
539 regBwOpMode = BW_OPMODE_20MHZ;
540 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
541 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
542 break;
543 }
544
545 rtl92e_writeb(dev, BW_OPMODE, regBwOpMode);
546 {
547 u32 ratr_value;
548
549 ratr_value = regRATR;
550 if (priv->rf_type == RF_1T2R)
551 ratr_value &= ~(RATE_ALL_OFDM_2SS);
552 rtl92e_writel(dev, RATR0, ratr_value);
553 rtl92e_writeb(dev, UFWP, 1);
554 }
555 regTmp = rtl92e_readb(dev, 0x313);
556 regRRSR = ((regTmp) << 24) | (regRRSR & 0x00ffffff);
557 rtl92e_writel(dev, RRSR, regRRSR);
558
559 rtl92e_writew(dev, RETRY_LIMIT,
560 priv->short_retry_limit << RETRY_LIMIT_SHORT_SHIFT |
561 priv->long_retry_limit << RETRY_LIMIT_LONG_SHIFT);
562 }
563
rtl92e_start_adapter(struct net_device * dev)564 bool rtl92e_start_adapter(struct net_device *dev)
565 {
566 struct r8192_priv *priv = rtllib_priv(dev);
567 u32 ulRegRead;
568 bool rtStatus = true;
569 u8 tmpvalue;
570 u8 ICVersion, SwitchingRegulatorOutput;
571 bool bfirmwareok = true;
572 u32 tmpRegA, TempCCk;
573 int i = 0;
574 u32 retry_times = 0;
575
576 priv->being_init_adapter = true;
577
578 start:
579 rtl92e_reset_desc_ring(dev);
580 priv->rf_mode = RF_OP_By_SW_3wire;
581 if (priv->rst_progress == RESET_TYPE_NORESET) {
582 rtl92e_writeb(dev, ANAPAR, 0x37);
583 mdelay(500);
584 }
585 priv->fw_info->status = FW_STATUS_0_INIT;
586
587 ulRegRead = rtl92e_readl(dev, CPU_GEN);
588 if (priv->fw_info->status == FW_STATUS_0_INIT)
589 ulRegRead |= CPU_GEN_SYSTEM_RESET;
590 else if (priv->fw_info->status == FW_STATUS_5_READY)
591 ulRegRead |= CPU_GEN_FIRMWARE_RESET;
592 else
593 netdev_err(dev, "%s(): undefined firmware state: %d.\n",
594 __func__, priv->fw_info->status);
595
596 rtl92e_writel(dev, CPU_GEN, ulRegRead);
597
598 ICVersion = rtl92e_readb(dev, IC_VERRSION);
599 if (ICVersion >= 0x4) {
600 SwitchingRegulatorOutput = rtl92e_readb(dev, SWREGULATOR);
601 if (SwitchingRegulatorOutput != 0xb8) {
602 rtl92e_writeb(dev, SWREGULATOR, 0xa8);
603 mdelay(1);
604 rtl92e_writeb(dev, SWREGULATOR, 0xb8);
605 }
606 }
607 rtStatus = rtl92e_config_bb(dev);
608 if (!rtStatus) {
609 netdev_warn(dev, "%s(): Failed to configure BB\n", __func__);
610 return rtStatus;
611 }
612
613 priv->loopback_mode = RTL819X_NO_LOOPBACK;
614 if (priv->rst_progress == RESET_TYPE_NORESET) {
615 ulRegRead = rtl92e_readl(dev, CPU_GEN);
616 if (priv->loopback_mode == RTL819X_NO_LOOPBACK)
617 ulRegRead = (ulRegRead & CPU_GEN_NO_LOOPBACK_MSK) |
618 CPU_GEN_NO_LOOPBACK_SET;
619 else if (priv->loopback_mode == RTL819X_MAC_LOOPBACK)
620 ulRegRead |= CPU_CCK_LOOPBACK;
621 else
622 netdev_err(dev, "%s: Invalid loopback mode setting.\n",
623 __func__);
624
625 rtl92e_writel(dev, CPU_GEN, ulRegRead);
626
627 udelay(500);
628 }
629 _rtl92e_hwconfig(dev);
630 rtl92e_writeb(dev, CMDR, CR_RE | CR_TE);
631
632 rtl92e_writeb(dev, PCIF, ((MXDMA2_NO_LIMIT << MXDMA2_RX_SHIFT) |
633 (MXDMA2_NO_LIMIT << MXDMA2_TX_SHIFT)));
634 rtl92e_writel(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
635 rtl92e_writew(dev, MAC4, ((u16 *)(dev->dev_addr + 4))[0]);
636 rtl92e_writel(dev, RCR, priv->receive_config);
637
638 rtl92e_writel(dev, RQPN1, NUM_OF_PAGE_IN_FW_QUEUE_BK <<
639 RSVD_FW_QUEUE_PAGE_BK_SHIFT |
640 NUM_OF_PAGE_IN_FW_QUEUE_BE <<
641 RSVD_FW_QUEUE_PAGE_BE_SHIFT |
642 NUM_OF_PAGE_IN_FW_QUEUE_VI <<
643 RSVD_FW_QUEUE_PAGE_VI_SHIFT |
644 NUM_OF_PAGE_IN_FW_QUEUE_VO <<
645 RSVD_FW_QUEUE_PAGE_VO_SHIFT);
646 rtl92e_writel(dev, RQPN2, NUM_OF_PAGE_IN_FW_QUEUE_MGNT <<
647 RSVD_FW_QUEUE_PAGE_MGNT_SHIFT);
648 rtl92e_writel(dev, RQPN3, APPLIED_RESERVED_QUEUE_IN_FW |
649 NUM_OF_PAGE_IN_FW_QUEUE_BCN <<
650 RSVD_FW_QUEUE_PAGE_BCN_SHIFT|
651 NUM_OF_PAGE_IN_FW_QUEUE_PUB <<
652 RSVD_FW_QUEUE_PAGE_PUB_SHIFT);
653
654 rtl92e_tx_enable(dev);
655 rtl92e_rx_enable(dev);
656 ulRegRead = (0xFFF00000 & rtl92e_readl(dev, RRSR)) |
657 RATE_ALL_OFDM_AG | RATE_ALL_CCK;
658 rtl92e_writel(dev, RRSR, ulRegRead);
659 rtl92e_writel(dev, RATR0+4*7, (RATE_ALL_OFDM_AG | RATE_ALL_CCK));
660
661 rtl92e_writeb(dev, ACK_TIMEOUT, 0x30);
662
663 if (priv->rst_progress == RESET_TYPE_NORESET)
664 rtl92e_set_wireless_mode(dev, priv->rtllib->mode);
665 rtl92e_cam_reset(dev);
666 {
667 u8 SECR_value = 0x0;
668
669 SECR_value |= SCR_TxEncEnable;
670 SECR_value |= SCR_RxDecEnable;
671 SECR_value |= SCR_NoSKMC;
672 rtl92e_writeb(dev, SECR, SECR_value);
673 }
674 rtl92e_writew(dev, ATIMWND, 2);
675 rtl92e_writew(dev, BCN_INTERVAL, 100);
676
677 for (i = 0; i < QOS_QUEUE_NUM; i++)
678 rtl92e_writel(dev, WDCAPARA_ADD[i], 0x005e4332);
679
680 rtl92e_writeb(dev, 0xbe, 0xc0);
681
682 rtl92e_config_mac(dev);
683
684 if (priv->card_8192_version > VERSION_8190_BD) {
685 rtl92e_get_tx_power(dev);
686 rtl92e_set_tx_power(dev, priv->chan);
687 }
688
689 tmpvalue = rtl92e_readb(dev, IC_VERRSION);
690 priv->ic_cut = tmpvalue;
691
692 bfirmwareok = rtl92e_init_fw(dev);
693 if (!bfirmwareok) {
694 if (retry_times < 10) {
695 retry_times++;
696 goto start;
697 } else {
698 rtStatus = false;
699 goto end;
700 }
701 }
702
703 if (priv->rst_progress == RESET_TYPE_NORESET) {
704 rtStatus = rtl92e_config_phy(dev);
705 if (!rtStatus) {
706 netdev_info(dev, "RF Config failed\n");
707 return rtStatus;
708 }
709 }
710
711 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1);
712 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1);
713
714 rtl92e_writeb(dev, 0x87, 0x0);
715
716 if (priv->rtllib->rf_off_reason > RF_CHANGE_BY_PS) {
717 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
718 } else if (priv->rtllib->rf_off_reason >= RF_CHANGE_BY_IPS) {
719 rtl92e_set_rf_state(dev, rf_off, priv->rtllib->rf_off_reason);
720 } else {
721 priv->rtllib->rf_power_state = rf_on;
722 priv->rtllib->rf_off_reason = 0;
723 }
724
725 if (priv->rtllib->FwRWRF)
726 priv->rf_mode = RF_OP_By_FW;
727 else
728 priv->rf_mode = RF_OP_By_SW_3wire;
729
730 if (priv->rst_progress == RESET_TYPE_NORESET) {
731 rtl92e_dm_init_txpower_tracking(dev);
732
733 if (priv->ic_cut >= IC_VersionCut_D) {
734 tmpRegA = rtl92e_get_bb_reg(dev, rOFDM0_XATxIQImbalance,
735 bMaskDWord);
736 rtl92e_get_bb_reg(dev, rOFDM0_XCTxIQImbalance, bMaskDWord);
737
738 for (i = 0; i < TX_BB_GAIN_TABLE_LEN; i++) {
739 if (tmpRegA == dm_tx_bb_gain[i]) {
740 priv->rfa_txpowertrackingindex = i;
741 priv->rfa_txpowertrackingindex_real = i;
742 priv->rfa_txpowertracking_default =
743 priv->rfa_txpowertrackingindex;
744 break;
745 }
746 }
747
748 TempCCk = rtl92e_get_bb_reg(dev, rCCK0_TxFilter1,
749 bMaskByte2);
750
751 for (i = 0; i < CCK_TX_BB_GAIN_TABLE_LEN; i++) {
752 if (TempCCk == dm_cck_tx_bb_gain[i][0]) {
753 priv->cck_present_attn_20m_def = i;
754 break;
755 }
756 }
757 priv->cck_present_attn_40m_def = 0;
758 priv->cck_present_attn_diff = 0;
759 priv->cck_present_attn =
760 priv->cck_present_attn_20m_def;
761 priv->btxpower_tracking = false;
762 }
763 }
764 rtl92e_irq_enable(dev);
765 end:
766 priv->being_init_adapter = false;
767 return rtStatus;
768 }
769
_rtl92e_net_update(struct net_device * dev)770 static void _rtl92e_net_update(struct net_device *dev)
771 {
772
773 struct r8192_priv *priv = rtllib_priv(dev);
774 struct rtllib_network *net;
775 u16 BcnTimeCfg = 0, BcnCW = 6, BcnIFS = 0xf;
776 u16 rate_config = 0;
777
778 net = &priv->rtllib->current_network;
779 rtl92e_config_rate(dev, &rate_config);
780 priv->dot11_current_preamble_mode = PREAMBLE_AUTO;
781 priv->basic_rate = rate_config &= 0x15f;
782 rtl92e_writew(dev, BSSIDR, *(u16 *)net->bssid);
783 rtl92e_writel(dev, BSSIDR + 2, *(u32 *)(net->bssid + 2));
784
785 if (priv->rtllib->iw_mode == IW_MODE_ADHOC) {
786 rtl92e_writew(dev, ATIMWND, 2);
787 rtl92e_writew(dev, BCN_DMATIME, 256);
788 rtl92e_writew(dev, BCN_INTERVAL, net->beacon_interval);
789 rtl92e_writew(dev, BCN_DRV_EARLY_INT, 10);
790 rtl92e_writeb(dev, BCN_ERR_THRESH, 100);
791
792 BcnTimeCfg |= (BcnCW<<BCN_TCFG_CW_SHIFT);
793 BcnTimeCfg |= BcnIFS<<BCN_TCFG_IFS;
794
795 rtl92e_writew(dev, BCN_TCFG, BcnTimeCfg);
796 }
797 }
798
rtl92e_link_change(struct net_device * dev)799 void rtl92e_link_change(struct net_device *dev)
800 {
801 struct r8192_priv *priv = rtllib_priv(dev);
802 struct rtllib_device *ieee = priv->rtllib;
803
804 if (!priv->up)
805 return;
806
807 if (ieee->state == RTLLIB_LINKED) {
808 _rtl92e_net_update(dev);
809 priv->ops->update_ratr_table(dev);
810 if ((ieee->pairwise_key_type == KEY_TYPE_WEP40) ||
811 (ieee->pairwise_key_type == KEY_TYPE_WEP104))
812 rtl92e_enable_hw_security_config(dev);
813 } else {
814 rtl92e_writeb(dev, 0x173, 0);
815 }
816 _rtl92e_update_msr(dev);
817
818 if (ieee->iw_mode == IW_MODE_INFRA || ieee->iw_mode == IW_MODE_ADHOC) {
819 u32 reg;
820
821 reg = rtl92e_readl(dev, RCR);
822 if (priv->rtllib->state == RTLLIB_LINKED) {
823 if (ieee->intel_promiscuous_md_info.promiscuous_on)
824 ;
825 else
826 priv->receive_config = reg |= RCR_CBSSID;
827 } else
828 priv->receive_config = reg &= ~RCR_CBSSID;
829
830 rtl92e_writel(dev, RCR, reg);
831 }
832 }
833
rtl92e_set_monitor_mode(struct net_device * dev,bool bAllowAllDA,bool WriteIntoReg)834 void rtl92e_set_monitor_mode(struct net_device *dev, bool bAllowAllDA,
835 bool WriteIntoReg)
836 {
837 struct r8192_priv *priv = rtllib_priv(dev);
838
839 if (bAllowAllDA)
840 priv->receive_config |= RCR_AAP;
841 else
842 priv->receive_config &= ~RCR_AAP;
843
844 if (WriteIntoReg)
845 rtl92e_writel(dev, RCR, priv->receive_config);
846 }
847
_rtl92e_rate_mgn_to_hw(u8 rate)848 static u8 _rtl92e_rate_mgn_to_hw(u8 rate)
849 {
850 u8 ret = DESC90_RATE1M;
851
852 switch (rate) {
853 case MGN_1M:
854 ret = DESC90_RATE1M;
855 break;
856 case MGN_2M:
857 ret = DESC90_RATE2M;
858 break;
859 case MGN_5_5M:
860 ret = DESC90_RATE5_5M;
861 break;
862 case MGN_11M:
863 ret = DESC90_RATE11M;
864 break;
865 case MGN_6M:
866 ret = DESC90_RATE6M;
867 break;
868 case MGN_9M:
869 ret = DESC90_RATE9M;
870 break;
871 case MGN_12M:
872 ret = DESC90_RATE12M;
873 break;
874 case MGN_18M:
875 ret = DESC90_RATE18M;
876 break;
877 case MGN_24M:
878 ret = DESC90_RATE24M;
879 break;
880 case MGN_36M:
881 ret = DESC90_RATE36M;
882 break;
883 case MGN_48M:
884 ret = DESC90_RATE48M;
885 break;
886 case MGN_54M:
887 ret = DESC90_RATE54M;
888 break;
889 case MGN_MCS0:
890 ret = DESC90_RATEMCS0;
891 break;
892 case MGN_MCS1:
893 ret = DESC90_RATEMCS1;
894 break;
895 case MGN_MCS2:
896 ret = DESC90_RATEMCS2;
897 break;
898 case MGN_MCS3:
899 ret = DESC90_RATEMCS3;
900 break;
901 case MGN_MCS4:
902 ret = DESC90_RATEMCS4;
903 break;
904 case MGN_MCS5:
905 ret = DESC90_RATEMCS5;
906 break;
907 case MGN_MCS6:
908 ret = DESC90_RATEMCS6;
909 break;
910 case MGN_MCS7:
911 ret = DESC90_RATEMCS7;
912 break;
913 case MGN_MCS8:
914 ret = DESC90_RATEMCS8;
915 break;
916 case MGN_MCS9:
917 ret = DESC90_RATEMCS9;
918 break;
919 case MGN_MCS10:
920 ret = DESC90_RATEMCS10;
921 break;
922 case MGN_MCS11:
923 ret = DESC90_RATEMCS11;
924 break;
925 case MGN_MCS12:
926 ret = DESC90_RATEMCS12;
927 break;
928 case MGN_MCS13:
929 ret = DESC90_RATEMCS13;
930 break;
931 case MGN_MCS14:
932 ret = DESC90_RATEMCS14;
933 break;
934 case MGN_MCS15:
935 ret = DESC90_RATEMCS15;
936 break;
937 case (0x80|0x20):
938 ret = DESC90_RATEMCS32;
939 break;
940 default:
941 break;
942 }
943 return ret;
944 }
945
_rtl92e_hw_queue_to_fw_queue(struct net_device * dev,u8 QueueID,u8 priority)946 static u8 _rtl92e_hw_queue_to_fw_queue(struct net_device *dev, u8 QueueID,
947 u8 priority)
948 {
949 u8 QueueSelect = 0x0;
950
951 switch (QueueID) {
952 case BE_QUEUE:
953 QueueSelect = QSLT_BE;
954 break;
955
956 case BK_QUEUE:
957 QueueSelect = QSLT_BK;
958 break;
959
960 case VO_QUEUE:
961 QueueSelect = QSLT_VO;
962 break;
963
964 case VI_QUEUE:
965 QueueSelect = QSLT_VI;
966 break;
967 case MGNT_QUEUE:
968 QueueSelect = QSLT_MGNT;
969 break;
970 case BEACON_QUEUE:
971 QueueSelect = QSLT_BEACON;
972 break;
973 case TXCMD_QUEUE:
974 QueueSelect = QSLT_CMD;
975 break;
976 case HIGH_QUEUE:
977 QueueSelect = QSLT_HIGH;
978 break;
979 default:
980 netdev_warn(dev, "%s(): Impossible Queue Selection: %d\n",
981 __func__, QueueID);
982 break;
983 }
984 return QueueSelect;
985 }
986
_rtl92e_query_is_short(u8 TxHT,u8 TxRate,struct cb_desc * tcb_desc)987 static u8 _rtl92e_query_is_short(u8 TxHT, u8 TxRate, struct cb_desc *tcb_desc)
988 {
989 u8 tmp_Short;
990
991 tmp_Short = (TxHT == 1) ? ((tcb_desc->bUseShortGI) ? 1 : 0) :
992 ((tcb_desc->bUseShortPreamble) ? 1 : 0);
993 if (TxHT == 1 && TxRate != DESC90_RATEMCS15)
994 tmp_Short = 0;
995
996 return tmp_Short;
997 }
998
rtl92e_fill_tx_desc(struct net_device * dev,struct tx_desc * pdesc,struct cb_desc * cb_desc,struct sk_buff * skb)999 void rtl92e_fill_tx_desc(struct net_device *dev, struct tx_desc *pdesc,
1000 struct cb_desc *cb_desc, struct sk_buff *skb)
1001 {
1002 struct r8192_priv *priv = rtllib_priv(dev);
1003 dma_addr_t mapping;
1004 struct tx_fwinfo_8190pci *pTxFwInfo;
1005
1006 pTxFwInfo = (struct tx_fwinfo_8190pci *)skb->data;
1007 memset(pTxFwInfo, 0, sizeof(struct tx_fwinfo_8190pci));
1008 pTxFwInfo->TxHT = (cb_desc->data_rate & 0x80) ? 1 : 0;
1009 pTxFwInfo->TxRate = _rtl92e_rate_mgn_to_hw(cb_desc->data_rate);
1010 pTxFwInfo->EnableCPUDur = cb_desc->bTxEnableFwCalcDur;
1011 pTxFwInfo->Short = _rtl92e_query_is_short(pTxFwInfo->TxHT,
1012 pTxFwInfo->TxRate, cb_desc);
1013
1014 if (cb_desc->bAMPDUEnable) {
1015 pTxFwInfo->AllowAggregation = 1;
1016 pTxFwInfo->RxMF = cb_desc->ampdu_factor;
1017 pTxFwInfo->RxAMD = cb_desc->ampdu_density;
1018 } else {
1019 pTxFwInfo->AllowAggregation = 0;
1020 pTxFwInfo->RxMF = 0;
1021 pTxFwInfo->RxAMD = 0;
1022 }
1023
1024 pTxFwInfo->RtsEnable = (cb_desc->bRTSEnable) ? 1 : 0;
1025 pTxFwInfo->CtsEnable = (cb_desc->bCTSEnable) ? 1 : 0;
1026 pTxFwInfo->RtsSTBC = (cb_desc->bRTSSTBC) ? 1 : 0;
1027 pTxFwInfo->RtsHT = (cb_desc->rts_rate&0x80) ? 1 : 0;
1028 pTxFwInfo->RtsRate = _rtl92e_rate_mgn_to_hw(cb_desc->rts_rate);
1029 pTxFwInfo->RtsBandwidth = 0;
1030 pTxFwInfo->RtsSubcarrier = cb_desc->RTSSC;
1031 pTxFwInfo->RtsShort = (pTxFwInfo->RtsHT == 0) ?
1032 (cb_desc->bRTSUseShortPreamble ? 1 : 0) :
1033 (cb_desc->bRTSUseShortGI ? 1 : 0);
1034 if (priv->current_chnl_bw == HT_CHANNEL_WIDTH_20_40) {
1035 if (cb_desc->bPacketBW) {
1036 pTxFwInfo->TxBandwidth = 1;
1037 pTxFwInfo->TxSubCarrier = 0;
1038 } else {
1039 pTxFwInfo->TxBandwidth = 0;
1040 pTxFwInfo->TxSubCarrier = priv->n_cur_40mhz_prime_sc;
1041 }
1042 } else {
1043 pTxFwInfo->TxBandwidth = 0;
1044 pTxFwInfo->TxSubCarrier = 0;
1045 }
1046
1047 memset((u8 *)pdesc, 0, 12);
1048
1049 mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
1050 DMA_TO_DEVICE);
1051 if (dma_mapping_error(&priv->pdev->dev, mapping)) {
1052 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1053 return;
1054 }
1055
1056 pdesc->LINIP = 0;
1057 pdesc->CmdInit = 1;
1058 pdesc->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1059 pdesc->PktSize = skb->len - sizeof(struct tx_fwinfo_8190pci);
1060
1061 pdesc->SecCAMID = 0;
1062 pdesc->RATid = cb_desc->RATRIndex;
1063
1064
1065 pdesc->NoEnc = 1;
1066 pdesc->SecType = 0x0;
1067 if (cb_desc->bHwSec) {
1068 static u8 tmp;
1069
1070 if (!tmp)
1071 tmp = 1;
1072 switch (priv->rtllib->pairwise_key_type) {
1073 case KEY_TYPE_WEP40:
1074 case KEY_TYPE_WEP104:
1075 pdesc->SecType = 0x1;
1076 pdesc->NoEnc = 0;
1077 break;
1078 case KEY_TYPE_TKIP:
1079 pdesc->SecType = 0x2;
1080 pdesc->NoEnc = 0;
1081 break;
1082 case KEY_TYPE_CCMP:
1083 pdesc->SecType = 0x3;
1084 pdesc->NoEnc = 0;
1085 break;
1086 case KEY_TYPE_NA:
1087 pdesc->SecType = 0x0;
1088 pdesc->NoEnc = 1;
1089 break;
1090 }
1091 }
1092
1093 pdesc->PktId = 0x0;
1094
1095 pdesc->QueueSelect = _rtl92e_hw_queue_to_fw_queue(dev,
1096 cb_desc->queue_index,
1097 cb_desc->priority);
1098 pdesc->TxFWInfoSize = sizeof(struct tx_fwinfo_8190pci);
1099
1100 pdesc->DISFB = cb_desc->tx_dis_rate_fallback;
1101 pdesc->USERATE = cb_desc->tx_use_drv_assinged_rate;
1102
1103 pdesc->FirstSeg = 1;
1104 pdesc->LastSeg = 1;
1105 pdesc->TxBufferSize = skb->len;
1106
1107 pdesc->TxBuffAddr = mapping;
1108 }
1109
rtl92e_fill_tx_cmd_desc(struct net_device * dev,struct tx_desc_cmd * entry,struct cb_desc * cb_desc,struct sk_buff * skb)1110 void rtl92e_fill_tx_cmd_desc(struct net_device *dev, struct tx_desc_cmd *entry,
1111 struct cb_desc *cb_desc, struct sk_buff *skb)
1112 {
1113 struct r8192_priv *priv = rtllib_priv(dev);
1114 dma_addr_t mapping = dma_map_single(&priv->pdev->dev, skb->data,
1115 skb->len, DMA_TO_DEVICE);
1116
1117 if (dma_mapping_error(&priv->pdev->dev, mapping))
1118 netdev_err(dev, "%s(): DMA Mapping error\n", __func__);
1119 memset(entry, 0, 12);
1120 entry->LINIP = cb_desc->bLastIniPkt;
1121 entry->FirstSeg = 1;
1122 entry->LastSeg = 1;
1123 if (cb_desc->bCmdOrInit == DESC_PACKET_TYPE_INIT) {
1124 entry->CmdInit = DESC_PACKET_TYPE_INIT;
1125 } else {
1126 struct tx_desc *entry_tmp = (struct tx_desc *)entry;
1127
1128 entry_tmp->CmdInit = DESC_PACKET_TYPE_NORMAL;
1129 entry_tmp->Offset = sizeof(struct tx_fwinfo_8190pci) + 8;
1130 entry_tmp->PktSize = cb_desc->pkt_size + entry_tmp->Offset;
1131 entry_tmp->QueueSelect = QSLT_CMD;
1132 entry_tmp->TxFWInfoSize = 0x08;
1133 entry_tmp->RATid = DESC_PACKET_TYPE_INIT;
1134 }
1135 entry->TxBufferSize = skb->len;
1136 entry->TxBuffAddr = mapping;
1137 entry->OWN = 1;
1138 }
1139
_rtl92e_rate_hw_to_mgn(bool bIsHT,u8 rate)1140 static u8 _rtl92e_rate_hw_to_mgn(bool bIsHT, u8 rate)
1141 {
1142 u8 ret_rate = 0x02;
1143
1144 if (!bIsHT) {
1145 switch (rate) {
1146 case DESC90_RATE1M:
1147 ret_rate = MGN_1M;
1148 break;
1149 case DESC90_RATE2M:
1150 ret_rate = MGN_2M;
1151 break;
1152 case DESC90_RATE5_5M:
1153 ret_rate = MGN_5_5M;
1154 break;
1155 case DESC90_RATE11M:
1156 ret_rate = MGN_11M;
1157 break;
1158 case DESC90_RATE6M:
1159 ret_rate = MGN_6M;
1160 break;
1161 case DESC90_RATE9M:
1162 ret_rate = MGN_9M;
1163 break;
1164 case DESC90_RATE12M:
1165 ret_rate = MGN_12M;
1166 break;
1167 case DESC90_RATE18M:
1168 ret_rate = MGN_18M;
1169 break;
1170 case DESC90_RATE24M:
1171 ret_rate = MGN_24M;
1172 break;
1173 case DESC90_RATE36M:
1174 ret_rate = MGN_36M;
1175 break;
1176 case DESC90_RATE48M:
1177 ret_rate = MGN_48M;
1178 break;
1179 case DESC90_RATE54M:
1180 ret_rate = MGN_54M;
1181 break;
1182 }
1183
1184 } else {
1185 switch (rate) {
1186 case DESC90_RATEMCS0:
1187 ret_rate = MGN_MCS0;
1188 break;
1189 case DESC90_RATEMCS1:
1190 ret_rate = MGN_MCS1;
1191 break;
1192 case DESC90_RATEMCS2:
1193 ret_rate = MGN_MCS2;
1194 break;
1195 case DESC90_RATEMCS3:
1196 ret_rate = MGN_MCS3;
1197 break;
1198 case DESC90_RATEMCS4:
1199 ret_rate = MGN_MCS4;
1200 break;
1201 case DESC90_RATEMCS5:
1202 ret_rate = MGN_MCS5;
1203 break;
1204 case DESC90_RATEMCS6:
1205 ret_rate = MGN_MCS6;
1206 break;
1207 case DESC90_RATEMCS7:
1208 ret_rate = MGN_MCS7;
1209 break;
1210 case DESC90_RATEMCS8:
1211 ret_rate = MGN_MCS8;
1212 break;
1213 case DESC90_RATEMCS9:
1214 ret_rate = MGN_MCS9;
1215 break;
1216 case DESC90_RATEMCS10:
1217 ret_rate = MGN_MCS10;
1218 break;
1219 case DESC90_RATEMCS11:
1220 ret_rate = MGN_MCS11;
1221 break;
1222 case DESC90_RATEMCS12:
1223 ret_rate = MGN_MCS12;
1224 break;
1225 case DESC90_RATEMCS13:
1226 ret_rate = MGN_MCS13;
1227 break;
1228 case DESC90_RATEMCS14:
1229 ret_rate = MGN_MCS14;
1230 break;
1231 case DESC90_RATEMCS15:
1232 ret_rate = MGN_MCS15;
1233 break;
1234 case DESC90_RATEMCS32:
1235 ret_rate = 0x80 | 0x20;
1236 break;
1237 }
1238 }
1239
1240 return ret_rate;
1241 }
1242
_rtl92e_signal_scale_mapping(struct r8192_priv * priv,long currsig)1243 static long _rtl92e_signal_scale_mapping(struct r8192_priv *priv, long currsig)
1244 {
1245 long retsig;
1246
1247 if (currsig >= 61 && currsig <= 100)
1248 retsig = 90 + ((currsig - 60) / 4);
1249 else if (currsig >= 41 && currsig <= 60)
1250 retsig = 78 + ((currsig - 40) / 2);
1251 else if (currsig >= 31 && currsig <= 40)
1252 retsig = 66 + (currsig - 30);
1253 else if (currsig >= 21 && currsig <= 30)
1254 retsig = 54 + (currsig - 20);
1255 else if (currsig >= 5 && currsig <= 20)
1256 retsig = 42 + (((currsig - 5) * 2) / 3);
1257 else if (currsig == 4)
1258 retsig = 36;
1259 else if (currsig == 3)
1260 retsig = 27;
1261 else if (currsig == 2)
1262 retsig = 18;
1263 else if (currsig == 1)
1264 retsig = 9;
1265 else
1266 retsig = currsig;
1267
1268 return retsig;
1269 }
1270
1271
1272 #define rx_hal_is_cck_rate(_pdrvinfo)\
1273 ((_pdrvinfo->RxRate == DESC90_RATE1M ||\
1274 _pdrvinfo->RxRate == DESC90_RATE2M ||\
1275 _pdrvinfo->RxRate == DESC90_RATE5_5M ||\
1276 _pdrvinfo->RxRate == DESC90_RATE11M) &&\
1277 !_pdrvinfo->RxHT)
1278
_rtl92e_query_rxphystatus(struct r8192_priv * priv,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo,struct rtllib_rx_stats * precord_stats,bool bpacket_match_bssid,bool bpacket_toself,bool bPacketBeacon,bool bToSelfBA)1279 static void _rtl92e_query_rxphystatus(
1280 struct r8192_priv *priv,
1281 struct rtllib_rx_stats *pstats,
1282 struct rx_desc *pdesc,
1283 struct rx_fwinfo *pdrvinfo,
1284 struct rtllib_rx_stats *precord_stats,
1285 bool bpacket_match_bssid,
1286 bool bpacket_toself,
1287 bool bPacketBeacon,
1288 bool bToSelfBA
1289 )
1290 {
1291 struct phy_sts_ofdm_819xpci *pofdm_buf;
1292 struct phy_sts_cck_819xpci *pcck_buf;
1293 u8 *prxpkt;
1294 u8 i, max_spatial_stream, tmp_rxevm;
1295 s8 rx_pwr[4], rx_pwr_all = 0;
1296 s8 rx_evmX;
1297 u8 evm, pwdb_all;
1298 u32 RSSI, total_rssi = 0;
1299 u8 is_cck_rate = 0;
1300 u8 rf_rx_num = 0;
1301 static u8 check_reg824;
1302 static u32 reg824_bit9;
1303
1304 is_cck_rate = rx_hal_is_cck_rate(pdrvinfo);
1305 memset(precord_stats, 0, sizeof(struct rtllib_rx_stats));
1306 pstats->bPacketMatchBSSID = precord_stats->bPacketMatchBSSID =
1307 bpacket_match_bssid;
1308 pstats->bPacketToSelf = precord_stats->bPacketToSelf = bpacket_toself;
1309 pstats->bIsCCK = precord_stats->bIsCCK = is_cck_rate;
1310 pstats->bPacketBeacon = precord_stats->bPacketBeacon = bPacketBeacon;
1311 pstats->bToSelfBA = precord_stats->bToSelfBA = bToSelfBA;
1312 if (check_reg824 == 0) {
1313 reg824_bit9 = rtl92e_get_bb_reg(priv->rtllib->dev,
1314 rFPGA0_XA_HSSIParameter2,
1315 0x200);
1316 check_reg824 = 1;
1317 }
1318
1319
1320 prxpkt = (u8 *)pdrvinfo;
1321
1322 prxpkt += sizeof(struct rx_fwinfo);
1323
1324 pcck_buf = (struct phy_sts_cck_819xpci *)prxpkt;
1325 pofdm_buf = (struct phy_sts_ofdm_819xpci *)prxpkt;
1326
1327 pstats->RxMIMOSignalQuality[0] = -1;
1328 pstats->RxMIMOSignalQuality[1] = -1;
1329 precord_stats->RxMIMOSignalQuality[0] = -1;
1330 precord_stats->RxMIMOSignalQuality[1] = -1;
1331
1332 if (is_cck_rate) {
1333 u8 report;
1334
1335 if (!reg824_bit9) {
1336 report = pcck_buf->cck_agc_rpt & 0xc0;
1337 report >>= 6;
1338 switch (report) {
1339 case 0x3:
1340 rx_pwr_all = -35 - (pcck_buf->cck_agc_rpt &
1341 0x3e);
1342 break;
1343 case 0x2:
1344 rx_pwr_all = -23 - (pcck_buf->cck_agc_rpt &
1345 0x3e);
1346 break;
1347 case 0x1:
1348 rx_pwr_all = -11 - (pcck_buf->cck_agc_rpt &
1349 0x3e);
1350 break;
1351 case 0x0:
1352 rx_pwr_all = 8 - (pcck_buf->cck_agc_rpt & 0x3e);
1353 break;
1354 }
1355 } else {
1356 report = pcck_buf->cck_agc_rpt & 0x60;
1357 report >>= 5;
1358 switch (report) {
1359 case 0x3:
1360 rx_pwr_all = -35 -
1361 ((pcck_buf->cck_agc_rpt &
1362 0x1f) << 1);
1363 break;
1364 case 0x2:
1365 rx_pwr_all = -23 -
1366 ((pcck_buf->cck_agc_rpt &
1367 0x1f) << 1);
1368 break;
1369 case 0x1:
1370 rx_pwr_all = -11 -
1371 ((pcck_buf->cck_agc_rpt &
1372 0x1f) << 1);
1373 break;
1374 case 0x0:
1375 rx_pwr_all = -8 -
1376 ((pcck_buf->cck_agc_rpt &
1377 0x1f) << 1);
1378 break;
1379 }
1380 }
1381
1382 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1383 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1384 pstats->RecvSignalPower = rx_pwr_all;
1385
1386 if (bpacket_match_bssid) {
1387 u8 sq;
1388
1389 if (pstats->RxPWDBAll > 40) {
1390 sq = 100;
1391 } else {
1392 sq = pcck_buf->sq_rpt;
1393
1394 if (pcck_buf->sq_rpt > 64)
1395 sq = 0;
1396 else if (pcck_buf->sq_rpt < 20)
1397 sq = 100;
1398 else
1399 sq = ((64-sq) * 100) / 44;
1400 }
1401 pstats->SignalQuality = sq;
1402 precord_stats->SignalQuality = sq;
1403 pstats->RxMIMOSignalQuality[0] = sq;
1404 precord_stats->RxMIMOSignalQuality[0] = sq;
1405 pstats->RxMIMOSignalQuality[1] = -1;
1406 precord_stats->RxMIMOSignalQuality[1] = -1;
1407 }
1408 } else {
1409 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
1410 if (priv->brfpath_rxenable[i])
1411 rf_rx_num++;
1412
1413 rx_pwr[i] = ((pofdm_buf->trsw_gain_X[i] & 0x3F) *
1414 2) - 110;
1415
1416 RSSI = rtl92e_rx_db_to_percent(rx_pwr[i]);
1417 if (priv->brfpath_rxenable[i])
1418 total_rssi += RSSI;
1419
1420 if (bpacket_match_bssid) {
1421 pstats->RxMIMOSignalStrength[i] = RSSI;
1422 precord_stats->RxMIMOSignalStrength[i] = RSSI;
1423 }
1424 }
1425
1426
1427 rx_pwr_all = (((pofdm_buf->pwdb_all) >> 1) & 0x7f) - 106;
1428 pwdb_all = rtl92e_rx_db_to_percent(rx_pwr_all);
1429
1430 pstats->RxPWDBAll = precord_stats->RxPWDBAll = pwdb_all;
1431 pstats->RxPower = precord_stats->RxPower = rx_pwr_all;
1432 pstats->RecvSignalPower = rx_pwr_all;
1433 if (pdrvinfo->RxHT && pdrvinfo->RxRate >= DESC90_RATEMCS8 &&
1434 pdrvinfo->RxRate <= DESC90_RATEMCS15)
1435 max_spatial_stream = 2;
1436 else
1437 max_spatial_stream = 1;
1438
1439 for (i = 0; i < max_spatial_stream; i++) {
1440 tmp_rxevm = pofdm_buf->rxevm_X[i];
1441 rx_evmX = (s8)(tmp_rxevm);
1442
1443 rx_evmX /= 2;
1444
1445 evm = rtl92e_evm_db_to_percent(rx_evmX);
1446 if (bpacket_match_bssid) {
1447 if (i == 0) {
1448 pstats->SignalQuality = evm & 0xff;
1449 precord_stats->SignalQuality = evm & 0xff;
1450 }
1451 pstats->RxMIMOSignalQuality[i] = evm & 0xff;
1452 precord_stats->RxMIMOSignalQuality[i] = evm & 0xff;
1453 }
1454 }
1455 }
1456
1457 if (is_cck_rate) {
1458 pstats->SignalStrength = precord_stats->SignalStrength =
1459 _rtl92e_signal_scale_mapping(priv,
1460 (long)pwdb_all);
1461
1462 } else {
1463 if (rf_rx_num != 0)
1464 pstats->SignalStrength = precord_stats->SignalStrength =
1465 _rtl92e_signal_scale_mapping(priv,
1466 (long)(total_rssi /= rf_rx_num));
1467 }
1468 }
1469
_rtl92e_process_phyinfo(struct r8192_priv * priv,u8 * buffer,struct rtllib_rx_stats * prev_st,struct rtllib_rx_stats * curr_st)1470 static void _rtl92e_process_phyinfo(struct r8192_priv *priv, u8 *buffer,
1471 struct rtllib_rx_stats *prev_st,
1472 struct rtllib_rx_stats *curr_st)
1473 {
1474 bool bcheck = false;
1475 u8 rfpath;
1476 u32 ij, tmp_val;
1477 static u32 slide_rssi_index, slide_rssi_statistics;
1478 static u32 slide_evm_index, slide_evm_statistics;
1479 static u32 last_rssi, last_evm;
1480 static u32 slide_beacon_adc_pwdb_index;
1481 static u32 slide_beacon_adc_pwdb_statistics;
1482 static u32 last_beacon_adc_pwdb;
1483 struct rtllib_hdr_3addr *hdr;
1484 u16 sc;
1485 unsigned int seq;
1486
1487 hdr = (struct rtllib_hdr_3addr *)buffer;
1488 sc = le16_to_cpu(hdr->seq_ctl);
1489 seq = WLAN_GET_SEQ_SEQ(sc);
1490 curr_st->Seq_Num = seq;
1491 if (!prev_st->bIsAMPDU)
1492 bcheck = true;
1493
1494 if (slide_rssi_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1495 slide_rssi_statistics = PHY_RSSI_SLID_WIN_MAX;
1496 last_rssi = priv->stats.slide_signal_strength[slide_rssi_index];
1497 priv->stats.slide_rssi_total -= last_rssi;
1498 }
1499 priv->stats.slide_rssi_total += prev_st->SignalStrength;
1500
1501 priv->stats.slide_signal_strength[slide_rssi_index++] =
1502 prev_st->SignalStrength;
1503 if (slide_rssi_index >= PHY_RSSI_SLID_WIN_MAX)
1504 slide_rssi_index = 0;
1505
1506 tmp_val = priv->stats.slide_rssi_total/slide_rssi_statistics;
1507 priv->stats.signal_strength = rtl92e_translate_to_dbm(priv, tmp_val);
1508 curr_st->rssi = priv->stats.signal_strength;
1509 if (!prev_st->bPacketMatchBSSID) {
1510 if (!prev_st->bToSelfBA)
1511 return;
1512 }
1513
1514 if (!bcheck)
1515 return;
1516
1517 if (!prev_st->bIsCCK && prev_st->bPacketToSelf) {
1518 for (rfpath = RF90_PATH_A; rfpath < RF90_PATH_C; rfpath++) {
1519 if (!rtl92e_is_legal_rf_path(priv->rtllib->dev, rfpath))
1520 continue;
1521 if (priv->stats.rx_rssi_percentage[rfpath] == 0) {
1522 priv->stats.rx_rssi_percentage[rfpath] =
1523 prev_st->RxMIMOSignalStrength[rfpath];
1524 }
1525 if (prev_st->RxMIMOSignalStrength[rfpath] >
1526 priv->stats.rx_rssi_percentage[rfpath]) {
1527 priv->stats.rx_rssi_percentage[rfpath] =
1528 ((priv->stats.rx_rssi_percentage[rfpath]
1529 * (RX_SMOOTH - 1)) +
1530 (prev_st->RxMIMOSignalStrength
1531 [rfpath])) / (RX_SMOOTH);
1532 priv->stats.rx_rssi_percentage[rfpath] =
1533 priv->stats.rx_rssi_percentage[rfpath]
1534 + 1;
1535 } else {
1536 priv->stats.rx_rssi_percentage[rfpath] =
1537 ((priv->stats.rx_rssi_percentage[rfpath] *
1538 (RX_SMOOTH-1)) +
1539 (prev_st->RxMIMOSignalStrength[rfpath])) /
1540 (RX_SMOOTH);
1541 }
1542 }
1543 }
1544
1545
1546 if (prev_st->bPacketBeacon) {
1547 if (slide_beacon_adc_pwdb_statistics++ >=
1548 PHY_Beacon_RSSI_SLID_WIN_MAX) {
1549 slide_beacon_adc_pwdb_statistics =
1550 PHY_Beacon_RSSI_SLID_WIN_MAX;
1551 last_beacon_adc_pwdb = priv->stats.slide_beacon_pwdb
1552 [slide_beacon_adc_pwdb_index];
1553 priv->stats.slide_beacon_total -= last_beacon_adc_pwdb;
1554 }
1555 priv->stats.slide_beacon_total += prev_st->RxPWDBAll;
1556 priv->stats.slide_beacon_pwdb[slide_beacon_adc_pwdb_index] =
1557 prev_st->RxPWDBAll;
1558 slide_beacon_adc_pwdb_index++;
1559 if (slide_beacon_adc_pwdb_index >= PHY_Beacon_RSSI_SLID_WIN_MAX)
1560 slide_beacon_adc_pwdb_index = 0;
1561 prev_st->RxPWDBAll = priv->stats.slide_beacon_total /
1562 slide_beacon_adc_pwdb_statistics;
1563 if (prev_st->RxPWDBAll >= 3)
1564 prev_st->RxPWDBAll -= 3;
1565 }
1566 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1567 prev_st->bToSelfBA) {
1568 if (priv->undecorated_smoothed_pwdb < 0)
1569 priv->undecorated_smoothed_pwdb = prev_st->RxPWDBAll;
1570 if (prev_st->RxPWDBAll > (u32)priv->undecorated_smoothed_pwdb) {
1571 priv->undecorated_smoothed_pwdb =
1572 (((priv->undecorated_smoothed_pwdb) *
1573 (RX_SMOOTH-1)) +
1574 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1575 priv->undecorated_smoothed_pwdb =
1576 priv->undecorated_smoothed_pwdb + 1;
1577 } else {
1578 priv->undecorated_smoothed_pwdb =
1579 (((priv->undecorated_smoothed_pwdb) *
1580 (RX_SMOOTH-1)) +
1581 (prev_st->RxPWDBAll)) / (RX_SMOOTH);
1582 }
1583 rtl92e_update_rx_statistics(priv, prev_st);
1584 }
1585
1586 if (prev_st->SignalQuality != 0) {
1587 if (prev_st->bPacketToSelf || prev_st->bPacketBeacon ||
1588 prev_st->bToSelfBA) {
1589 if (slide_evm_statistics++ >= PHY_RSSI_SLID_WIN_MAX) {
1590 slide_evm_statistics = PHY_RSSI_SLID_WIN_MAX;
1591 last_evm =
1592 priv->stats.slide_evm[slide_evm_index];
1593 priv->stats.slide_evm_total -= last_evm;
1594 }
1595
1596 priv->stats.slide_evm_total += prev_st->SignalQuality;
1597
1598 priv->stats.slide_evm[slide_evm_index++] =
1599 prev_st->SignalQuality;
1600 if (slide_evm_index >= PHY_RSSI_SLID_WIN_MAX)
1601 slide_evm_index = 0;
1602
1603 tmp_val = priv->stats.slide_evm_total /
1604 slide_evm_statistics;
1605 priv->stats.last_signal_strength_inpercent = tmp_val;
1606 }
1607
1608 if (prev_st->bPacketToSelf ||
1609 prev_st->bPacketBeacon ||
1610 prev_st->bToSelfBA) {
1611 for (ij = 0; ij < 2; ij++) {
1612 if (prev_st->RxMIMOSignalQuality[ij] != -1) {
1613 if (priv->stats.rx_evm_percentage[ij] == 0)
1614 priv->stats.rx_evm_percentage[ij] =
1615 prev_st->RxMIMOSignalQuality[ij];
1616 priv->stats.rx_evm_percentage[ij] =
1617 ((priv->stats.rx_evm_percentage[ij] *
1618 (RX_SMOOTH - 1)) +
1619 (prev_st->RxMIMOSignalQuality[ij])) /
1620 (RX_SMOOTH);
1621 }
1622 }
1623 }
1624 }
1625 }
1626
_rtl92e_translate_rx_signal_stats(struct net_device * dev,struct sk_buff * skb,struct rtllib_rx_stats * pstats,struct rx_desc * pdesc,struct rx_fwinfo * pdrvinfo)1627 static void _rtl92e_translate_rx_signal_stats(struct net_device *dev,
1628 struct sk_buff *skb,
1629 struct rtllib_rx_stats *pstats,
1630 struct rx_desc *pdesc,
1631 struct rx_fwinfo *pdrvinfo)
1632 {
1633 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1634 bool bpacket_match_bssid, bpacket_toself;
1635 bool bPacketBeacon = false;
1636 struct rtllib_hdr_3addr *hdr;
1637 bool bToSelfBA = false;
1638 static struct rtllib_rx_stats previous_stats;
1639 u16 fc, type;
1640 u8 *tmp_buf;
1641 u8 *praddr;
1642
1643 tmp_buf = skb->data + pstats->RxDrvInfoSize + pstats->RxBufShift;
1644
1645 hdr = (struct rtllib_hdr_3addr *)tmp_buf;
1646 fc = le16_to_cpu(hdr->frame_ctl);
1647 type = WLAN_FC_GET_TYPE(fc);
1648 praddr = hdr->addr1;
1649
1650 bpacket_match_bssid =
1651 ((type != RTLLIB_FTYPE_CTL) &&
1652 ether_addr_equal(priv->rtllib->current_network.bssid,
1653 (fc & RTLLIB_FCTL_TODS) ? hdr->addr1 :
1654 (fc & RTLLIB_FCTL_FROMDS) ? hdr->addr2 :
1655 hdr->addr3) &&
1656 (!pstats->bHwError) && (!pstats->bCRC) && (!pstats->bICV));
1657 bpacket_toself = bpacket_match_bssid && /* check this */
1658 ether_addr_equal(praddr, priv->rtllib->dev->dev_addr);
1659 if (WLAN_FC_GET_FRAMETYPE(fc) == RTLLIB_STYPE_BEACON)
1660 bPacketBeacon = true;
1661 _rtl92e_process_phyinfo(priv, tmp_buf, &previous_stats, pstats);
1662 _rtl92e_query_rxphystatus(priv, pstats, pdesc, pdrvinfo,
1663 &previous_stats, bpacket_match_bssid,
1664 bpacket_toself, bPacketBeacon, bToSelfBA);
1665 rtl92e_copy_mpdu_stats(pstats, &previous_stats);
1666 }
1667
_rtl92e_update_received_rate_histogram_stats(struct net_device * dev,struct rtllib_rx_stats * pstats)1668 static void _rtl92e_update_received_rate_histogram_stats(
1669 struct net_device *dev,
1670 struct rtllib_rx_stats *pstats)
1671 {
1672 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1673 u32 rcvType = 1;
1674 u32 rateIndex;
1675
1676 if (pstats->bCRC)
1677 rcvType = 2;
1678 else if (pstats->bICV)
1679 rcvType = 3;
1680
1681 switch (pstats->rate) {
1682 case MGN_1M:
1683 rateIndex = 0;
1684 break;
1685 case MGN_2M:
1686 rateIndex = 1;
1687 break;
1688 case MGN_5_5M:
1689 rateIndex = 2;
1690 break;
1691 case MGN_11M:
1692 rateIndex = 3;
1693 break;
1694 case MGN_6M:
1695 rateIndex = 4;
1696 break;
1697 case MGN_9M:
1698 rateIndex = 5;
1699 break;
1700 case MGN_12M:
1701 rateIndex = 6;
1702 break;
1703 case MGN_18M:
1704 rateIndex = 7;
1705 break;
1706 case MGN_24M:
1707 rateIndex = 8;
1708 break;
1709 case MGN_36M:
1710 rateIndex = 9;
1711 break;
1712 case MGN_48M:
1713 rateIndex = 10;
1714 break;
1715 case MGN_54M:
1716 rateIndex = 11;
1717 break;
1718 case MGN_MCS0:
1719 rateIndex = 12;
1720 break;
1721 case MGN_MCS1:
1722 rateIndex = 13;
1723 break;
1724 case MGN_MCS2:
1725 rateIndex = 14;
1726 break;
1727 case MGN_MCS3:
1728 rateIndex = 15;
1729 break;
1730 case MGN_MCS4:
1731 rateIndex = 16;
1732 break;
1733 case MGN_MCS5:
1734 rateIndex = 17;
1735 break;
1736 case MGN_MCS6:
1737 rateIndex = 18;
1738 break;
1739 case MGN_MCS7:
1740 rateIndex = 19;
1741 break;
1742 case MGN_MCS8:
1743 rateIndex = 20;
1744 break;
1745 case MGN_MCS9:
1746 rateIndex = 21;
1747 break;
1748 case MGN_MCS10:
1749 rateIndex = 22;
1750 break;
1751 case MGN_MCS11:
1752 rateIndex = 23;
1753 break;
1754 case MGN_MCS12:
1755 rateIndex = 24;
1756 break;
1757 case MGN_MCS13:
1758 rateIndex = 25;
1759 break;
1760 case MGN_MCS14:
1761 rateIndex = 26;
1762 break;
1763 case MGN_MCS15:
1764 rateIndex = 27;
1765 break;
1766 default:
1767 rateIndex = 28;
1768 break;
1769 }
1770 priv->stats.received_rate_histogram[0][rateIndex]++;
1771 priv->stats.received_rate_histogram[rcvType][rateIndex]++;
1772 }
1773
rtl92e_get_rx_stats(struct net_device * dev,struct rtllib_rx_stats * stats,struct rx_desc * pdesc,struct sk_buff * skb)1774 bool rtl92e_get_rx_stats(struct net_device *dev, struct rtllib_rx_stats *stats,
1775 struct rx_desc *pdesc, struct sk_buff *skb)
1776 {
1777 struct rx_fwinfo *pDrvInfo = NULL;
1778
1779 stats->bICV = pdesc->ICV;
1780 stats->bCRC = pdesc->CRC32;
1781 stats->bHwError = pdesc->CRC32 | pdesc->ICV;
1782
1783 stats->Length = pdesc->Length;
1784 if (stats->Length < 24)
1785 stats->bHwError |= 1;
1786
1787 if (stats->bHwError) {
1788 stats->bShift = false;
1789 return false;
1790 }
1791
1792 stats->RxDrvInfoSize = pdesc->RxDrvInfoSize;
1793 stats->RxBufShift = (pdesc->Shift) & 0x03;
1794 stats->Decrypted = !pdesc->SWDec;
1795
1796 pDrvInfo = (struct rx_fwinfo *)(skb->data + stats->RxBufShift);
1797
1798 stats->rate = _rtl92e_rate_hw_to_mgn((bool)pDrvInfo->RxHT,
1799 pDrvInfo->RxRate);
1800 stats->bShortPreamble = pDrvInfo->SPLCP;
1801
1802 _rtl92e_update_received_rate_histogram_stats(dev, stats);
1803
1804 stats->bIsAMPDU = (pDrvInfo->PartAggr == 1);
1805 stats->bFirstMPDU = (pDrvInfo->PartAggr == 1) &&
1806 (pDrvInfo->FirstAGGR == 1);
1807
1808 stats->TimeStampLow = pDrvInfo->TSFL;
1809 stats->TimeStampHigh = rtl92e_readl(dev, TSFR+4);
1810
1811 rtl92e_update_rx_pkt_timestamp(dev, stats);
1812
1813 if ((stats->RxBufShift + stats->RxDrvInfoSize) > 0)
1814 stats->bShift = 1;
1815
1816 stats->RxIs40MHzPacket = pDrvInfo->BW;
1817
1818 _rtl92e_translate_rx_signal_stats(dev, skb, stats, pdesc, pDrvInfo);
1819 skb_trim(skb, skb->len - S_CRC_LEN);
1820
1821
1822 stats->packetlength = stats->Length-4;
1823 stats->fraglength = stats->packetlength;
1824 stats->fragoffset = 0;
1825 stats->ntotalfrag = 1;
1826 return true;
1827 }
1828
rtl92e_stop_adapter(struct net_device * dev,bool reset)1829 void rtl92e_stop_adapter(struct net_device *dev, bool reset)
1830 {
1831 struct r8192_priv *priv = rtllib_priv(dev);
1832 int i;
1833 u8 OpMode;
1834 u8 u1bTmp;
1835 u32 ulRegRead;
1836
1837 OpMode = RT_OP_MODE_NO_LINK;
1838 priv->rtllib->SetHwRegHandler(dev, HW_VAR_MEDIA_STATUS, &OpMode);
1839
1840 if (!priv->rtllib->bSupportRemoteWakeUp) {
1841 u1bTmp = 0x0;
1842 rtl92e_writeb(dev, CMDR, u1bTmp);
1843 }
1844
1845 mdelay(20);
1846
1847 if (!reset) {
1848 mdelay(150);
1849
1850 priv->hw_rf_off_action = 2;
1851
1852 if (!priv->rtllib->bSupportRemoteWakeUp) {
1853 rtl92e_set_rf_off(dev);
1854 ulRegRead = rtl92e_readl(dev, CPU_GEN);
1855 ulRegRead |= CPU_GEN_SYSTEM_RESET;
1856 rtl92e_writel(dev, CPU_GEN, ulRegRead);
1857 } else {
1858 rtl92e_writel(dev, WFCRC0, 0xffffffff);
1859 rtl92e_writel(dev, WFCRC1, 0xffffffff);
1860 rtl92e_writel(dev, WFCRC2, 0xffffffff);
1861
1862
1863 rtl92e_writeb(dev, PMR, 0x5);
1864 rtl92e_writeb(dev, MAC_BLK_CTRL, 0xa);
1865 }
1866 }
1867
1868 for (i = 0; i < MAX_QUEUE_SIZE; i++)
1869 skb_queue_purge(&priv->rtllib->skb_waitQ[i]);
1870
1871 skb_queue_purge(&priv->skb_queue);
1872 }
1873
rtl92e_update_ratr_table(struct net_device * dev)1874 void rtl92e_update_ratr_table(struct net_device *dev)
1875 {
1876 struct r8192_priv *priv = rtllib_priv(dev);
1877 struct rtllib_device *ieee = priv->rtllib;
1878 u8 *pMcsRate = ieee->dot11ht_oper_rate_set;
1879 u32 ratr_value = 0;
1880 u16 rate_config = 0;
1881 u8 rate_index = 0;
1882
1883 rtl92e_config_rate(dev, &rate_config);
1884 ratr_value = rate_config | *pMcsRate << 12;
1885 switch (ieee->mode) {
1886 case IEEE_A:
1887 ratr_value &= 0x00000FF0;
1888 break;
1889 case IEEE_B:
1890 ratr_value &= 0x0000000F;
1891 break;
1892 case IEEE_G:
1893 case IEEE_G|IEEE_B:
1894 ratr_value &= 0x00000FF7;
1895 break;
1896 case IEEE_N_24G:
1897 case IEEE_N_5G:
1898 if (ieee->ht_info->peer_mimo_ps == 0) {
1899 ratr_value &= 0x0007F007;
1900 } else {
1901 if (priv->rf_type == RF_1T2R)
1902 ratr_value &= 0x000FF007;
1903 else
1904 ratr_value &= 0x0F81F007;
1905 }
1906 break;
1907 default:
1908 break;
1909 }
1910 ratr_value &= 0x0FFFFFFF;
1911 if (ieee->ht_info->cur_tx_bw40mhz &&
1912 ieee->ht_info->bCurShortGI40MHz)
1913 ratr_value |= 0x80000000;
1914 else if (!ieee->ht_info->cur_tx_bw40mhz &&
1915 ieee->ht_info->bCurShortGI20MHz)
1916 ratr_value |= 0x80000000;
1917 rtl92e_writel(dev, RATR0+rate_index*4, ratr_value);
1918 rtl92e_writeb(dev, UFWP, 1);
1919 }
1920
1921 void
rtl92e_init_variables(struct net_device * dev)1922 rtl92e_init_variables(struct net_device *dev)
1923 {
1924 struct r8192_priv *priv = rtllib_priv(dev);
1925
1926 strscpy(priv->nick, "rtl8192E", sizeof(priv->nick));
1927
1928 priv->rtllib->softmac_features = IEEE_SOFTMAC_SCAN |
1929 IEEE_SOFTMAC_ASSOCIATE | IEEE_SOFTMAC_PROBERQ |
1930 IEEE_SOFTMAC_PROBERS | IEEE_SOFTMAC_TX_QUEUE;
1931
1932 priv->rtllib->tx_headroom = sizeof(struct tx_fwinfo_8190pci);
1933
1934 priv->short_retry_limit = 0x30;
1935 priv->long_retry_limit = 0x30;
1936
1937 priv->receive_config = RCR_ADD3 |
1938 RCR_AMF | RCR_ADF |
1939 RCR_AICV |
1940 RCR_AB | RCR_AM | RCR_APM |
1941 RCR_AAP | ((u32)7<<RCR_MXDMA_OFFSET) |
1942 ((u32)7 << RCR_FIFO_OFFSET) | RCR_ONLYERLPKT;
1943
1944 priv->irq_mask[0] = (u32)(IMR_ROK | IMR_VODOK | IMR_VIDOK |
1945 IMR_BEDOK | IMR_BKDOK | IMR_HCCADOK |
1946 IMR_MGNTDOK | IMR_COMDOK | IMR_HIGHDOK |
1947 IMR_BDOK | IMR_RXCMDOK | IMR_TIMEOUT0 |
1948 IMR_RDU | IMR_RXFOVW | IMR_TXFOVW |
1949 IMR_BcnInt | IMR_TBDOK | IMR_TBDER);
1950
1951 priv->bfirst_after_down = false;
1952 }
1953
rtl92e_enable_irq(struct net_device * dev)1954 void rtl92e_enable_irq(struct net_device *dev)
1955 {
1956 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1957
1958 priv->irq_enabled = 1;
1959
1960 rtl92e_writel(dev, INTA_MASK, priv->irq_mask[0]);
1961
1962 }
1963
rtl92e_disable_irq(struct net_device * dev)1964 void rtl92e_disable_irq(struct net_device *dev)
1965 {
1966 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1967
1968 rtl92e_writel(dev, INTA_MASK, 0);
1969
1970 priv->irq_enabled = 0;
1971 }
1972
rtl92e_clear_irq(struct net_device * dev)1973 void rtl92e_clear_irq(struct net_device *dev)
1974 {
1975 u32 tmp;
1976
1977 tmp = rtl92e_readl(dev, ISR);
1978 rtl92e_writel(dev, ISR, tmp);
1979 }
1980
1981
rtl92e_enable_rx(struct net_device * dev)1982 void rtl92e_enable_rx(struct net_device *dev)
1983 {
1984 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1985
1986 rtl92e_writel(dev, RDQDA, priv->rx_ring_dma[RX_MPDU_QUEUE]);
1987 }
1988
1989 static const u32 TX_DESC_BASE[] = {
1990 BKQDA, BEQDA, VIQDA, VOQDA, HCCAQDA, CQDA, MQDA, HQDA, BQDA
1991 };
1992
rtl92e_enable_tx(struct net_device * dev)1993 void rtl92e_enable_tx(struct net_device *dev)
1994 {
1995 struct r8192_priv *priv = (struct r8192_priv *)rtllib_priv(dev);
1996 u32 i;
1997
1998 for (i = 0; i < MAX_TX_QUEUE_COUNT; i++)
1999 rtl92e_writel(dev, TX_DESC_BASE[i], priv->tx_ring[i].dma);
2000 }
2001
2002
rtl92e_ack_irq(struct net_device * dev,u32 * p_inta,u32 * p_intb)2003 void rtl92e_ack_irq(struct net_device *dev, u32 *p_inta, u32 *p_intb)
2004 {
2005 *p_inta = rtl92e_readl(dev, ISR);
2006 rtl92e_writel(dev, ISR, *p_inta);
2007 }
2008
rtl92e_is_rx_stuck(struct net_device * dev)2009 bool rtl92e_is_rx_stuck(struct net_device *dev)
2010 {
2011 struct r8192_priv *priv = rtllib_priv(dev);
2012 u16 RegRxCounter = rtl92e_readw(dev, 0x130);
2013 bool bStuck = false;
2014 static u8 rx_chk_cnt;
2015 u32 SlotIndex = 0, TotalRxStuckCount = 0;
2016 u8 i;
2017 u8 SilentResetRxSoltNum = 4;
2018
2019 rx_chk_cnt++;
2020 if (priv->undecorated_smoothed_pwdb >= (RATE_ADAPTIVE_TH_HIGH + 5)) {
2021 rx_chk_cnt = 0;
2022 } else if ((priv->undecorated_smoothed_pwdb < (RATE_ADAPTIVE_TH_HIGH + 5))
2023 && (((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) &&
2024 (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_40M))
2025 || ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) &&
2026 (priv->undecorated_smoothed_pwdb >= RATE_ADAPTIVE_TH_LOW_20M)))) {
2027 if (rx_chk_cnt < 2)
2028 return bStuck;
2029 rx_chk_cnt = 0;
2030 } else if ((((priv->current_chnl_bw != HT_CHANNEL_WIDTH_20) &&
2031 (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_40M)) ||
2032 ((priv->current_chnl_bw == HT_CHANNEL_WIDTH_20) &&
2033 (priv->undecorated_smoothed_pwdb < RATE_ADAPTIVE_TH_LOW_20M))) &&
2034 priv->undecorated_smoothed_pwdb >= VERY_LOW_RSSI) {
2035 if (rx_chk_cnt < 4)
2036 return bStuck;
2037 rx_chk_cnt = 0;
2038 } else {
2039 if (rx_chk_cnt < 8)
2040 return bStuck;
2041 rx_chk_cnt = 0;
2042 }
2043
2044
2045 SlotIndex = (priv->silent_reset_rx_slot_index++)%SilentResetRxSoltNum;
2046
2047 if (priv->rx_ctr == RegRxCounter) {
2048 priv->silent_reset_rx_stuck_event[SlotIndex] = 1;
2049
2050 for (i = 0; i < SilentResetRxSoltNum; i++)
2051 TotalRxStuckCount += priv->silent_reset_rx_stuck_event[i];
2052
2053 if (TotalRxStuckCount == SilentResetRxSoltNum) {
2054 bStuck = true;
2055 for (i = 0; i < SilentResetRxSoltNum; i++)
2056 TotalRxStuckCount +=
2057 priv->silent_reset_rx_stuck_event[i];
2058 }
2059
2060
2061 } else {
2062 priv->silent_reset_rx_stuck_event[SlotIndex] = 0;
2063 }
2064
2065 priv->rx_ctr = RegRxCounter;
2066
2067 return bStuck;
2068 }
2069
rtl92e_is_tx_stuck(struct net_device * dev)2070 bool rtl92e_is_tx_stuck(struct net_device *dev)
2071 {
2072 struct r8192_priv *priv = rtllib_priv(dev);
2073 bool bStuck = false;
2074 u16 RegTxCounter = rtl92e_readw(dev, 0x128);
2075
2076 if (priv->tx_counter == RegTxCounter)
2077 bStuck = true;
2078
2079 priv->tx_counter = RegTxCounter;
2080
2081 return bStuck;
2082 }
2083
rtl92e_get_nmode_support_by_sec(struct net_device * dev)2084 bool rtl92e_get_nmode_support_by_sec(struct net_device *dev)
2085 {
2086 struct r8192_priv *priv = rtllib_priv(dev);
2087 struct rtllib_device *ieee = priv->rtllib;
2088
2089 if (ieee->rtllib_ap_sec_type &&
2090 (ieee->rtllib_ap_sec_type(priv->rtllib)&(SEC_ALG_WEP |
2091 SEC_ALG_TKIP))) {
2092 return false;
2093 } else {
2094 return true;
2095 }
2096 }
2097
rtl92e_is_halfn_supported_by_ap(struct net_device * dev)2098 bool rtl92e_is_halfn_supported_by_ap(struct net_device *dev)
2099 {
2100 struct r8192_priv *priv = rtllib_priv(dev);
2101 struct rtllib_device *ieee = priv->rtllib;
2102
2103 return ieee->bHalfWirelessN24GMode;
2104 }
2105