1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 - 2015 Xilinx, Inc. 4 * Michal Simek <michal.simek@xilinx.com> 5 */ 6 7 #ifndef _ASM_ARCH_HARDWARE_H 8 #define _ASM_ARCH_HARDWARE_H 9 10 #ifndef __ASSEMBLY__ 11 #include <linux/bitops.h> 12 #endif 13 14 #define ZYNQMP_TCM_BASE_ADDR 0xFFE00000 15 #define ZYNQMP_TCM_SIZE 0x40000 16 17 #define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000 18 #define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000 19 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 20 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 21 22 #define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800 23 #define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \ 24 + 0x00000114) 25 #define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210 26 27 #define ADMA_CH0_BASEADDR 0xFFA80000 28 29 #define PS_MODE0 BIT(0) 30 #define PS_MODE1 BIT(1) 31 #define PS_MODE2 BIT(2) 32 #define PS_MODE3 BIT(3) 33 34 #define RESET_REASON_DEBUG_SYS BIT(6) 35 #define RESET_REASON_SOFT BIT(5) 36 #define RESET_REASON_SRST BIT(4) 37 #define RESET_REASON_PSONLY BIT(3) 38 #define RESET_REASON_PMU BIT(2) 39 #define RESET_REASON_INTERNAL BIT(1) 40 #define RESET_REASON_EXTERNAL BIT(0) 41 42 struct crlapb_regs { 43 u32 reserved0[36]; 44 u32 cpu_r5_ctrl; /* 0x90 */ 45 u32 reserved1[37]; 46 u32 timestamp_ref_ctrl; /* 0x128 */ 47 u32 reserved2[53]; 48 u32 boot_mode; /* 0x200 */ 49 u32 reserved3_0[7]; 50 u32 reset_reason; /* 0x220 */ 51 u32 reserved3_1[6]; 52 u32 rst_lpd_top; /* 0x23C */ 53 u32 reserved4[4]; 54 u32 boot_pin_ctrl; /* 0x250 */ 55 u32 reserved5[21]; 56 }; 57 58 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) 59 60 #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 61 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 62 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 63 64 struct iou_scntr_secure { 65 u32 counter_control_register; 66 u32 reserved0[7]; 67 u32 base_frequency_id_register; 68 }; 69 70 #define iou_scntr_secure ((struct iou_scntr_secure *)ZYNQMP_IOU_SCNTR_SECURE) 71 72 #define ZYNQMP_PS_VERSION 0xFFCA0044 73 #define ZYNQMP_PS_VER_MASK GENMASK(1, 0) 74 75 /* Bootmode setting values */ 76 #define BOOT_MODES_MASK 0x0000000F 77 #define QSPI_MODE_24BIT 0x00000001 78 #define QSPI_MODE_32BIT 0x00000002 79 #define SD_MODE 0x00000003 /* sd 0 */ 80 #define SD_MODE1 0x00000005 /* sd 1 */ 81 #define NAND_MODE 0x00000004 82 #define EMMC_MODE 0x00000006 83 #define USB_MODE 0x00000007 84 #define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ 85 #define JTAG_MODE 0x00000000 86 #define BOOT_MODE_USE_ALT 0x100 87 #define BOOT_MODE_ALT_SHIFT 12 88 /* SW secondary boot modes 0xa - 0xd */ 89 #define SW_USBHOST_MODE 0x0000000A 90 #define SW_SATA_MODE 0x0000000B 91 92 #define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000 93 94 struct iou_slcr_regs { 95 u32 mio_pin[78]; 96 u32 reserved[442]; 97 }; 98 99 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) 100 101 #define ZYNQMP_RPU_BASEADDR 0xFF9A0000 102 103 struct rpu_regs { 104 u32 rpu_glbl_ctrl; 105 u32 reserved0[63]; 106 u32 rpu0_cfg; /* 0x100 */ 107 u32 reserved1[63]; 108 u32 rpu1_cfg; /* 0x200 */ 109 }; 110 111 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) 112 113 #define ZYNQMP_CRF_APB_BASEADDR 0xFD1A0000 114 115 struct crfapb_regs { 116 u32 reserved0[65]; 117 u32 rst_fpd_apu; /* 0x104 */ 118 u32 reserved1; 119 }; 120 121 #define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR) 122 123 #define ZYNQMP_APU_BASEADDR 0xFD5C0000 124 125 struct apu_regs { 126 u32 reserved0[16]; 127 u32 rvbar_addr0_l; /* 0x40 */ 128 u32 rvbar_addr0_h; /* 0x44 */ 129 u32 reserved1[20]; 130 }; 131 132 #define apu_base ((struct apu_regs *)ZYNQMP_APU_BASEADDR) 133 134 /* Board version value */ 135 #define ZYNQMP_CSU_BASEADDR 0xFFCA0000 136 #define ZYNQMP_CSU_VERSION_SILICON 0x0 137 #define ZYNQMP_CSU_VERSION_QEMU 0x3 138 139 #define ZYNQMP_CSU_VERSION_EMPTY_SHIFT 20 140 141 #define ZYNQMP_SILICON_VER_MASK 0xF 142 #define ZYNQMP_SILICON_VER_SHIFT 0 143 144 struct csu_regs { 145 u32 reserved0[4]; 146 u32 multi_boot; 147 u32 reserved1[11]; 148 u32 idcode; 149 u32 version; 150 }; 151 152 #define csu_base ((struct csu_regs *)ZYNQMP_CSU_BASEADDR) 153 154 #define ZYNQMP_PMU_BASEADDR 0xFFD80000 155 156 struct pmu_regs { 157 u32 reserved[18]; 158 u32 gen_storage6; /* 0x48 */ 159 }; 160 161 #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) 162 163 #endif /* _ASM_ARCH_HARDWARE_H */ 164