1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26
27 #include <linux/firmware.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/debugfs.h>
31 #include <drm/drm_drv.h>
32
33 #include "amdgpu.h"
34 #include "amdgpu_pm.h"
35 #include "amdgpu_vcn.h"
36 #include "soc15d.h"
37
38 /* Firmware Names */
39 #define FIRMWARE_RAVEN "amdgpu/raven_vcn.bin"
40 #define FIRMWARE_PICASSO "amdgpu/picasso_vcn.bin"
41 #define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
42 #define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
43 #define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
44 #define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
45 #define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
46 #define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
47 #define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
48 #define FIRMWARE_SIENNA_CICHLID "amdgpu/sienna_cichlid_vcn.bin"
49 #define FIRMWARE_NAVY_FLOUNDER "amdgpu/navy_flounder_vcn.bin"
50 #define FIRMWARE_VANGOGH "amdgpu/vangogh_vcn.bin"
51 #define FIRMWARE_DIMGREY_CAVEFISH "amdgpu/dimgrey_cavefish_vcn.bin"
52 #define FIRMWARE_ALDEBARAN "amdgpu/aldebaran_vcn.bin"
53 #define FIRMWARE_BEIGE_GOBY "amdgpu/beige_goby_vcn.bin"
54 #define FIRMWARE_YELLOW_CARP "amdgpu/yellow_carp_vcn.bin"
55 #define FIRMWARE_VCN_3_1_2 "amdgpu/vcn_3_1_2.bin"
56 #define FIRMWARE_VCN4_0_0 "amdgpu/vcn_4_0_0.bin"
57 #define FIRMWARE_VCN4_0_2 "amdgpu/vcn_4_0_2.bin"
58 #define FIRMWARE_VCN4_0_4 "amdgpu/vcn_4_0_4.bin"
59
60 MODULE_FIRMWARE(FIRMWARE_RAVEN);
61 MODULE_FIRMWARE(FIRMWARE_PICASSO);
62 MODULE_FIRMWARE(FIRMWARE_RAVEN2);
63 MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
64 MODULE_FIRMWARE(FIRMWARE_RENOIR);
65 MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
66 MODULE_FIRMWARE(FIRMWARE_ALDEBARAN);
67 MODULE_FIRMWARE(FIRMWARE_NAVI10);
68 MODULE_FIRMWARE(FIRMWARE_NAVI14);
69 MODULE_FIRMWARE(FIRMWARE_NAVI12);
70 MODULE_FIRMWARE(FIRMWARE_SIENNA_CICHLID);
71 MODULE_FIRMWARE(FIRMWARE_NAVY_FLOUNDER);
72 MODULE_FIRMWARE(FIRMWARE_VANGOGH);
73 MODULE_FIRMWARE(FIRMWARE_DIMGREY_CAVEFISH);
74 MODULE_FIRMWARE(FIRMWARE_BEIGE_GOBY);
75 MODULE_FIRMWARE(FIRMWARE_YELLOW_CARP);
76 MODULE_FIRMWARE(FIRMWARE_VCN_3_1_2);
77 MODULE_FIRMWARE(FIRMWARE_VCN4_0_0);
78 MODULE_FIRMWARE(FIRMWARE_VCN4_0_2);
79 MODULE_FIRMWARE(FIRMWARE_VCN4_0_4);
80
81 static void amdgpu_vcn_idle_work_handler(struct work_struct *work);
82
amdgpu_vcn_early_init(struct amdgpu_device * adev)83 int amdgpu_vcn_early_init(struct amdgpu_device *adev)
84 {
85 char ucode_prefix[30];
86 char fw_name[40];
87 int r;
88
89 amdgpu_ucode_ip_version_decode(adev, UVD_HWIP, ucode_prefix, sizeof(ucode_prefix));
90 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s.bin", ucode_prefix);
91 r = amdgpu_ucode_request(adev, &adev->vcn.fw, fw_name);
92 if (r)
93 amdgpu_ucode_release(&adev->vcn.fw);
94
95 return r;
96 }
97
amdgpu_vcn_sw_init(struct amdgpu_device * adev)98 int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
99 {
100 unsigned long bo_size;
101 const struct common_firmware_header *hdr;
102 unsigned char fw_check;
103 unsigned int fw_shared_size, log_offset;
104 int i, r;
105
106 INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
107 mutex_init(&adev->vcn.vcn_pg_lock);
108 mutex_init(&adev->vcn.vcn1_jpeg1_workaround);
109 atomic_set(&adev->vcn.total_submission_cnt, 0);
110 for (i = 0; i < adev->vcn.num_vcn_inst; i++)
111 atomic_set(&adev->vcn.inst[i].dpg_enc_submission_cnt, 0);
112
113 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
114 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
115 adev->vcn.indirect_sram = true;
116
117 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
118 adev->vcn.fw_version = le32_to_cpu(hdr->ucode_version);
119
120 /* Bit 20-23, it is encode major and non-zero for new naming convention.
121 * This field is part of version minor and DRM_DISABLED_FLAG in old naming
122 * convention. Since the l:wq!atest version minor is 0x5B and DRM_DISABLED_FLAG
123 * is zero in old naming convention, this field is always zero so far.
124 * These four bits are used to tell which naming convention is present.
125 */
126 fw_check = (le32_to_cpu(hdr->ucode_version) >> 20) & 0xf;
127 if (fw_check) {
128 unsigned int dec_ver, enc_major, enc_minor, vep, fw_rev;
129
130 fw_rev = le32_to_cpu(hdr->ucode_version) & 0xfff;
131 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 12) & 0xff;
132 enc_major = fw_check;
133 dec_ver = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xf;
134 vep = (le32_to_cpu(hdr->ucode_version) >> 28) & 0xf;
135 DRM_INFO("Found VCN firmware Version ENC: %u.%u DEC: %u VEP: %u Revision: %u\n",
136 enc_major, enc_minor, dec_ver, vep, fw_rev);
137 } else {
138 unsigned int version_major, version_minor, family_id;
139
140 family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
141 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
142 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
143 DRM_INFO("Found VCN firmware Version: %u.%u Family ID: %u\n",
144 version_major, version_minor, family_id);
145 }
146
147 bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE;
148 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
149 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
150
151 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){
152 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared));
153 log_offset = offsetof(struct amdgpu_vcn4_fw_shared, fw_log);
154 } else {
155 fw_shared_size = AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared));
156 log_offset = offsetof(struct amdgpu_fw_shared, fw_log);
157 }
158
159 bo_size += fw_shared_size;
160
161 if (amdgpu_vcnfw_log)
162 bo_size += AMDGPU_VCNFW_LOG_SIZE;
163
164 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
165 if (adev->vcn.harvest_config & (1 << i))
166 continue;
167
168 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
169 AMDGPU_GEM_DOMAIN_VRAM |
170 AMDGPU_GEM_DOMAIN_GTT,
171 &adev->vcn.inst[i].vcpu_bo,
172 &adev->vcn.inst[i].gpu_addr,
173 &adev->vcn.inst[i].cpu_addr);
174 if (r) {
175 dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
176 return r;
177 }
178
179 adev->vcn.inst[i].fw_shared.cpu_addr = adev->vcn.inst[i].cpu_addr +
180 bo_size - fw_shared_size;
181 adev->vcn.inst[i].fw_shared.gpu_addr = adev->vcn.inst[i].gpu_addr +
182 bo_size - fw_shared_size;
183
184 adev->vcn.inst[i].fw_shared.mem_size = fw_shared_size;
185
186 if (amdgpu_vcnfw_log) {
187 adev->vcn.inst[i].fw_shared.cpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
188 adev->vcn.inst[i].fw_shared.gpu_addr -= AMDGPU_VCNFW_LOG_SIZE;
189 adev->vcn.inst[i].fw_shared.log_offset = log_offset;
190 }
191
192 if (adev->vcn.indirect_sram) {
193 r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
194 AMDGPU_GEM_DOMAIN_VRAM |
195 AMDGPU_GEM_DOMAIN_GTT,
196 &adev->vcn.inst[i].dpg_sram_bo,
197 &adev->vcn.inst[i].dpg_sram_gpu_addr,
198 &adev->vcn.inst[i].dpg_sram_cpu_addr);
199 if (r) {
200 dev_err(adev->dev, "VCN %d (%d) failed to allocate DPG bo\n", i, r);
201 return r;
202 }
203 }
204 }
205
206 return 0;
207 }
208
amdgpu_vcn_sw_fini(struct amdgpu_device * adev)209 int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
210 {
211 int i, j;
212
213 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
214 if (adev->vcn.harvest_config & (1 << j))
215 continue;
216
217 if (adev->vcn.indirect_sram) {
218 amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
219 &adev->vcn.inst[j].dpg_sram_gpu_addr,
220 (void **)&adev->vcn.inst[j].dpg_sram_cpu_addr);
221 }
222 kvfree(adev->vcn.inst[j].saved_bo);
223
224 amdgpu_bo_free_kernel(&adev->vcn.inst[j].vcpu_bo,
225 &adev->vcn.inst[j].gpu_addr,
226 (void **)&adev->vcn.inst[j].cpu_addr);
227
228 amdgpu_ring_fini(&adev->vcn.inst[j].ring_dec);
229
230 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
231 amdgpu_ring_fini(&adev->vcn.inst[j].ring_enc[i]);
232 }
233
234 amdgpu_ucode_release(&adev->vcn.fw);
235 mutex_destroy(&adev->vcn.vcn1_jpeg1_workaround);
236 mutex_destroy(&adev->vcn.vcn_pg_lock);
237
238 return 0;
239 }
240
241 /* from vcn4 and above, only unified queue is used */
amdgpu_vcn_using_unified_queue(struct amdgpu_ring * ring)242 static bool amdgpu_vcn_using_unified_queue(struct amdgpu_ring *ring)
243 {
244 struct amdgpu_device *adev = ring->adev;
245 bool ret = false;
246
247 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0))
248 ret = true;
249
250 return ret;
251 }
252
amdgpu_vcn_is_disabled_vcn(struct amdgpu_device * adev,enum vcn_ring_type type,uint32_t vcn_instance)253 bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type type, uint32_t vcn_instance)
254 {
255 bool ret = false;
256 int vcn_config = adev->vcn.vcn_config[vcn_instance];
257
258 if ((type == VCN_ENCODE_RING) && (vcn_config & VCN_BLOCK_ENCODE_DISABLE_MASK)) {
259 ret = true;
260 } else if ((type == VCN_DECODE_RING) && (vcn_config & VCN_BLOCK_DECODE_DISABLE_MASK)) {
261 ret = true;
262 } else if ((type == VCN_UNIFIED_RING) && (vcn_config & VCN_BLOCK_QUEUE_DISABLE_MASK)) {
263 ret = true;
264 }
265
266 return ret;
267 }
268
amdgpu_vcn_suspend(struct amdgpu_device * adev)269 int amdgpu_vcn_suspend(struct amdgpu_device *adev)
270 {
271 unsigned size;
272 void *ptr;
273 int i, idx;
274
275 cancel_delayed_work_sync(&adev->vcn.idle_work);
276
277 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
278 if (adev->vcn.harvest_config & (1 << i))
279 continue;
280 if (adev->vcn.inst[i].vcpu_bo == NULL)
281 return 0;
282
283 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
284 ptr = adev->vcn.inst[i].cpu_addr;
285
286 adev->vcn.inst[i].saved_bo = kvmalloc(size, GFP_KERNEL);
287 if (!adev->vcn.inst[i].saved_bo)
288 return -ENOMEM;
289
290 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
291 memcpy_fromio(adev->vcn.inst[i].saved_bo, ptr, size);
292 drm_dev_exit(idx);
293 }
294 }
295 return 0;
296 }
297
amdgpu_vcn_resume(struct amdgpu_device * adev)298 int amdgpu_vcn_resume(struct amdgpu_device *adev)
299 {
300 unsigned size;
301 void *ptr;
302 int i, idx;
303
304 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
305 if (adev->vcn.harvest_config & (1 << i))
306 continue;
307 if (adev->vcn.inst[i].vcpu_bo == NULL)
308 return -EINVAL;
309
310 size = amdgpu_bo_size(adev->vcn.inst[i].vcpu_bo);
311 ptr = adev->vcn.inst[i].cpu_addr;
312
313 if (adev->vcn.inst[i].saved_bo != NULL) {
314 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
315 memcpy_toio(ptr, adev->vcn.inst[i].saved_bo, size);
316 drm_dev_exit(idx);
317 }
318 kvfree(adev->vcn.inst[i].saved_bo);
319 adev->vcn.inst[i].saved_bo = NULL;
320 } else {
321 const struct common_firmware_header *hdr;
322 unsigned offset;
323
324 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
325 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
326 offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
327 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
328 memcpy_toio(adev->vcn.inst[i].cpu_addr, adev->vcn.fw->data + offset,
329 le32_to_cpu(hdr->ucode_size_bytes));
330 drm_dev_exit(idx);
331 }
332 size -= le32_to_cpu(hdr->ucode_size_bytes);
333 ptr += le32_to_cpu(hdr->ucode_size_bytes);
334 }
335 memset_io(ptr, 0, size);
336 }
337 }
338 return 0;
339 }
340
amdgpu_vcn_idle_work_handler(struct work_struct * work)341 static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
342 {
343 struct amdgpu_device *adev =
344 container_of(work, struct amdgpu_device, vcn.idle_work.work);
345 unsigned int fences = 0, fence[AMDGPU_MAX_VCN_INSTANCES] = {0};
346 unsigned int i, j;
347 int r = 0;
348
349 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
350 if (adev->vcn.harvest_config & (1 << j))
351 continue;
352
353 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
354 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_enc[i]);
355 }
356
357 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
358 struct dpg_pause_state new_state;
359
360 if (fence[j] ||
361 unlikely(atomic_read(&adev->vcn.inst[j].dpg_enc_submission_cnt)))
362 new_state.fw_based = VCN_DPG_STATE__PAUSE;
363 else
364 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
365
366 adev->vcn.pause_dpg_mode(adev, j, &new_state);
367 }
368
369 fence[j] += amdgpu_fence_count_emitted(&adev->vcn.inst[j].ring_dec);
370 fences += fence[j];
371 }
372
373 if (!fences && !atomic_read(&adev->vcn.total_submission_cnt)) {
374 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
375 AMD_PG_STATE_GATE);
376 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
377 false);
378 if (r)
379 dev_warn(adev->dev, "(%d) failed to disable video power profile mode\n", r);
380 } else {
381 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
382 }
383 }
384
amdgpu_vcn_ring_begin_use(struct amdgpu_ring * ring)385 void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
386 {
387 struct amdgpu_device *adev = ring->adev;
388 int r = 0;
389
390 atomic_inc(&adev->vcn.total_submission_cnt);
391
392 if (!cancel_delayed_work_sync(&adev->vcn.idle_work)) {
393 r = amdgpu_dpm_switch_power_profile(adev, PP_SMC_POWER_PROFILE_VIDEO,
394 true);
395 if (r)
396 dev_warn(adev->dev, "(%d) failed to switch to video power profile mode\n", r);
397 }
398
399 mutex_lock(&adev->vcn.vcn_pg_lock);
400 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
401 AMD_PG_STATE_UNGATE);
402
403 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
404 struct dpg_pause_state new_state;
405
406 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC) {
407 atomic_inc(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
408 new_state.fw_based = VCN_DPG_STATE__PAUSE;
409 } else {
410 unsigned int fences = 0;
411 unsigned int i;
412
413 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
414 fences += amdgpu_fence_count_emitted(&adev->vcn.inst[ring->me].ring_enc[i]);
415
416 if (fences || atomic_read(&adev->vcn.inst[ring->me].dpg_enc_submission_cnt))
417 new_state.fw_based = VCN_DPG_STATE__PAUSE;
418 else
419 new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
420 }
421
422 adev->vcn.pause_dpg_mode(adev, ring->me, &new_state);
423 }
424 mutex_unlock(&adev->vcn.vcn_pg_lock);
425 }
426
amdgpu_vcn_ring_end_use(struct amdgpu_ring * ring)427 void amdgpu_vcn_ring_end_use(struct amdgpu_ring *ring)
428 {
429 if (ring->adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG &&
430 ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
431 atomic_dec(&ring->adev->vcn.inst[ring->me].dpg_enc_submission_cnt);
432
433 atomic_dec(&ring->adev->vcn.total_submission_cnt);
434
435 schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
436 }
437
amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring * ring)438 int amdgpu_vcn_dec_ring_test_ring(struct amdgpu_ring *ring)
439 {
440 struct amdgpu_device *adev = ring->adev;
441 uint32_t tmp = 0;
442 unsigned i;
443 int r;
444
445 /* VCN in SRIOV does not support direct register read/write */
446 if (amdgpu_sriov_vf(adev))
447 return 0;
448
449 WREG32(adev->vcn.inst[ring->me].external.scratch9, 0xCAFEDEAD);
450 r = amdgpu_ring_alloc(ring, 3);
451 if (r)
452 return r;
453 amdgpu_ring_write(ring, PACKET0(adev->vcn.internal.scratch9, 0));
454 amdgpu_ring_write(ring, 0xDEADBEEF);
455 amdgpu_ring_commit(ring);
456 for (i = 0; i < adev->usec_timeout; i++) {
457 tmp = RREG32(adev->vcn.inst[ring->me].external.scratch9);
458 if (tmp == 0xDEADBEEF)
459 break;
460 udelay(1);
461 }
462
463 if (i >= adev->usec_timeout)
464 r = -ETIMEDOUT;
465
466 return r;
467 }
468
amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring * ring)469 int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
470 {
471 struct amdgpu_device *adev = ring->adev;
472 uint32_t rptr;
473 unsigned int i;
474 int r;
475
476 if (amdgpu_sriov_vf(adev))
477 return 0;
478
479 r = amdgpu_ring_alloc(ring, 16);
480 if (r)
481 return r;
482
483 rptr = amdgpu_ring_get_rptr(ring);
484
485 amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
486 amdgpu_ring_commit(ring);
487
488 for (i = 0; i < adev->usec_timeout; i++) {
489 if (amdgpu_ring_get_rptr(ring) != rptr)
490 break;
491 udelay(1);
492 }
493
494 if (i >= adev->usec_timeout)
495 r = -ETIMEDOUT;
496
497 return r;
498 }
499
amdgpu_vcn_dec_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)500 static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
501 struct amdgpu_ib *ib_msg,
502 struct dma_fence **fence)
503 {
504 u64 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
505 struct amdgpu_device *adev = ring->adev;
506 struct dma_fence *f = NULL;
507 struct amdgpu_job *job;
508 struct amdgpu_ib *ib;
509 int i, r;
510
511 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
512 64, AMDGPU_IB_POOL_DIRECT,
513 &job);
514 if (r)
515 goto err;
516
517 ib = &job->ibs[0];
518 ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
519 ib->ptr[1] = addr;
520 ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
521 ib->ptr[3] = addr >> 32;
522 ib->ptr[4] = PACKET0(adev->vcn.internal.cmd, 0);
523 ib->ptr[5] = 0;
524 for (i = 6; i < 16; i += 2) {
525 ib->ptr[i] = PACKET0(adev->vcn.internal.nop, 0);
526 ib->ptr[i+1] = 0;
527 }
528 ib->length_dw = 16;
529
530 r = amdgpu_job_submit_direct(job, ring, &f);
531 if (r)
532 goto err_free;
533
534 amdgpu_ib_free(adev, ib_msg, f);
535
536 if (fence)
537 *fence = dma_fence_get(f);
538 dma_fence_put(f);
539
540 return 0;
541
542 err_free:
543 amdgpu_job_free(job);
544 err:
545 amdgpu_ib_free(adev, ib_msg, f);
546 return r;
547 }
548
amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)549 static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
550 struct amdgpu_ib *ib)
551 {
552 struct amdgpu_device *adev = ring->adev;
553 uint32_t *msg;
554 int r, i;
555
556 memset(ib, 0, sizeof(*ib));
557 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
558 AMDGPU_IB_POOL_DIRECT,
559 ib);
560 if (r)
561 return r;
562
563 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
564 msg[0] = cpu_to_le32(0x00000028);
565 msg[1] = cpu_to_le32(0x00000038);
566 msg[2] = cpu_to_le32(0x00000001);
567 msg[3] = cpu_to_le32(0x00000000);
568 msg[4] = cpu_to_le32(handle);
569 msg[5] = cpu_to_le32(0x00000000);
570 msg[6] = cpu_to_le32(0x00000001);
571 msg[7] = cpu_to_le32(0x00000028);
572 msg[8] = cpu_to_le32(0x00000010);
573 msg[9] = cpu_to_le32(0x00000000);
574 msg[10] = cpu_to_le32(0x00000007);
575 msg[11] = cpu_to_le32(0x00000000);
576 msg[12] = cpu_to_le32(0x00000780);
577 msg[13] = cpu_to_le32(0x00000440);
578 for (i = 14; i < 1024; ++i)
579 msg[i] = cpu_to_le32(0x0);
580
581 return 0;
582 }
583
amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib)584 static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
585 struct amdgpu_ib *ib)
586 {
587 struct amdgpu_device *adev = ring->adev;
588 uint32_t *msg;
589 int r, i;
590
591 memset(ib, 0, sizeof(*ib));
592 r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
593 AMDGPU_IB_POOL_DIRECT,
594 ib);
595 if (r)
596 return r;
597
598 msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
599 msg[0] = cpu_to_le32(0x00000028);
600 msg[1] = cpu_to_le32(0x00000018);
601 msg[2] = cpu_to_le32(0x00000000);
602 msg[3] = cpu_to_le32(0x00000002);
603 msg[4] = cpu_to_le32(handle);
604 msg[5] = cpu_to_le32(0x00000000);
605 for (i = 6; i < 1024; ++i)
606 msg[i] = cpu_to_le32(0x0);
607
608 return 0;
609 }
610
amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring * ring,long timeout)611 int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
612 {
613 struct dma_fence *fence = NULL;
614 struct amdgpu_ib ib;
615 long r;
616
617 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
618 if (r)
619 goto error;
620
621 r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
622 if (r)
623 goto error;
624 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
625 if (r)
626 goto error;
627
628 r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
629 if (r)
630 goto error;
631
632 r = dma_fence_wait_timeout(fence, false, timeout);
633 if (r == 0)
634 r = -ETIMEDOUT;
635 else if (r > 0)
636 r = 0;
637
638 dma_fence_put(fence);
639 error:
640 return r;
641 }
642
amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib * ib,uint32_t ib_pack_in_dw,bool enc)643 static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
644 uint32_t ib_pack_in_dw, bool enc)
645 {
646 uint32_t *ib_checksum;
647
648 ib->ptr[ib->length_dw++] = 0x00000010; /* single queue checksum */
649 ib->ptr[ib->length_dw++] = 0x30000002;
650 ib_checksum = &ib->ptr[ib->length_dw++];
651 ib->ptr[ib->length_dw++] = ib_pack_in_dw;
652
653 ib->ptr[ib->length_dw++] = 0x00000010; /* engine info */
654 ib->ptr[ib->length_dw++] = 0x30000001;
655 ib->ptr[ib->length_dw++] = enc ? 0x2 : 0x3;
656 ib->ptr[ib->length_dw++] = ib_pack_in_dw * sizeof(uint32_t);
657
658 return ib_checksum;
659 }
660
amdgpu_vcn_unified_ring_ib_checksum(uint32_t ** ib_checksum,uint32_t ib_pack_in_dw)661 static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
662 uint32_t ib_pack_in_dw)
663 {
664 uint32_t i;
665 uint32_t checksum = 0;
666
667 for (i = 0; i < ib_pack_in_dw; i++)
668 checksum += *(*ib_checksum + 2 + i);
669
670 **ib_checksum = checksum;
671 }
672
amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring * ring,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)673 static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
674 struct amdgpu_ib *ib_msg,
675 struct dma_fence **fence)
676 {
677 struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
678 unsigned int ib_size_dw = 64;
679 struct amdgpu_device *adev = ring->adev;
680 struct dma_fence *f = NULL;
681 struct amdgpu_job *job;
682 struct amdgpu_ib *ib;
683 uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
684 bool sq = amdgpu_vcn_using_unified_queue(ring);
685 uint32_t *ib_checksum;
686 uint32_t ib_pack_in_dw;
687 int i, r;
688
689 if (sq)
690 ib_size_dw += 8;
691
692 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
693 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
694 &job);
695 if (r)
696 goto err;
697
698 ib = &job->ibs[0];
699 ib->length_dw = 0;
700
701 /* single queue headers */
702 if (sq) {
703 ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
704 + 4 + 2; /* engine info + decoding ib in dw */
705 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
706 }
707
708 ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
709 ib->ptr[ib->length_dw++] = cpu_to_le32(AMDGPU_VCN_IB_FLAG_DECODE_BUFFER);
710 decode_buffer = (struct amdgpu_vcn_decode_buffer *)&(ib->ptr[ib->length_dw]);
711 ib->length_dw += sizeof(struct amdgpu_vcn_decode_buffer) / 4;
712 memset(decode_buffer, 0, sizeof(struct amdgpu_vcn_decode_buffer));
713
714 decode_buffer->valid_buf_flag |= cpu_to_le32(AMDGPU_VCN_CMD_FLAG_MSG_BUFFER);
715 decode_buffer->msg_buffer_address_hi = cpu_to_le32(addr >> 32);
716 decode_buffer->msg_buffer_address_lo = cpu_to_le32(addr);
717
718 for (i = ib->length_dw; i < ib_size_dw; ++i)
719 ib->ptr[i] = 0x0;
720
721 if (sq)
722 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, ib_pack_in_dw);
723
724 r = amdgpu_job_submit_direct(job, ring, &f);
725 if (r)
726 goto err_free;
727
728 amdgpu_ib_free(adev, ib_msg, f);
729
730 if (fence)
731 *fence = dma_fence_get(f);
732 dma_fence_put(f);
733
734 return 0;
735
736 err_free:
737 amdgpu_job_free(job);
738 err:
739 amdgpu_ib_free(adev, ib_msg, f);
740 return r;
741 }
742
amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring * ring,long timeout)743 int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
744 {
745 struct dma_fence *fence = NULL;
746 struct amdgpu_ib ib;
747 long r;
748
749 r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
750 if (r)
751 goto error;
752
753 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
754 if (r)
755 goto error;
756 r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
757 if (r)
758 goto error;
759
760 r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
761 if (r)
762 goto error;
763
764 r = dma_fence_wait_timeout(fence, false, timeout);
765 if (r == 0)
766 r = -ETIMEDOUT;
767 else if (r > 0)
768 r = 0;
769
770 dma_fence_put(fence);
771 error:
772 return r;
773 }
774
amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring * ring)775 int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
776 {
777 struct amdgpu_device *adev = ring->adev;
778 uint32_t rptr;
779 unsigned i;
780 int r;
781
782 if (amdgpu_sriov_vf(adev))
783 return 0;
784
785 r = amdgpu_ring_alloc(ring, 16);
786 if (r)
787 return r;
788
789 rptr = amdgpu_ring_get_rptr(ring);
790
791 amdgpu_ring_write(ring, VCN_ENC_CMD_END);
792 amdgpu_ring_commit(ring);
793
794 for (i = 0; i < adev->usec_timeout; i++) {
795 if (amdgpu_ring_get_rptr(ring) != rptr)
796 break;
797 udelay(1);
798 }
799
800 if (i >= adev->usec_timeout)
801 r = -ETIMEDOUT;
802
803 return r;
804 }
805
amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)806 static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
807 struct amdgpu_ib *ib_msg,
808 struct dma_fence **fence)
809 {
810 unsigned int ib_size_dw = 16;
811 struct amdgpu_job *job;
812 struct amdgpu_ib *ib;
813 struct dma_fence *f = NULL;
814 uint32_t *ib_checksum = NULL;
815 uint64_t addr;
816 bool sq = amdgpu_vcn_using_unified_queue(ring);
817 int i, r;
818
819 if (sq)
820 ib_size_dw += 8;
821
822 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
823 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
824 &job);
825 if (r)
826 return r;
827
828 ib = &job->ibs[0];
829 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
830
831 ib->length_dw = 0;
832
833 if (sq)
834 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
835
836 ib->ptr[ib->length_dw++] = 0x00000018;
837 ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
838 ib->ptr[ib->length_dw++] = handle;
839 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
840 ib->ptr[ib->length_dw++] = addr;
841 ib->ptr[ib->length_dw++] = 0x0000000b;
842
843 ib->ptr[ib->length_dw++] = 0x00000014;
844 ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
845 ib->ptr[ib->length_dw++] = 0x0000001c;
846 ib->ptr[ib->length_dw++] = 0x00000000;
847 ib->ptr[ib->length_dw++] = 0x00000000;
848
849 ib->ptr[ib->length_dw++] = 0x00000008;
850 ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
851
852 for (i = ib->length_dw; i < ib_size_dw; ++i)
853 ib->ptr[i] = 0x0;
854
855 if (sq)
856 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
857
858 r = amdgpu_job_submit_direct(job, ring, &f);
859 if (r)
860 goto err;
861
862 if (fence)
863 *fence = dma_fence_get(f);
864 dma_fence_put(f);
865
866 return 0;
867
868 err:
869 amdgpu_job_free(job);
870 return r;
871 }
872
amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring * ring,uint32_t handle,struct amdgpu_ib * ib_msg,struct dma_fence ** fence)873 static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
874 struct amdgpu_ib *ib_msg,
875 struct dma_fence **fence)
876 {
877 unsigned int ib_size_dw = 16;
878 struct amdgpu_job *job;
879 struct amdgpu_ib *ib;
880 struct dma_fence *f = NULL;
881 uint32_t *ib_checksum = NULL;
882 uint64_t addr;
883 bool sq = amdgpu_vcn_using_unified_queue(ring);
884 int i, r;
885
886 if (sq)
887 ib_size_dw += 8;
888
889 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
890 ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
891 &job);
892 if (r)
893 return r;
894
895 ib = &job->ibs[0];
896 addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
897
898 ib->length_dw = 0;
899
900 if (sq)
901 ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, 0x11, true);
902
903 ib->ptr[ib->length_dw++] = 0x00000018;
904 ib->ptr[ib->length_dw++] = 0x00000001;
905 ib->ptr[ib->length_dw++] = handle;
906 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
907 ib->ptr[ib->length_dw++] = addr;
908 ib->ptr[ib->length_dw++] = 0x0000000b;
909
910 ib->ptr[ib->length_dw++] = 0x00000014;
911 ib->ptr[ib->length_dw++] = 0x00000002;
912 ib->ptr[ib->length_dw++] = 0x0000001c;
913 ib->ptr[ib->length_dw++] = 0x00000000;
914 ib->ptr[ib->length_dw++] = 0x00000000;
915
916 ib->ptr[ib->length_dw++] = 0x00000008;
917 ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
918
919 for (i = ib->length_dw; i < ib_size_dw; ++i)
920 ib->ptr[i] = 0x0;
921
922 if (sq)
923 amdgpu_vcn_unified_ring_ib_checksum(&ib_checksum, 0x11);
924
925 r = amdgpu_job_submit_direct(job, ring, &f);
926 if (r)
927 goto err;
928
929 if (fence)
930 *fence = dma_fence_get(f);
931 dma_fence_put(f);
932
933 return 0;
934
935 err:
936 amdgpu_job_free(job);
937 return r;
938 }
939
amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring * ring,long timeout)940 int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
941 {
942 struct amdgpu_device *adev = ring->adev;
943 struct dma_fence *fence = NULL;
944 struct amdgpu_ib ib;
945 long r;
946
947 memset(&ib, 0, sizeof(ib));
948 r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
949 AMDGPU_IB_POOL_DIRECT,
950 &ib);
951 if (r)
952 return r;
953
954 r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
955 if (r)
956 goto error;
957
958 r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
959 if (r)
960 goto error;
961
962 r = dma_fence_wait_timeout(fence, false, timeout);
963 if (r == 0)
964 r = -ETIMEDOUT;
965 else if (r > 0)
966 r = 0;
967
968 error:
969 amdgpu_ib_free(adev, &ib, fence);
970 dma_fence_put(fence);
971
972 return r;
973 }
974
amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring * ring,long timeout)975 int amdgpu_vcn_unified_ring_test_ib(struct amdgpu_ring *ring, long timeout)
976 {
977 long r;
978
979 r = amdgpu_vcn_enc_ring_test_ib(ring, timeout);
980 if (r)
981 goto error;
982
983 r = amdgpu_vcn_dec_sw_ring_test_ib(ring, timeout);
984
985 error:
986 return r;
987 }
988
amdgpu_vcn_get_enc_ring_prio(int ring)989 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
990 {
991 switch(ring) {
992 case 0:
993 return AMDGPU_RING_PRIO_0;
994 case 1:
995 return AMDGPU_RING_PRIO_1;
996 case 2:
997 return AMDGPU_RING_PRIO_2;
998 default:
999 return AMDGPU_RING_PRIO_0;
1000 }
1001 }
1002
amdgpu_vcn_setup_ucode(struct amdgpu_device * adev)1003 void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
1004 {
1005 int i;
1006 unsigned int idx;
1007
1008 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1009 const struct common_firmware_header *hdr;
1010 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
1011
1012 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
1013 if (adev->vcn.harvest_config & (1 << i))
1014 continue;
1015 /* currently only support 2 FW instances */
1016 if (i >= 2) {
1017 dev_info(adev->dev, "More then 2 VCN FW instances!\n");
1018 break;
1019 }
1020 idx = AMDGPU_UCODE_ID_VCN + i;
1021 adev->firmware.ucode[idx].ucode_id = idx;
1022 adev->firmware.ucode[idx].fw = adev->vcn.fw;
1023 adev->firmware.fw_size +=
1024 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
1025 }
1026 dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
1027 }
1028 }
1029
1030 /*
1031 * debugfs for mapping vcn firmware log buffer.
1032 */
1033 #if defined(CONFIG_DEBUG_FS)
amdgpu_debugfs_vcn_fwlog_read(struct file * f,char __user * buf,size_t size,loff_t * pos)1034 static ssize_t amdgpu_debugfs_vcn_fwlog_read(struct file *f, char __user *buf,
1035 size_t size, loff_t *pos)
1036 {
1037 struct amdgpu_vcn_inst *vcn;
1038 void *log_buf;
1039 volatile struct amdgpu_vcn_fwlog *plog;
1040 unsigned int read_pos, write_pos, available, i, read_bytes = 0;
1041 unsigned int read_num[2] = {0};
1042
1043 vcn = file_inode(f)->i_private;
1044 if (!vcn)
1045 return -ENODEV;
1046
1047 if (!vcn->fw_shared.cpu_addr || !amdgpu_vcnfw_log)
1048 return -EFAULT;
1049
1050 log_buf = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1051
1052 plog = (volatile struct amdgpu_vcn_fwlog *)log_buf;
1053 read_pos = plog->rptr;
1054 write_pos = plog->wptr;
1055
1056 if (read_pos > AMDGPU_VCNFW_LOG_SIZE || write_pos > AMDGPU_VCNFW_LOG_SIZE)
1057 return -EFAULT;
1058
1059 if (!size || (read_pos == write_pos))
1060 return 0;
1061
1062 if (write_pos > read_pos) {
1063 available = write_pos - read_pos;
1064 read_num[0] = min(size, (size_t)available);
1065 } else {
1066 read_num[0] = AMDGPU_VCNFW_LOG_SIZE - read_pos;
1067 available = read_num[0] + write_pos - plog->header_size;
1068 if (size > available)
1069 read_num[1] = write_pos - plog->header_size;
1070 else if (size > read_num[0])
1071 read_num[1] = size - read_num[0];
1072 else
1073 read_num[0] = size;
1074 }
1075
1076 for (i = 0; i < 2; i++) {
1077 if (read_num[i]) {
1078 if (read_pos == AMDGPU_VCNFW_LOG_SIZE)
1079 read_pos = plog->header_size;
1080 if (read_num[i] == copy_to_user((buf + read_bytes),
1081 (log_buf + read_pos), read_num[i]))
1082 return -EFAULT;
1083
1084 read_bytes += read_num[i];
1085 read_pos += read_num[i];
1086 }
1087 }
1088
1089 plog->rptr = read_pos;
1090 *pos += read_bytes;
1091 return read_bytes;
1092 }
1093
1094 static const struct file_operations amdgpu_debugfs_vcnfwlog_fops = {
1095 .owner = THIS_MODULE,
1096 .read = amdgpu_debugfs_vcn_fwlog_read,
1097 .llseek = default_llseek
1098 };
1099 #endif
1100
amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device * adev,uint8_t i,struct amdgpu_vcn_inst * vcn)1101 void amdgpu_debugfs_vcn_fwlog_init(struct amdgpu_device *adev, uint8_t i,
1102 struct amdgpu_vcn_inst *vcn)
1103 {
1104 #if defined(CONFIG_DEBUG_FS)
1105 struct drm_minor *minor = adev_to_drm(adev)->primary;
1106 struct dentry *root = minor->debugfs_root;
1107 char name[32];
1108
1109 sprintf(name, "amdgpu_vcn_%d_fwlog", i);
1110 debugfs_create_file_size(name, S_IFREG | S_IRUGO, root, vcn,
1111 &amdgpu_debugfs_vcnfwlog_fops,
1112 AMDGPU_VCNFW_LOG_SIZE);
1113 #endif
1114 }
1115
amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst * vcn)1116 void amdgpu_vcn_fwlog_init(struct amdgpu_vcn_inst *vcn)
1117 {
1118 #if defined(CONFIG_DEBUG_FS)
1119 volatile uint32_t *flag = vcn->fw_shared.cpu_addr;
1120 void *fw_log_cpu_addr = vcn->fw_shared.cpu_addr + vcn->fw_shared.mem_size;
1121 uint64_t fw_log_gpu_addr = vcn->fw_shared.gpu_addr + vcn->fw_shared.mem_size;
1122 volatile struct amdgpu_vcn_fwlog *log_buf = fw_log_cpu_addr;
1123 volatile struct amdgpu_fw_shared_fw_logging *fw_log = vcn->fw_shared.cpu_addr
1124 + vcn->fw_shared.log_offset;
1125 *flag |= cpu_to_le32(AMDGPU_VCN_FW_LOGGING_FLAG);
1126 fw_log->is_enabled = 1;
1127 fw_log->addr_lo = cpu_to_le32(fw_log_gpu_addr & 0xFFFFFFFF);
1128 fw_log->addr_hi = cpu_to_le32(fw_log_gpu_addr >> 32);
1129 fw_log->size = cpu_to_le32(AMDGPU_VCNFW_LOG_SIZE);
1130
1131 log_buf->header_size = sizeof(struct amdgpu_vcn_fwlog);
1132 log_buf->buffer_size = AMDGPU_VCNFW_LOG_SIZE;
1133 log_buf->rptr = log_buf->header_size;
1134 log_buf->wptr = log_buf->header_size;
1135 log_buf->wrapped = 0;
1136 #endif
1137 }
1138
amdgpu_vcn_process_poison_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1139 int amdgpu_vcn_process_poison_irq(struct amdgpu_device *adev,
1140 struct amdgpu_irq_src *source,
1141 struct amdgpu_iv_entry *entry)
1142 {
1143 struct ras_common_if *ras_if = adev->vcn.ras_if;
1144 struct ras_dispatch_if ih_data = {
1145 .entry = entry,
1146 };
1147
1148 if (!ras_if)
1149 return 0;
1150
1151 if (!amdgpu_sriov_vf(adev)) {
1152 ih_data.head = *ras_if;
1153 amdgpu_ras_interrupt_dispatch(adev, &ih_data);
1154 } else {
1155 if (adev->virt.ops && adev->virt.ops->ras_poison_handler)
1156 adev->virt.ops->ras_poison_handler(adev);
1157 else
1158 dev_warn(adev->dev,
1159 "No ras_poison_handler interface in SRIOV for VCN!\n");
1160 }
1161
1162 return 0;
1163 }
1164
amdgpu_vcn_set_ras_funcs(struct amdgpu_device * adev)1165 void amdgpu_vcn_set_ras_funcs(struct amdgpu_device *adev)
1166 {
1167 if (!adev->vcn.ras)
1168 return;
1169
1170 amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block);
1171
1172 strcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn");
1173 adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
1174 adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
1175 adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm;
1176
1177 /* If don't define special ras_late_init function, use default ras_late_init */
1178 if (!adev->vcn.ras->ras_block.ras_late_init)
1179 adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
1180 }
1181