1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/module.h>
8 #include <linux/msi.h>
9 #include <linux/pci.h>
10
11 #include "pci.h"
12 #include "core.h"
13 #include "hif.h"
14 #include "mhi.h"
15 #include "debug.h"
16
17 #define ATH12K_PCI_BAR_NUM 0
18 #define ATH12K_PCI_DMA_MASK 32
19
20 #define ATH12K_PCI_IRQ_CE0_OFFSET 3
21
22 #define WINDOW_ENABLE_BIT 0x40000000
23 #define WINDOW_REG_ADDRESS 0x310c
24 #define WINDOW_VALUE_MASK GENMASK(24, 19)
25 #define WINDOW_START 0x80000
26 #define WINDOW_RANGE_MASK GENMASK(18, 0)
27 #define WINDOW_STATIC_MASK GENMASK(31, 6)
28
29 #define TCSR_SOC_HW_VERSION 0x1B00000
30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8)
31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4)
32
33 /* BAR0 + 4k is always accessible, and no
34 * need to force wakeup.
35 * 4K - 32 = 0xFE0
36 */
37 #define ACCESS_ALWAYS_OFF 0xFE0
38
39 #define QCN9274_DEVICE_ID 0x1109
40 #define WCN7850_DEVICE_ID 0x1107
41
42 static const struct pci_device_id ath12k_pci_id_table[] = {
43 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) },
44 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) },
45 {0}
46 };
47
48 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table);
49
50 /* TODO: revisit IRQ mapping for new SRNG's */
51 static const struct ath12k_msi_config ath12k_msi_config[] = {
52 {
53 .total_vectors = 16,
54 .total_users = 3,
55 .users = (struct ath12k_msi_user[]) {
56 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
57 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
58 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
59 },
60 },
61 };
62
63 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = {
64 "bhi",
65 "mhi-er0",
66 "mhi-er1",
67 "ce0",
68 "ce1",
69 "ce2",
70 "ce3",
71 "ce4",
72 "ce5",
73 "ce6",
74 "ce7",
75 "ce8",
76 "ce9",
77 "ce10",
78 "ce11",
79 "ce12",
80 "ce13",
81 "ce14",
82 "ce15",
83 "host2wbm-desc-feed",
84 "host2reo-re-injection",
85 "host2reo-command",
86 "host2rxdma-monitor-ring3",
87 "host2rxdma-monitor-ring2",
88 "host2rxdma-monitor-ring1",
89 "reo2ost-exception",
90 "wbm2host-rx-release",
91 "reo2host-status",
92 "reo2host-destination-ring4",
93 "reo2host-destination-ring3",
94 "reo2host-destination-ring2",
95 "reo2host-destination-ring1",
96 "rxdma2host-monitor-destination-mac3",
97 "rxdma2host-monitor-destination-mac2",
98 "rxdma2host-monitor-destination-mac1",
99 "ppdu-end-interrupts-mac3",
100 "ppdu-end-interrupts-mac2",
101 "ppdu-end-interrupts-mac1",
102 "rxdma2host-monitor-status-ring-mac3",
103 "rxdma2host-monitor-status-ring-mac2",
104 "rxdma2host-monitor-status-ring-mac1",
105 "host2rxdma-host-buf-ring-mac3",
106 "host2rxdma-host-buf-ring-mac2",
107 "host2rxdma-host-buf-ring-mac1",
108 "rxdma2host-destination-ring-mac3",
109 "rxdma2host-destination-ring-mac2",
110 "rxdma2host-destination-ring-mac1",
111 "host2tcl-input-ring4",
112 "host2tcl-input-ring3",
113 "host2tcl-input-ring2",
114 "host2tcl-input-ring1",
115 "wbm2host-tx-completions-ring4",
116 "wbm2host-tx-completions-ring3",
117 "wbm2host-tx-completions-ring2",
118 "wbm2host-tx-completions-ring1",
119 "tcl2host-status-ring",
120 };
121
ath12k_pci_select_window(struct ath12k_pci * ab_pci,u32 offset)122 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset)
123 {
124 struct ath12k_base *ab = ab_pci->ab;
125
126 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK);
127 u32 static_window;
128
129 lockdep_assert_held(&ab_pci->window_lock);
130
131 /* Preserve the static window configuration and reset only dynamic window */
132 static_window = ab_pci->register_window & WINDOW_STATIC_MASK;
133 window |= static_window;
134
135 if (window != ab_pci->register_window) {
136 iowrite32(WINDOW_ENABLE_BIT | window,
137 ab->mem + WINDOW_REG_ADDRESS);
138 ioread32(ab->mem + WINDOW_REG_ADDRESS);
139 ab_pci->register_window = window;
140 }
141 }
142
ath12k_pci_select_static_window(struct ath12k_pci * ab_pci)143 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci)
144 {
145 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK);
146 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK);
147 u32 window;
148
149 window = (umac_window << 12) | (ce_window << 6);
150
151 spin_lock_bh(&ab_pci->window_lock);
152 ab_pci->register_window = window;
153 spin_unlock_bh(&ab_pci->window_lock);
154
155 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
156 }
157
ath12k_pci_get_window_start(struct ath12k_base * ab,u32 offset)158 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab,
159 u32 offset)
160 {
161 u32 window_start;
162
163 /* If offset lies within DP register range, use 3rd window */
164 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
165 window_start = 3 * WINDOW_START;
166 /* If offset lies within CE register range, use 2nd window */
167 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
168 window_start = 2 * WINDOW_START;
169 /* If offset lies within PCI_BAR_WINDOW0_BASE and within PCI_SOC_PCI_REG_BASE
170 * use 0th window
171 */
172 else if (((offset ^ PCI_BAR_WINDOW0_BASE) < WINDOW_RANGE_MASK) &&
173 !((offset ^ PCI_SOC_PCI_REG_BASE) < PCI_SOC_RANGE_MASK))
174 window_start = 0;
175 else
176 window_start = WINDOW_START;
177
178 return window_start;
179 }
180
ath12k_pci_soc_global_reset(struct ath12k_base * ab)181 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab)
182 {
183 u32 val, delay;
184
185 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
186
187 val |= PCIE_SOC_GLOBAL_RESET_V;
188
189 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
190
191 /* TODO: exact time to sleep is uncertain */
192 delay = 10;
193 mdelay(delay);
194
195 /* Need to toggle V bit back otherwise stuck in reset status */
196 val &= ~PCIE_SOC_GLOBAL_RESET_V;
197
198 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
199
200 mdelay(delay);
201
202 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
203 if (val == 0xffffffff)
204 ath12k_warn(ab, "link down error during global reset\n");
205 }
206
ath12k_pci_clear_dbg_registers(struct ath12k_base * ab)207 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab)
208 {
209 u32 val;
210
211 /* read cookie */
212 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR);
213 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val);
214
215 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
216 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
217
218 /* TODO: exact time to sleep is uncertain */
219 mdelay(10);
220
221 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
222 * continuing warm path and entering dead loop.
223 */
224 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0);
225 mdelay(10);
226
227 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
228 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
229
230 /* A read clear register. clear the register to prevent
231 * Q6 from entering wrong code path.
232 */
233 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
234 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val);
235 }
236
ath12k_pci_enable_ltssm(struct ath12k_base * ab)237 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab)
238 {
239 u32 val;
240 int i;
241
242 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
243
244 /* PCIE link seems very unstable after the Hot Reset*/
245 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
246 if (val == 0xffffffff)
247 mdelay(5);
248
249 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
250 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
251 }
252
253 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val);
254
255 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
256 val |= GCC_GCC_PCIE_HOT_RST_VAL;
257 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
258 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
259
260 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
261
262 mdelay(5);
263 }
264
ath12k_pci_clear_all_intrs(struct ath12k_base * ab)265 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab)
266 {
267 /* This is a WAR for PCIE Hotreset.
268 * When target receive Hotreset, but will set the interrupt.
269 * So when download SBL again, SBL will open Interrupt and
270 * receive it, and crash immediately.
271 */
272 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
273 }
274
ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base * ab)275 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab)
276 {
277 u32 val;
278
279 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
280 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
281 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
282 }
283
ath12k_pci_force_wake(struct ath12k_base * ab)284 static void ath12k_pci_force_wake(struct ath12k_base *ab)
285 {
286 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
287 mdelay(5);
288 }
289
ath12k_pci_sw_reset(struct ath12k_base * ab,bool power_on)290 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on)
291 {
292 if (power_on) {
293 ath12k_pci_enable_ltssm(ab);
294 ath12k_pci_clear_all_intrs(ab);
295 ath12k_pci_set_wlaon_pwr_ctrl(ab);
296 }
297
298 ath12k_mhi_clear_vector(ab);
299 ath12k_pci_clear_dbg_registers(ab);
300 ath12k_pci_soc_global_reset(ab);
301 ath12k_mhi_set_mhictrl_reset(ab);
302 }
303
ath12k_pci_free_ext_irq(struct ath12k_base * ab)304 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab)
305 {
306 int i, j;
307
308 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
309 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
310
311 for (j = 0; j < irq_grp->num_irq; j++)
312 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
313
314 netif_napi_del(&irq_grp->napi);
315 }
316 }
317
ath12k_pci_free_irq(struct ath12k_base * ab)318 static void ath12k_pci_free_irq(struct ath12k_base *ab)
319 {
320 int i, irq_idx;
321
322 for (i = 0; i < ab->hw_params->ce_count; i++) {
323 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
324 continue;
325 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
326 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
327 }
328
329 ath12k_pci_free_ext_irq(ab);
330 }
331
ath12k_pci_ce_irq_enable(struct ath12k_base * ab,u16 ce_id)332 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id)
333 {
334 u32 irq_idx;
335
336 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
337 enable_irq(ab->irq_num[irq_idx]);
338 }
339
ath12k_pci_ce_irq_disable(struct ath12k_base * ab,u16 ce_id)340 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id)
341 {
342 u32 irq_idx;
343
344 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id;
345 disable_irq_nosync(ab->irq_num[irq_idx]);
346 }
347
ath12k_pci_ce_irqs_disable(struct ath12k_base * ab)348 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab)
349 {
350 int i;
351
352 for (i = 0; i < ab->hw_params->ce_count; i++) {
353 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
354 continue;
355 ath12k_pci_ce_irq_disable(ab, i);
356 }
357 }
358
ath12k_pci_sync_ce_irqs(struct ath12k_base * ab)359 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab)
360 {
361 int i;
362 int irq_idx;
363
364 for (i = 0; i < ab->hw_params->ce_count; i++) {
365 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
366 continue;
367
368 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
369 synchronize_irq(ab->irq_num[irq_idx]);
370 }
371 }
372
ath12k_pci_ce_tasklet(struct tasklet_struct * t)373 static void ath12k_pci_ce_tasklet(struct tasklet_struct *t)
374 {
375 struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
376
377 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
378
379 ath12k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
380 }
381
ath12k_pci_ce_interrupt_handler(int irq,void * arg)382 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg)
383 {
384 struct ath12k_ce_pipe *ce_pipe = arg;
385
386 /* last interrupt received for this CE */
387 ce_pipe->timestamp = jiffies;
388
389 ath12k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
390 tasklet_schedule(&ce_pipe->intr_tq);
391
392 return IRQ_HANDLED;
393 }
394
ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp * irq_grp)395 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp)
396 {
397 int i;
398
399 for (i = 0; i < irq_grp->num_irq; i++)
400 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
401 }
402
__ath12k_pci_ext_irq_disable(struct ath12k_base * sc)403 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *sc)
404 {
405 int i;
406
407 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
408 struct ath12k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
409
410 ath12k_pci_ext_grp_disable(irq_grp);
411
412 napi_synchronize(&irq_grp->napi);
413 napi_disable(&irq_grp->napi);
414 }
415 }
416
ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp * irq_grp)417 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp)
418 {
419 int i;
420
421 for (i = 0; i < irq_grp->num_irq; i++)
422 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
423 }
424
ath12k_pci_sync_ext_irqs(struct ath12k_base * ab)425 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab)
426 {
427 int i, j, irq_idx;
428
429 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
430 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
431
432 for (j = 0; j < irq_grp->num_irq; j++) {
433 irq_idx = irq_grp->irqs[j];
434 synchronize_irq(ab->irq_num[irq_idx]);
435 }
436 }
437 }
438
ath12k_pci_ext_grp_napi_poll(struct napi_struct * napi,int budget)439 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
440 {
441 struct ath12k_ext_irq_grp *irq_grp = container_of(napi,
442 struct ath12k_ext_irq_grp,
443 napi);
444 struct ath12k_base *ab = irq_grp->ab;
445 int work_done;
446
447 work_done = ath12k_dp_service_srng(ab, irq_grp, budget);
448 if (work_done < budget) {
449 napi_complete_done(napi, work_done);
450 ath12k_pci_ext_grp_enable(irq_grp);
451 }
452
453 if (work_done > budget)
454 work_done = budget;
455
456 return work_done;
457 }
458
ath12k_pci_ext_interrupt_handler(int irq,void * arg)459 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg)
460 {
461 struct ath12k_ext_irq_grp *irq_grp = arg;
462
463 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq);
464
465 /* last interrupt received for this group */
466 irq_grp->timestamp = jiffies;
467
468 ath12k_pci_ext_grp_disable(irq_grp);
469
470 napi_schedule(&irq_grp->napi);
471
472 return IRQ_HANDLED;
473 }
474
ath12k_pci_ext_irq_config(struct ath12k_base * ab)475 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab)
476 {
477 int i, j, ret, num_vectors = 0;
478 u32 user_base_data = 0, base_vector = 0, base_idx;
479
480 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
481 ret = ath12k_pci_get_user_msi_assignment(ab, "DP",
482 &num_vectors,
483 &user_base_data,
484 &base_vector);
485 if (ret < 0)
486 return ret;
487
488 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
489 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
490 u32 num_irq = 0;
491
492 irq_grp->ab = ab;
493 irq_grp->grp_id = i;
494 init_dummy_netdev(&irq_grp->napi_ndev);
495 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
496 ath12k_pci_ext_grp_napi_poll);
497
498 if (ab->hw_params->ring_mask->tx[i] ||
499 ab->hw_params->ring_mask->rx[i] ||
500 ab->hw_params->ring_mask->rx_err[i] ||
501 ab->hw_params->ring_mask->rx_wbm_rel[i] ||
502 ab->hw_params->ring_mask->reo_status[i] ||
503 ab->hw_params->ring_mask->host2rxdma[i] ||
504 ab->hw_params->ring_mask->rx_mon_dest[i]) {
505 num_irq = 1;
506 }
507
508 irq_grp->num_irq = num_irq;
509 irq_grp->irqs[0] = base_idx + i;
510
511 for (j = 0; j < irq_grp->num_irq; j++) {
512 int irq_idx = irq_grp->irqs[j];
513 int vector = (i % num_vectors) + base_vector;
514 int irq = ath12k_pci_get_msi_irq(ab->dev, vector);
515
516 ab->irq_num[irq_idx] = irq;
517
518 ath12k_dbg(ab, ATH12K_DBG_PCI,
519 "irq:%d group:%d\n", irq, i);
520
521 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
522 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler,
523 IRQF_SHARED,
524 "DP_EXT_IRQ", irq_grp);
525 if (ret) {
526 ath12k_err(ab, "failed request irq %d: %d\n",
527 vector, ret);
528 return ret;
529 }
530
531 disable_irq_nosync(ab->irq_num[irq_idx]);
532 }
533 }
534
535 return 0;
536 }
537
ath12k_pci_config_irq(struct ath12k_base * ab)538 static int ath12k_pci_config_irq(struct ath12k_base *ab)
539 {
540 struct ath12k_ce_pipe *ce_pipe;
541 u32 msi_data_start;
542 u32 msi_data_count, msi_data_idx;
543 u32 msi_irq_start;
544 unsigned int msi_data;
545 int irq, i, ret, irq_idx;
546
547 ret = ath12k_pci_get_user_msi_assignment(ab,
548 "CE", &msi_data_count,
549 &msi_data_start, &msi_irq_start);
550 if (ret)
551 return ret;
552
553 /* Configure CE irqs */
554
555 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
556 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
557 continue;
558
559 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
560 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data);
561 ce_pipe = &ab->ce.ce_pipe[i];
562
563 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i;
564
565 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet);
566
567 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler,
568 IRQF_SHARED, irq_name[irq_idx],
569 ce_pipe);
570 if (ret) {
571 ath12k_err(ab, "failed to request irq %d: %d\n",
572 irq_idx, ret);
573 return ret;
574 }
575
576 ab->irq_num[irq_idx] = irq;
577 msi_data_idx++;
578
579 ath12k_pci_ce_irq_disable(ab, i);
580 }
581
582 ret = ath12k_pci_ext_irq_config(ab);
583 if (ret)
584 return ret;
585
586 return 0;
587 }
588
ath12k_pci_init_qmi_ce_config(struct ath12k_base * ab)589 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab)
590 {
591 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
592
593 cfg->tgt_ce = ab->hw_params->target_ce_config;
594 cfg->tgt_ce_len = ab->hw_params->target_ce_count;
595
596 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map;
597 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len;
598 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id;
599 }
600
ath12k_pci_ce_irqs_enable(struct ath12k_base * ab)601 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab)
602 {
603 int i;
604
605 for (i = 0; i < ab->hw_params->ce_count; i++) {
606 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
607 continue;
608 ath12k_pci_ce_irq_enable(ab, i);
609 }
610 }
611
ath12k_pci_msi_config(struct ath12k_pci * ab_pci,bool enable)612 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable)
613 {
614 struct pci_dev *dev = ab_pci->pdev;
615 u16 control;
616
617 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
618
619 if (enable)
620 control |= PCI_MSI_FLAGS_ENABLE;
621 else
622 control &= ~PCI_MSI_FLAGS_ENABLE;
623
624 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
625 }
626
ath12k_pci_msi_enable(struct ath12k_pci * ab_pci)627 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci)
628 {
629 ath12k_pci_msi_config(ab_pci, true);
630 }
631
ath12k_pci_msi_disable(struct ath12k_pci * ab_pci)632 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci)
633 {
634 ath12k_pci_msi_config(ab_pci, false);
635 }
636
ath12k_pci_msi_alloc(struct ath12k_pci * ab_pci)637 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci)
638 {
639 struct ath12k_base *ab = ab_pci->ab;
640 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
641 struct msi_desc *msi_desc;
642 int num_vectors;
643 int ret;
644
645 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
646 msi_config->total_vectors,
647 msi_config->total_vectors,
648 PCI_IRQ_MSI);
649 if (num_vectors != msi_config->total_vectors) {
650 ath12k_err(ab, "failed to get %d MSI vectors, only %d available",
651 msi_config->total_vectors, num_vectors);
652
653 if (num_vectors >= 0)
654 return -EINVAL;
655 else
656 return num_vectors;
657 }
658
659 ath12k_pci_msi_disable(ab_pci);
660
661 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
662 if (!msi_desc) {
663 ath12k_err(ab, "msi_desc is NULL!\n");
664 ret = -EINVAL;
665 goto free_msi_vector;
666 }
667
668 ab_pci->msi_ep_base_data = msi_desc->msg.data;
669 if (msi_desc->pci.msi_attrib.is_64)
670 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
671
672 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
673
674 return 0;
675
676 free_msi_vector:
677 pci_free_irq_vectors(ab_pci->pdev);
678
679 return ret;
680 }
681
ath12k_pci_msi_free(struct ath12k_pci * ab_pci)682 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci)
683 {
684 pci_free_irq_vectors(ab_pci->pdev);
685 }
686
ath12k_pci_claim(struct ath12k_pci * ab_pci,struct pci_dev * pdev)687 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev)
688 {
689 struct ath12k_base *ab = ab_pci->ab;
690 u16 device_id;
691 int ret = 0;
692
693 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
694 if (device_id != ab_pci->dev_id) {
695 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
696 device_id, ab_pci->dev_id);
697 ret = -EIO;
698 goto out;
699 }
700
701 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM);
702 if (ret) {
703 ath12k_err(ab, "failed to assign pci resource: %d\n", ret);
704 goto out;
705 }
706
707 ret = pci_enable_device(pdev);
708 if (ret) {
709 ath12k_err(ab, "failed to enable pci device: %d\n", ret);
710 goto out;
711 }
712
713 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci");
714 if (ret) {
715 ath12k_err(ab, "failed to request pci region: %d\n", ret);
716 goto disable_device;
717 }
718
719 ret = dma_set_mask_and_coherent(&pdev->dev,
720 DMA_BIT_MASK(ATH12K_PCI_DMA_MASK));
721 if (ret) {
722 ath12k_err(ab, "failed to set pci dma mask to %d: %d\n",
723 ATH12K_PCI_DMA_MASK, ret);
724 goto release_region;
725 }
726
727 pci_set_master(pdev);
728
729 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM);
730 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0);
731 if (!ab->mem) {
732 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM);
733 ret = -EIO;
734 goto clear_master;
735 }
736
737 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
738 return 0;
739
740 clear_master:
741 pci_clear_master(pdev);
742 release_region:
743 pci_release_region(pdev, ATH12K_PCI_BAR_NUM);
744 disable_device:
745 pci_disable_device(pdev);
746 out:
747 return ret;
748 }
749
ath12k_pci_free_region(struct ath12k_pci * ab_pci)750 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci)
751 {
752 struct ath12k_base *ab = ab_pci->ab;
753 struct pci_dev *pci_dev = ab_pci->pdev;
754
755 pci_iounmap(pci_dev, ab->mem);
756 ab->mem = NULL;
757 pci_clear_master(pci_dev);
758 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM);
759 if (pci_is_enabled(pci_dev))
760 pci_disable_device(pci_dev);
761 }
762
ath12k_pci_aspm_disable(struct ath12k_pci * ab_pci)763 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci)
764 {
765 struct ath12k_base *ab = ab_pci->ab;
766
767 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
768 &ab_pci->link_ctl);
769
770 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
771 ab_pci->link_ctl,
772 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
773 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
774
775 /* disable L0s and L1 */
776 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
777 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
778
779 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags);
780 }
781
ath12k_pci_aspm_restore(struct ath12k_pci * ab_pci)782 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci)
783 {
784 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags))
785 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
786 ab_pci->link_ctl);
787 }
788
ath12k_pci_kill_tasklets(struct ath12k_base * ab)789 static void ath12k_pci_kill_tasklets(struct ath12k_base *ab)
790 {
791 int i;
792
793 for (i = 0; i < ab->hw_params->ce_count; i++) {
794 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
795
796 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
797 continue;
798
799 tasklet_kill(&ce_pipe->intr_tq);
800 }
801 }
802
ath12k_pci_ce_irq_disable_sync(struct ath12k_base * ab)803 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab)
804 {
805 ath12k_pci_ce_irqs_disable(ab);
806 ath12k_pci_sync_ce_irqs(ab);
807 ath12k_pci_kill_tasklets(ab);
808 }
809
ath12k_pci_map_service_to_pipe(struct ath12k_base * ab,u16 service_id,u8 * ul_pipe,u8 * dl_pipe)810 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id,
811 u8 *ul_pipe, u8 *dl_pipe)
812 {
813 const struct service_to_pipe *entry;
814 bool ul_set = false, dl_set = false;
815 int i;
816
817 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) {
818 entry = &ab->hw_params->svc_to_ce_map[i];
819
820 if (__le32_to_cpu(entry->service_id) != service_id)
821 continue;
822
823 switch (__le32_to_cpu(entry->pipedir)) {
824 case PIPEDIR_NONE:
825 break;
826 case PIPEDIR_IN:
827 WARN_ON(dl_set);
828 *dl_pipe = __le32_to_cpu(entry->pipenum);
829 dl_set = true;
830 break;
831 case PIPEDIR_OUT:
832 WARN_ON(ul_set);
833 *ul_pipe = __le32_to_cpu(entry->pipenum);
834 ul_set = true;
835 break;
836 case PIPEDIR_INOUT:
837 WARN_ON(dl_set);
838 WARN_ON(ul_set);
839 *dl_pipe = __le32_to_cpu(entry->pipenum);
840 *ul_pipe = __le32_to_cpu(entry->pipenum);
841 dl_set = true;
842 ul_set = true;
843 break;
844 }
845 }
846
847 if (WARN_ON(!ul_set || !dl_set))
848 return -ENOENT;
849
850 return 0;
851 }
852
ath12k_pci_get_msi_irq(struct device * dev,unsigned int vector)853 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector)
854 {
855 struct pci_dev *pci_dev = to_pci_dev(dev);
856
857 return pci_irq_vector(pci_dev, vector);
858 }
859
ath12k_pci_get_user_msi_assignment(struct ath12k_base * ab,char * user_name,int * num_vectors,u32 * user_base_data,u32 * base_vector)860 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name,
861 int *num_vectors, u32 *user_base_data,
862 u32 *base_vector)
863 {
864 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
865 const struct ath12k_msi_config *msi_config = ab_pci->msi_config;
866 int idx;
867
868 for (idx = 0; idx < msi_config->total_users; idx++) {
869 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
870 *num_vectors = msi_config->users[idx].num_vectors;
871 *user_base_data = msi_config->users[idx].base_vector
872 + ab_pci->msi_ep_base_data;
873 *base_vector = msi_config->users[idx].base_vector;
874
875 ath12k_dbg(ab, ATH12K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
876 user_name, *num_vectors, *user_base_data,
877 *base_vector);
878
879 return 0;
880 }
881 }
882
883 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
884
885 return -EINVAL;
886 }
887
ath12k_pci_get_msi_address(struct ath12k_base * ab,u32 * msi_addr_lo,u32 * msi_addr_hi)888 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo,
889 u32 *msi_addr_hi)
890 {
891 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
892 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
893
894 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
895 msi_addr_lo);
896
897 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
898 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
899 msi_addr_hi);
900 } else {
901 *msi_addr_hi = 0;
902 }
903 }
904
ath12k_pci_get_ce_msi_idx(struct ath12k_base * ab,u32 ce_id,u32 * msi_idx)905 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id,
906 u32 *msi_idx)
907 {
908 u32 i, msi_data_idx;
909
910 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) {
911 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
912 continue;
913
914 if (ce_id == i)
915 break;
916
917 msi_data_idx++;
918 }
919 *msi_idx = msi_data_idx;
920 }
921
ath12k_pci_hif_ce_irq_enable(struct ath12k_base * ab)922 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab)
923 {
924 ath12k_pci_ce_irqs_enable(ab);
925 }
926
ath12k_pci_hif_ce_irq_disable(struct ath12k_base * ab)927 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab)
928 {
929 ath12k_pci_ce_irq_disable_sync(ab);
930 }
931
ath12k_pci_ext_irq_enable(struct ath12k_base * ab)932 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab)
933 {
934 int i;
935
936 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) {
937 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
938
939 napi_enable(&irq_grp->napi);
940 ath12k_pci_ext_grp_enable(irq_grp);
941 }
942 }
943
ath12k_pci_ext_irq_disable(struct ath12k_base * ab)944 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab)
945 {
946 __ath12k_pci_ext_irq_disable(ab);
947 ath12k_pci_sync_ext_irqs(ab);
948 }
949
ath12k_pci_hif_suspend(struct ath12k_base * ab)950 int ath12k_pci_hif_suspend(struct ath12k_base *ab)
951 {
952 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
953
954 ath12k_mhi_suspend(ar_pci);
955
956 return 0;
957 }
958
ath12k_pci_hif_resume(struct ath12k_base * ab)959 int ath12k_pci_hif_resume(struct ath12k_base *ab)
960 {
961 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab);
962
963 ath12k_mhi_resume(ar_pci);
964
965 return 0;
966 }
967
ath12k_pci_stop(struct ath12k_base * ab)968 void ath12k_pci_stop(struct ath12k_base *ab)
969 {
970 ath12k_pci_ce_irq_disable_sync(ab);
971 ath12k_ce_cleanup_pipes(ab);
972 }
973
ath12k_pci_start(struct ath12k_base * ab)974 int ath12k_pci_start(struct ath12k_base *ab)
975 {
976 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
977
978 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
979
980 ath12k_pci_aspm_restore(ab_pci);
981
982 ath12k_pci_ce_irqs_enable(ab);
983 ath12k_ce_rx_post_buf(ab);
984
985 return 0;
986 }
987
ath12k_pci_read32(struct ath12k_base * ab,u32 offset)988 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset)
989 {
990 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
991 u32 val, window_start;
992
993 /* for offset beyond BAR + 4K - 32, may
994 * need to wakeup MHI to access.
995 */
996 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
997 offset >= ACCESS_ALWAYS_OFF)
998 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
999
1000 if (offset < WINDOW_START) {
1001 val = ioread32(ab->mem + offset);
1002 } else {
1003 if (ab->static_window_map)
1004 window_start = ath12k_pci_get_window_start(ab, offset);
1005 else
1006 window_start = WINDOW_START;
1007
1008 if (window_start == WINDOW_START) {
1009 spin_lock_bh(&ab_pci->window_lock);
1010 ath12k_pci_select_window(ab_pci, offset);
1011 val = ioread32(ab->mem + window_start +
1012 (offset & WINDOW_RANGE_MASK));
1013 spin_unlock_bh(&ab_pci->window_lock);
1014 } else {
1015 if ((!window_start) &&
1016 (offset >= PCI_MHIREGLEN_REG &&
1017 offset <= PCI_MHI_REGION_END))
1018 offset = offset - PCI_MHIREGLEN_REG;
1019
1020 val = ioread32(ab->mem + window_start +
1021 (offset & WINDOW_RANGE_MASK));
1022 }
1023 }
1024
1025 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1026 offset >= ACCESS_ALWAYS_OFF)
1027 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
1028
1029 return val;
1030 }
1031
ath12k_pci_write32(struct ath12k_base * ab,u32 offset,u32 value)1032 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value)
1033 {
1034 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1035 u32 window_start;
1036
1037 /* for offset beyond BAR + 4K - 32, may
1038 * need to wakeup MHI to access.
1039 */
1040 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1041 offset >= ACCESS_ALWAYS_OFF)
1042 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
1043
1044 if (offset < WINDOW_START) {
1045 iowrite32(value, ab->mem + offset);
1046 } else {
1047 if (ab->static_window_map)
1048 window_start = ath12k_pci_get_window_start(ab, offset);
1049 else
1050 window_start = WINDOW_START;
1051
1052 if (window_start == WINDOW_START) {
1053 spin_lock_bh(&ab_pci->window_lock);
1054 ath12k_pci_select_window(ab_pci, offset);
1055 iowrite32(value, ab->mem + window_start +
1056 (offset & WINDOW_RANGE_MASK));
1057 spin_unlock_bh(&ab_pci->window_lock);
1058 } else {
1059 if ((!window_start) &&
1060 (offset >= PCI_MHIREGLEN_REG &&
1061 offset <= PCI_MHI_REGION_END))
1062 offset = offset - PCI_MHIREGLEN_REG;
1063
1064 iowrite32(value, ab->mem + window_start +
1065 (offset & WINDOW_RANGE_MASK));
1066 }
1067 }
1068
1069 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
1070 offset >= ACCESS_ALWAYS_OFF)
1071 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
1072 }
1073
ath12k_pci_power_up(struct ath12k_base * ab)1074 int ath12k_pci_power_up(struct ath12k_base *ab)
1075 {
1076 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1077 int ret;
1078
1079 ab_pci->register_window = 0;
1080 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1081 ath12k_pci_sw_reset(ab_pci->ab, true);
1082
1083 /* Disable ASPM during firmware download due to problems switching
1084 * to AMSS state.
1085 */
1086 ath12k_pci_aspm_disable(ab_pci);
1087
1088 ath12k_pci_msi_enable(ab_pci);
1089
1090 ret = ath12k_mhi_start(ab_pci);
1091 if (ret) {
1092 ath12k_err(ab, "failed to start mhi: %d\n", ret);
1093 return ret;
1094 }
1095
1096 if (ab->static_window_map)
1097 ath12k_pci_select_static_window(ab_pci);
1098
1099 return 0;
1100 }
1101
ath12k_pci_power_down(struct ath12k_base * ab)1102 void ath12k_pci_power_down(struct ath12k_base *ab)
1103 {
1104 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1105
1106 /* restore aspm in case firmware bootup fails */
1107 ath12k_pci_aspm_restore(ab_pci);
1108
1109 ath12k_pci_force_wake(ab_pci->ab);
1110 ath12k_pci_msi_disable(ab_pci);
1111 ath12k_mhi_stop(ab_pci);
1112 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1113 ath12k_pci_sw_reset(ab_pci->ab, false);
1114 }
1115
1116 static const struct ath12k_hif_ops ath12k_pci_hif_ops = {
1117 .start = ath12k_pci_start,
1118 .stop = ath12k_pci_stop,
1119 .read32 = ath12k_pci_read32,
1120 .write32 = ath12k_pci_write32,
1121 .power_down = ath12k_pci_power_down,
1122 .power_up = ath12k_pci_power_up,
1123 .suspend = ath12k_pci_hif_suspend,
1124 .resume = ath12k_pci_hif_resume,
1125 .irq_enable = ath12k_pci_ext_irq_enable,
1126 .irq_disable = ath12k_pci_ext_irq_disable,
1127 .get_msi_address = ath12k_pci_get_msi_address,
1128 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment,
1129 .map_service_to_pipe = ath12k_pci_map_service_to_pipe,
1130 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable,
1131 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable,
1132 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx,
1133 };
1134
1135 static
ath12k_pci_read_hw_version(struct ath12k_base * ab,u32 * major,u32 * minor)1136 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor)
1137 {
1138 u32 soc_hw_version;
1139
1140 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION);
1141 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
1142 soc_hw_version);
1143 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
1144 soc_hw_version);
1145
1146 ath12k_dbg(ab, ATH12K_DBG_PCI,
1147 "pci tcsr_soc_hw_version major %d minor %d\n",
1148 *major, *minor);
1149 }
1150
ath12k_pci_probe(struct pci_dev * pdev,const struct pci_device_id * pci_dev)1151 static int ath12k_pci_probe(struct pci_dev *pdev,
1152 const struct pci_device_id *pci_dev)
1153 {
1154 struct ath12k_base *ab;
1155 struct ath12k_pci *ab_pci;
1156 u32 soc_hw_version_major, soc_hw_version_minor;
1157 int ret;
1158
1159 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI);
1160 if (!ab) {
1161 dev_err(&pdev->dev, "failed to allocate ath12k base\n");
1162 return -ENOMEM;
1163 }
1164
1165 ab->dev = &pdev->dev;
1166 pci_set_drvdata(pdev, ab);
1167 ab_pci = ath12k_pci_priv(ab);
1168 ab_pci->dev_id = pci_dev->device;
1169 ab_pci->ab = ab;
1170 ab_pci->pdev = pdev;
1171 ab->hif.ops = &ath12k_pci_hif_ops;
1172 pci_set_drvdata(pdev, ab);
1173 spin_lock_init(&ab_pci->window_lock);
1174
1175 ret = ath12k_pci_claim(ab_pci, pdev);
1176 if (ret) {
1177 ath12k_err(ab, "failed to claim device: %d\n", ret);
1178 goto err_free_core;
1179 }
1180
1181 switch (pci_dev->device) {
1182 case QCN9274_DEVICE_ID:
1183 ab_pci->msi_config = &ath12k_msi_config[0];
1184 ab->static_window_map = true;
1185 ath12k_pci_read_hw_version(ab, &soc_hw_version_major,
1186 &soc_hw_version_minor);
1187 switch (soc_hw_version_major) {
1188 case ATH12K_PCI_SOC_HW_VERSION_2:
1189 ab->hw_rev = ATH12K_HW_QCN9274_HW20;
1190 break;
1191 case ATH12K_PCI_SOC_HW_VERSION_1:
1192 ab->hw_rev = ATH12K_HW_QCN9274_HW10;
1193 break;
1194 default:
1195 dev_err(&pdev->dev,
1196 "Unknown hardware version found for QCN9274: 0x%x\n",
1197 soc_hw_version_major);
1198 return -EOPNOTSUPP;
1199 }
1200 break;
1201 case WCN7850_DEVICE_ID:
1202 ab_pci->msi_config = &ath12k_msi_config[0];
1203 ab->static_window_map = false;
1204 ab->hw_rev = ATH12K_HW_WCN7850_HW20;
1205 break;
1206
1207 default:
1208 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
1209 pci_dev->device);
1210 ret = -EOPNOTSUPP;
1211 goto err_pci_free_region;
1212 }
1213
1214 ret = ath12k_pci_msi_alloc(ab_pci);
1215 if (ret) {
1216 ath12k_err(ab, "failed to alloc msi: %d\n", ret);
1217 goto err_pci_free_region;
1218 }
1219
1220 ret = ath12k_core_pre_init(ab);
1221 if (ret)
1222 goto err_pci_msi_free;
1223
1224 ret = ath12k_mhi_register(ab_pci);
1225 if (ret) {
1226 ath12k_err(ab, "failed to register mhi: %d\n", ret);
1227 goto err_pci_msi_free;
1228 }
1229
1230 ret = ath12k_hal_srng_init(ab);
1231 if (ret)
1232 goto err_mhi_unregister;
1233
1234 ret = ath12k_ce_alloc_pipes(ab);
1235 if (ret) {
1236 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1237 goto err_hal_srng_deinit;
1238 }
1239
1240 ath12k_pci_init_qmi_ce_config(ab);
1241
1242 ret = ath12k_pci_config_irq(ab);
1243 if (ret) {
1244 ath12k_err(ab, "failed to config irq: %d\n", ret);
1245 goto err_ce_free;
1246 }
1247
1248 ret = ath12k_core_init(ab);
1249 if (ret) {
1250 ath12k_err(ab, "failed to init core: %d\n", ret);
1251 goto err_free_irq;
1252 }
1253 return 0;
1254
1255 err_free_irq:
1256 ath12k_pci_free_irq(ab);
1257
1258 err_ce_free:
1259 ath12k_ce_free_pipes(ab);
1260
1261 err_hal_srng_deinit:
1262 ath12k_hal_srng_deinit(ab);
1263
1264 err_mhi_unregister:
1265 ath12k_mhi_unregister(ab_pci);
1266
1267 err_pci_msi_free:
1268 ath12k_pci_msi_free(ab_pci);
1269
1270 err_pci_free_region:
1271 ath12k_pci_free_region(ab_pci);
1272
1273 err_free_core:
1274 ath12k_core_free(ab);
1275
1276 return ret;
1277 }
1278
ath12k_pci_remove(struct pci_dev * pdev)1279 static void ath12k_pci_remove(struct pci_dev *pdev)
1280 {
1281 struct ath12k_base *ab = pci_get_drvdata(pdev);
1282 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab);
1283
1284 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1285 ath12k_pci_power_down(ab);
1286 ath12k_qmi_deinit_service(ab);
1287 goto qmi_fail;
1288 }
1289
1290 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags);
1291
1292 cancel_work_sync(&ab->reset_work);
1293 ath12k_core_deinit(ab);
1294
1295 qmi_fail:
1296 ath12k_mhi_unregister(ab_pci);
1297
1298 ath12k_pci_free_irq(ab);
1299 ath12k_pci_msi_free(ab_pci);
1300 ath12k_pci_free_region(ab_pci);
1301
1302 ath12k_hal_srng_deinit(ab);
1303 ath12k_ce_free_pipes(ab);
1304 ath12k_core_free(ab);
1305 }
1306
ath12k_pci_shutdown(struct pci_dev * pdev)1307 static void ath12k_pci_shutdown(struct pci_dev *pdev)
1308 {
1309 struct ath12k_base *ab = pci_get_drvdata(pdev);
1310
1311 ath12k_pci_power_down(ab);
1312 }
1313
ath12k_pci_pm_suspend(struct device * dev)1314 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev)
1315 {
1316 struct ath12k_base *ab = dev_get_drvdata(dev);
1317 int ret;
1318
1319 ret = ath12k_core_suspend(ab);
1320 if (ret)
1321 ath12k_warn(ab, "failed to suspend core: %d\n", ret);
1322
1323 return ret;
1324 }
1325
ath12k_pci_pm_resume(struct device * dev)1326 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev)
1327 {
1328 struct ath12k_base *ab = dev_get_drvdata(dev);
1329 int ret;
1330
1331 ret = ath12k_core_resume(ab);
1332 if (ret)
1333 ath12k_warn(ab, "failed to resume core: %d\n", ret);
1334
1335 return ret;
1336 }
1337
1338 static SIMPLE_DEV_PM_OPS(ath12k_pci_pm_ops,
1339 ath12k_pci_pm_suspend,
1340 ath12k_pci_pm_resume);
1341
1342 static struct pci_driver ath12k_pci_driver = {
1343 .name = "ath12k_pci",
1344 .id_table = ath12k_pci_id_table,
1345 .probe = ath12k_pci_probe,
1346 .remove = ath12k_pci_remove,
1347 .shutdown = ath12k_pci_shutdown,
1348 .driver.pm = &ath12k_pci_pm_ops,
1349 };
1350
ath12k_pci_init(void)1351 static int ath12k_pci_init(void)
1352 {
1353 int ret;
1354
1355 ret = pci_register_driver(&ath12k_pci_driver);
1356 if (ret) {
1357 pr_err("failed to register ath12k pci driver: %d\n",
1358 ret);
1359 return ret;
1360 }
1361
1362 return 0;
1363 }
1364 module_init(ath12k_pci_init);
1365
ath12k_pci_exit(void)1366 static void ath12k_pci_exit(void)
1367 {
1368 pci_unregister_driver(&ath12k_pci_driver);
1369 }
1370
1371 module_exit(ath12k_pci_exit);
1372
1373 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11be WLAN PCIe devices");
1374 MODULE_LICENSE("Dual BSD/GPL");
1375