1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * - Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * - Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * - Neither the name of the Altera Corporation nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #include <common.h>
29 #include <log.h>
30 #include <asm/io.h>
31 #include <dma.h>
32 #include <linux/bitops.h>
33 #include <linux/delay.h>
34 #include <linux/errno.h>
35 #include <wait_bit.h>
36 #include <spi.h>
37 #include <spi-mem.h>
38 #include <malloc.h>
39 #include "cadence_qspi.h"
40
41 #define CQSPI_REG_POLL_US 1 /* 1us */
42 #define CQSPI_REG_RETRY 10000
43 #define CQSPI_POLL_IDLE_RETRY 3
44
45 /* Transfer mode */
46 #define CQSPI_INST_TYPE_SINGLE 0
47 #define CQSPI_INST_TYPE_DUAL 1
48 #define CQSPI_INST_TYPE_QUAD 2
49 #define CQSPI_INST_TYPE_OCTAL 3
50
51 #define CQSPI_STIG_DATA_LEN_MAX 8
52
53 #define CQSPI_DUMMY_CLKS_PER_BYTE 8
54 #define CQSPI_DUMMY_CLKS_MAX 31
55
56 /****************************************************************************
57 * Controller's configuration and status register (offset from QSPI_BASE)
58 ****************************************************************************/
59 #define CQSPI_REG_CONFIG 0x00
60 #define CQSPI_REG_CONFIG_ENABLE BIT(0)
61 #define CQSPI_REG_CONFIG_CLK_POL BIT(1)
62 #define CQSPI_REG_CONFIG_CLK_PHA BIT(2)
63 #define CQSPI_REG_CONFIG_DIRECT BIT(7)
64 #define CQSPI_REG_CONFIG_DECODE BIT(9)
65 #define CQSPI_REG_CONFIG_XIP_IMM BIT(18)
66 #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
67 #define CQSPI_REG_CONFIG_BAUD_LSB 19
68 #define CQSPI_REG_CONFIG_DTR_PROTO BIT(24)
69 #define CQSPI_REG_CONFIG_DUAL_OPCODE BIT(30)
70 #define CQSPI_REG_CONFIG_IDLE_LSB 31
71 #define CQSPI_REG_CONFIG_CHIPSELECT_MASK 0xF
72 #define CQSPI_REG_CONFIG_BAUD_MASK 0xF
73
74 #define CQSPI_REG_RD_INSTR 0x04
75 #define CQSPI_REG_RD_INSTR_OPCODE_LSB 0
76 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB 8
77 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB 12
78 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB 16
79 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB 20
80 #define CQSPI_REG_RD_INSTR_DUMMY_LSB 24
81 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_MASK 0x3
82 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_MASK 0x3
83 #define CQSPI_REG_RD_INSTR_TYPE_DATA_MASK 0x3
84 #define CQSPI_REG_RD_INSTR_DUMMY_MASK 0x1F
85
86 #define CQSPI_REG_WR_INSTR 0x08
87 #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
88 #define CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB 12
89 #define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
90
91 #define CQSPI_REG_DELAY 0x0C
92 #define CQSPI_REG_DELAY_TSLCH_LSB 0
93 #define CQSPI_REG_DELAY_TCHSH_LSB 8
94 #define CQSPI_REG_DELAY_TSD2D_LSB 16
95 #define CQSPI_REG_DELAY_TSHSL_LSB 24
96 #define CQSPI_REG_DELAY_TSLCH_MASK 0xFF
97 #define CQSPI_REG_DELAY_TCHSH_MASK 0xFF
98 #define CQSPI_REG_DELAY_TSD2D_MASK 0xFF
99 #define CQSPI_REG_DELAY_TSHSL_MASK 0xFF
100
101 #define CQSPI_REG_RD_DATA_CAPTURE 0x10
102 #define CQSPI_REG_RD_DATA_CAPTURE_BYPASS BIT(0)
103 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB 1
104 #define CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK 0xF
105
106 #define CQSPI_REG_SIZE 0x14
107 #define CQSPI_REG_SIZE_ADDRESS_LSB 0
108 #define CQSPI_REG_SIZE_PAGE_LSB 4
109 #define CQSPI_REG_SIZE_BLOCK_LSB 16
110 #define CQSPI_REG_SIZE_ADDRESS_MASK 0xF
111 #define CQSPI_REG_SIZE_PAGE_MASK 0xFFF
112 #define CQSPI_REG_SIZE_BLOCK_MASK 0x3F
113
114 #define CQSPI_REG_SRAMPARTITION 0x18
115 #define CQSPI_REG_INDIRECTTRIGGER 0x1C
116
117 #define CQSPI_REG_REMAP 0x24
118 #define CQSPI_REG_MODE_BIT 0x28
119
120 #define CQSPI_REG_SDRAMLEVEL 0x2C
121 #define CQSPI_REG_SDRAMLEVEL_RD_LSB 0
122 #define CQSPI_REG_SDRAMLEVEL_WR_LSB 16
123 #define CQSPI_REG_SDRAMLEVEL_RD_MASK 0xFFFF
124 #define CQSPI_REG_SDRAMLEVEL_WR_MASK 0xFFFF
125
126 #define CQSPI_REG_WR_COMPLETION_CTRL 0x38
127 #define CQSPI_REG_WR_DISABLE_AUTO_POLL BIT(14)
128
129 #define CQSPI_REG_IRQSTATUS 0x40
130 #define CQSPI_REG_IRQMASK 0x44
131
132 #define CQSPI_REG_INDIRECTRD 0x60
133 #define CQSPI_REG_INDIRECTRD_START BIT(0)
134 #define CQSPI_REG_INDIRECTRD_CANCEL BIT(1)
135 #define CQSPI_REG_INDIRECTRD_INPROGRESS BIT(2)
136 #define CQSPI_REG_INDIRECTRD_DONE BIT(5)
137
138 #define CQSPI_REG_INDIRECTRDWATERMARK 0x64
139 #define CQSPI_REG_INDIRECTRDSTARTADDR 0x68
140 #define CQSPI_REG_INDIRECTRDBYTES 0x6C
141
142 #define CQSPI_REG_CMDCTRL 0x90
143 #define CQSPI_REG_CMDCTRL_EXECUTE BIT(0)
144 #define CQSPI_REG_CMDCTRL_INPROGRESS BIT(1)
145 #define CQSPI_REG_CMDCTRL_DUMMY_LSB 7
146 #define CQSPI_REG_CMDCTRL_WR_BYTES_LSB 12
147 #define CQSPI_REG_CMDCTRL_WR_EN_LSB 15
148 #define CQSPI_REG_CMDCTRL_ADD_BYTES_LSB 16
149 #define CQSPI_REG_CMDCTRL_ADDR_EN_LSB 19
150 #define CQSPI_REG_CMDCTRL_RD_BYTES_LSB 20
151 #define CQSPI_REG_CMDCTRL_RD_EN_LSB 23
152 #define CQSPI_REG_CMDCTRL_OPCODE_LSB 24
153 #define CQSPI_REG_CMDCTRL_DUMMY_MASK 0x1F
154 #define CQSPI_REG_CMDCTRL_WR_BYTES_MASK 0x7
155 #define CQSPI_REG_CMDCTRL_ADD_BYTES_MASK 0x3
156 #define CQSPI_REG_CMDCTRL_RD_BYTES_MASK 0x7
157 #define CQSPI_REG_CMDCTRL_OPCODE_MASK 0xFF
158
159 #define CQSPI_REG_INDIRECTWR 0x70
160 #define CQSPI_REG_INDIRECTWR_START BIT(0)
161 #define CQSPI_REG_INDIRECTWR_CANCEL BIT(1)
162 #define CQSPI_REG_INDIRECTWR_INPROGRESS BIT(2)
163 #define CQSPI_REG_INDIRECTWR_DONE BIT(5)
164
165 #define CQSPI_REG_INDIRECTWRWATERMARK 0x74
166 #define CQSPI_REG_INDIRECTWRSTARTADDR 0x78
167 #define CQSPI_REG_INDIRECTWRBYTES 0x7C
168
169 #define CQSPI_REG_CMDADDRESS 0x94
170 #define CQSPI_REG_CMDREADDATALOWER 0xA0
171 #define CQSPI_REG_CMDREADDATAUPPER 0xA4
172 #define CQSPI_REG_CMDWRITEDATALOWER 0xA8
173 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC
174
175 #define CQSPI_REG_OP_EXT_LOWER 0xE0
176 #define CQSPI_REG_OP_EXT_READ_LSB 24
177 #define CQSPI_REG_OP_EXT_WRITE_LSB 16
178 #define CQSPI_REG_OP_EXT_STIG_LSB 0
179
180 #define CQSPI_REG_IS_IDLE(base) \
181 ((readl(base + CQSPI_REG_CONFIG) >> \
182 CQSPI_REG_CONFIG_IDLE_LSB) & 0x1)
183
184 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
185 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
186 CQSPI_REG_SDRAMLEVEL_RD_LSB) & CQSPI_REG_SDRAMLEVEL_RD_MASK)
187
188 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
189 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
190 CQSPI_REG_SDRAMLEVEL_WR_LSB) & CQSPI_REG_SDRAMLEVEL_WR_MASK)
191
cadence_qspi_apb_controller_enable(void * reg_base)192 void cadence_qspi_apb_controller_enable(void *reg_base)
193 {
194 unsigned int reg;
195 reg = readl(reg_base + CQSPI_REG_CONFIG);
196 reg |= CQSPI_REG_CONFIG_ENABLE;
197 writel(reg, reg_base + CQSPI_REG_CONFIG);
198 }
199
cadence_qspi_apb_controller_disable(void * reg_base)200 void cadence_qspi_apb_controller_disable(void *reg_base)
201 {
202 unsigned int reg;
203 reg = readl(reg_base + CQSPI_REG_CONFIG);
204 reg &= ~CQSPI_REG_CONFIG_ENABLE;
205 writel(reg, reg_base + CQSPI_REG_CONFIG);
206 }
207
cadence_qspi_apb_dac_mode_enable(void * reg_base)208 void cadence_qspi_apb_dac_mode_enable(void *reg_base)
209 {
210 unsigned int reg;
211
212 reg = readl(reg_base + CQSPI_REG_CONFIG);
213 reg |= CQSPI_REG_CONFIG_DIRECT;
214 writel(reg, reg_base + CQSPI_REG_CONFIG);
215 }
216
cadence_qspi_calc_dummy(const struct spi_mem_op * op,bool dtr)217 static unsigned int cadence_qspi_calc_dummy(const struct spi_mem_op *op,
218 bool dtr)
219 {
220 unsigned int dummy_clk;
221
222 if (!op->dummy.nbytes || !op->dummy.buswidth)
223 return 0;
224
225 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth);
226 if (dtr)
227 dummy_clk /= 2;
228
229 return dummy_clk;
230 }
231
cadence_qspi_calc_rdreg(struct cadence_spi_plat * plat)232 static u32 cadence_qspi_calc_rdreg(struct cadence_spi_plat *plat)
233 {
234 u32 rdreg = 0;
235
236 rdreg |= plat->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB;
237 rdreg |= plat->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB;
238 rdreg |= plat->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
239
240 return rdreg;
241 }
242
cadence_qspi_buswidth_to_inst_type(u8 buswidth)243 static int cadence_qspi_buswidth_to_inst_type(u8 buswidth)
244 {
245 switch (buswidth) {
246 case 0:
247 case 1:
248 return CQSPI_INST_TYPE_SINGLE;
249
250 case 2:
251 return CQSPI_INST_TYPE_DUAL;
252
253 case 4:
254 return CQSPI_INST_TYPE_QUAD;
255
256 case 8:
257 return CQSPI_INST_TYPE_OCTAL;
258
259 default:
260 return -ENOTSUPP;
261 }
262 }
263
cadence_qspi_set_protocol(struct cadence_spi_plat * plat,const struct spi_mem_op * op)264 static int cadence_qspi_set_protocol(struct cadence_spi_plat *plat,
265 const struct spi_mem_op *op)
266 {
267 int ret;
268
269 plat->dtr = op->data.dtr && op->cmd.dtr && op->addr.dtr;
270
271 ret = cadence_qspi_buswidth_to_inst_type(op->cmd.buswidth);
272 if (ret < 0)
273 return ret;
274 plat->inst_width = ret;
275
276 ret = cadence_qspi_buswidth_to_inst_type(op->addr.buswidth);
277 if (ret < 0)
278 return ret;
279 plat->addr_width = ret;
280
281 ret = cadence_qspi_buswidth_to_inst_type(op->data.buswidth);
282 if (ret < 0)
283 return ret;
284 plat->data_width = ret;
285
286 return 0;
287 }
288
289 /* Return 1 if idle, otherwise return 0 (busy). */
cadence_qspi_wait_idle(void * reg_base)290 static unsigned int cadence_qspi_wait_idle(void *reg_base)
291 {
292 unsigned int start, count = 0;
293 /* timeout in unit of ms */
294 unsigned int timeout = 5000;
295
296 start = get_timer(0);
297 for ( ; get_timer(start) < timeout ; ) {
298 if (CQSPI_REG_IS_IDLE(reg_base))
299 count++;
300 else
301 count = 0;
302 /*
303 * Ensure the QSPI controller is in true idle state after
304 * reading back the same idle status consecutively
305 */
306 if (count >= CQSPI_POLL_IDLE_RETRY)
307 return 1;
308 }
309
310 /* Timeout, still in busy mode. */
311 printf("QSPI: QSPI is still busy after poll for %d times.\n",
312 CQSPI_REG_RETRY);
313 return 0;
314 }
315
cadence_qspi_apb_readdata_capture(void * reg_base,unsigned int bypass,unsigned int delay)316 void cadence_qspi_apb_readdata_capture(void *reg_base,
317 unsigned int bypass, unsigned int delay)
318 {
319 unsigned int reg;
320 cadence_qspi_apb_controller_disable(reg_base);
321
322 reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);
323
324 if (bypass)
325 reg |= CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
326 else
327 reg &= ~CQSPI_REG_RD_DATA_CAPTURE_BYPASS;
328
329 reg &= ~(CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK
330 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB);
331
332 reg |= (delay & CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK)
333 << CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB;
334
335 writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);
336
337 cadence_qspi_apb_controller_enable(reg_base);
338 }
339
cadence_qspi_apb_config_baudrate_div(void * reg_base,unsigned int ref_clk_hz,unsigned int sclk_hz)340 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
341 unsigned int ref_clk_hz, unsigned int sclk_hz)
342 {
343 unsigned int reg;
344 unsigned int div;
345
346 cadence_qspi_apb_controller_disable(reg_base);
347 reg = readl(reg_base + CQSPI_REG_CONFIG);
348 reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
349
350 /*
351 * The baud_div field in the config reg is 4 bits, and the ref clock is
352 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
353 * SPI clock rate is less than or equal to the requested clock rate.
354 */
355 div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
356
357 /* ensure the baud rate doesn't exceed the max value */
358 if (div > CQSPI_REG_CONFIG_BAUD_MASK)
359 div = CQSPI_REG_CONFIG_BAUD_MASK;
360
361 debug("%s: ref_clk %dHz sclk %dHz Div 0x%x, actual %dHz\n", __func__,
362 ref_clk_hz, sclk_hz, div, ref_clk_hz / (2 * (div + 1)));
363
364 reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB);
365 writel(reg, reg_base + CQSPI_REG_CONFIG);
366
367 cadence_qspi_apb_controller_enable(reg_base);
368 }
369
cadence_qspi_apb_set_clk_mode(void * reg_base,uint mode)370 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)
371 {
372 unsigned int reg;
373
374 cadence_qspi_apb_controller_disable(reg_base);
375 reg = readl(reg_base + CQSPI_REG_CONFIG);
376 reg &= ~(CQSPI_REG_CONFIG_CLK_POL | CQSPI_REG_CONFIG_CLK_PHA);
377
378 if (mode & SPI_CPOL)
379 reg |= CQSPI_REG_CONFIG_CLK_POL;
380 if (mode & SPI_CPHA)
381 reg |= CQSPI_REG_CONFIG_CLK_PHA;
382
383 writel(reg, reg_base + CQSPI_REG_CONFIG);
384
385 cadence_qspi_apb_controller_enable(reg_base);
386 }
387
cadence_qspi_apb_chipselect(void * reg_base,unsigned int chip_select,unsigned int decoder_enable)388 void cadence_qspi_apb_chipselect(void *reg_base,
389 unsigned int chip_select, unsigned int decoder_enable)
390 {
391 unsigned int reg;
392
393 cadence_qspi_apb_controller_disable(reg_base);
394
395 debug("%s : chipselect %d decode %d\n", __func__, chip_select,
396 decoder_enable);
397
398 reg = readl(reg_base + CQSPI_REG_CONFIG);
399 /* docoder */
400 if (decoder_enable) {
401 reg |= CQSPI_REG_CONFIG_DECODE;
402 } else {
403 reg &= ~CQSPI_REG_CONFIG_DECODE;
404 /* Convert CS if without decoder.
405 * CS0 to 4b'1110
406 * CS1 to 4b'1101
407 * CS2 to 4b'1011
408 * CS3 to 4b'0111
409 */
410 chip_select = 0xF & ~(1 << chip_select);
411 }
412
413 reg &= ~(CQSPI_REG_CONFIG_CHIPSELECT_MASK
414 << CQSPI_REG_CONFIG_CHIPSELECT_LSB);
415 reg |= (chip_select & CQSPI_REG_CONFIG_CHIPSELECT_MASK)
416 << CQSPI_REG_CONFIG_CHIPSELECT_LSB;
417 writel(reg, reg_base + CQSPI_REG_CONFIG);
418
419 cadence_qspi_apb_controller_enable(reg_base);
420 }
421
cadence_qspi_apb_delay(void * reg_base,unsigned int ref_clk,unsigned int sclk_hz,unsigned int tshsl_ns,unsigned int tsd2d_ns,unsigned int tchsh_ns,unsigned int tslch_ns)422 void cadence_qspi_apb_delay(void *reg_base,
423 unsigned int ref_clk, unsigned int sclk_hz,
424 unsigned int tshsl_ns, unsigned int tsd2d_ns,
425 unsigned int tchsh_ns, unsigned int tslch_ns)
426 {
427 unsigned int ref_clk_ns;
428 unsigned int sclk_ns;
429 unsigned int tshsl, tchsh, tslch, tsd2d;
430 unsigned int reg;
431
432 cadence_qspi_apb_controller_disable(reg_base);
433
434 /* Convert to ns. */
435 ref_clk_ns = DIV_ROUND_UP(1000000000, ref_clk);
436
437 /* Convert to ns. */
438 sclk_ns = DIV_ROUND_UP(1000000000, sclk_hz);
439
440 /* The controller adds additional delay to that programmed in the reg */
441 if (tshsl_ns >= sclk_ns + ref_clk_ns)
442 tshsl_ns -= sclk_ns + ref_clk_ns;
443 if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns)
444 tchsh_ns -= sclk_ns + 3 * ref_clk_ns;
445 tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns);
446 tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns);
447 tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns);
448 tsd2d = DIV_ROUND_UP(tsd2d_ns, ref_clk_ns);
449
450 reg = ((tshsl & CQSPI_REG_DELAY_TSHSL_MASK)
451 << CQSPI_REG_DELAY_TSHSL_LSB);
452 reg |= ((tchsh & CQSPI_REG_DELAY_TCHSH_MASK)
453 << CQSPI_REG_DELAY_TCHSH_LSB);
454 reg |= ((tslch & CQSPI_REG_DELAY_TSLCH_MASK)
455 << CQSPI_REG_DELAY_TSLCH_LSB);
456 reg |= ((tsd2d & CQSPI_REG_DELAY_TSD2D_MASK)
457 << CQSPI_REG_DELAY_TSD2D_LSB);
458 writel(reg, reg_base + CQSPI_REG_DELAY);
459
460 cadence_qspi_apb_controller_enable(reg_base);
461 }
462
cadence_qspi_apb_controller_init(struct cadence_spi_plat * plat)463 void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat)
464 {
465 unsigned reg;
466
467 cadence_qspi_apb_controller_disable(plat->regbase);
468
469 /* Configure the device size and address bytes */
470 reg = readl(plat->regbase + CQSPI_REG_SIZE);
471 /* Clear the previous value */
472 reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);
473 reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);
474 reg |= (plat->page_size << CQSPI_REG_SIZE_PAGE_LSB);
475 reg |= (plat->block_size << CQSPI_REG_SIZE_BLOCK_LSB);
476 writel(reg, plat->regbase + CQSPI_REG_SIZE);
477
478 /* Configure the remap address register, no remap */
479 writel(0, plat->regbase + CQSPI_REG_REMAP);
480
481 /* Indirect mode configurations */
482 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION);
483
484 /* Disable all interrupts */
485 writel(0, plat->regbase + CQSPI_REG_IRQMASK);
486
487 cadence_qspi_apb_controller_enable(plat->regbase);
488 }
489
cadence_qspi_apb_exec_flash_cmd(void * reg_base,unsigned int reg)490 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,
491 unsigned int reg)
492 {
493 unsigned int retry = CQSPI_REG_RETRY;
494
495 /* Write the CMDCTRL without start execution. */
496 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
497 /* Start execute */
498 reg |= CQSPI_REG_CMDCTRL_EXECUTE;
499 writel(reg, reg_base + CQSPI_REG_CMDCTRL);
500
501 while (retry--) {
502 reg = readl(reg_base + CQSPI_REG_CMDCTRL);
503 if ((reg & CQSPI_REG_CMDCTRL_INPROGRESS) == 0)
504 break;
505 udelay(1);
506 }
507
508 if (!retry) {
509 printf("QSPI: flash command execution timeout\n");
510 return -EIO;
511 }
512
513 /* Polling QSPI idle status. */
514 if (!cadence_qspi_wait_idle(reg_base))
515 return -EIO;
516
517 return 0;
518 }
519
cadence_qspi_setup_opcode_ext(struct cadence_spi_plat * plat,const struct spi_mem_op * op,unsigned int shift)520 static int cadence_qspi_setup_opcode_ext(struct cadence_spi_plat *plat,
521 const struct spi_mem_op *op,
522 unsigned int shift)
523 {
524 unsigned int reg;
525 u8 ext;
526
527 if (op->cmd.nbytes != 2)
528 return -EINVAL;
529
530 /* Opcode extension is the LSB. */
531 ext = op->cmd.opcode & 0xff;
532
533 reg = readl(plat->regbase + CQSPI_REG_OP_EXT_LOWER);
534 reg &= ~(0xff << shift);
535 reg |= ext << shift;
536 writel(reg, plat->regbase + CQSPI_REG_OP_EXT_LOWER);
537
538 return 0;
539 }
540
cadence_qspi_enable_dtr(struct cadence_spi_plat * plat,const struct spi_mem_op * op,unsigned int shift,bool enable)541 static int cadence_qspi_enable_dtr(struct cadence_spi_plat *plat,
542 const struct spi_mem_op *op,
543 unsigned int shift,
544 bool enable)
545 {
546 unsigned int reg;
547 int ret;
548
549 reg = readl(plat->regbase + CQSPI_REG_CONFIG);
550
551 if (enable) {
552 reg |= CQSPI_REG_CONFIG_DTR_PROTO;
553 reg |= CQSPI_REG_CONFIG_DUAL_OPCODE;
554
555 /* Set up command opcode extension. */
556 ret = cadence_qspi_setup_opcode_ext(plat, op, shift);
557 if (ret)
558 return ret;
559 } else {
560 reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
561 reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
562 }
563
564 writel(reg, plat->regbase + CQSPI_REG_CONFIG);
565
566 return 0;
567 }
568
cadence_qspi_apb_command_read_setup(struct cadence_spi_plat * plat,const struct spi_mem_op * op)569 int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat,
570 const struct spi_mem_op *op)
571 {
572 int ret;
573 unsigned int reg;
574
575 ret = cadence_qspi_set_protocol(plat, op);
576 if (ret)
577 return ret;
578
579 ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_STIG_LSB,
580 plat->dtr);
581 if (ret)
582 return ret;
583
584 reg = cadence_qspi_calc_rdreg(plat);
585 writel(reg, plat->regbase + CQSPI_REG_RD_INSTR);
586
587 return 0;
588 }
589
590 /* For command RDID, RDSR. */
cadence_qspi_apb_command_read(struct cadence_spi_plat * plat,const struct spi_mem_op * op)591 int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat,
592 const struct spi_mem_op *op)
593 {
594 void *reg_base = plat->regbase;
595 unsigned int reg;
596 unsigned int read_len;
597 int status;
598 unsigned int rxlen = op->data.nbytes;
599 void *rxbuf = op->data.buf.in;
600 unsigned int dummy_clk;
601 u8 opcode;
602
603 if (rxlen > CQSPI_STIG_DATA_LEN_MAX || !rxbuf) {
604 printf("QSPI: Invalid input arguments rxlen %u\n", rxlen);
605 return -EINVAL;
606 }
607
608 if (plat->dtr)
609 opcode = op->cmd.opcode >> 8;
610 else
611 opcode = op->cmd.opcode;
612
613 reg = opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
614
615 /* Set up dummy cycles. */
616 dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr);
617 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
618 return -ENOTSUPP;
619
620 if (dummy_clk)
621 reg |= (dummy_clk & CQSPI_REG_CMDCTRL_DUMMY_MASK)
622 << CQSPI_REG_CMDCTRL_DUMMY_LSB;
623
624 reg |= (0x1 << CQSPI_REG_CMDCTRL_RD_EN_LSB);
625
626 /* 0 means 1 byte. */
627 reg |= (((rxlen - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK)
628 << CQSPI_REG_CMDCTRL_RD_BYTES_LSB);
629 status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
630 if (status != 0)
631 return status;
632
633 reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);
634
635 /* Put the read value into rx_buf */
636 read_len = (rxlen > 4) ? 4 : rxlen;
637 memcpy(rxbuf, ®, read_len);
638 rxbuf += read_len;
639
640 if (rxlen > 4) {
641 reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);
642
643 read_len = rxlen - read_len;
644 memcpy(rxbuf, ®, read_len);
645 }
646 return 0;
647 }
648
cadence_qspi_apb_command_write_setup(struct cadence_spi_plat * plat,const struct spi_mem_op * op)649 int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat,
650 const struct spi_mem_op *op)
651 {
652 int ret;
653 unsigned int reg;
654
655 ret = cadence_qspi_set_protocol(plat, op);
656 if (ret)
657 return ret;
658
659 ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_STIG_LSB,
660 plat->dtr);
661 if (ret)
662 return ret;
663
664 reg = cadence_qspi_calc_rdreg(plat);
665 writel(reg, plat->regbase + CQSPI_REG_RD_INSTR);
666
667 return 0;
668 }
669
670 /* For commands: WRSR, WREN, WRDI, CHIP_ERASE, BE, etc. */
cadence_qspi_apb_command_write(struct cadence_spi_plat * plat,const struct spi_mem_op * op)671 int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat,
672 const struct spi_mem_op *op)
673 {
674 unsigned int reg = 0;
675 unsigned int wr_data;
676 unsigned int wr_len;
677 unsigned int txlen = op->data.nbytes;
678 const void *txbuf = op->data.buf.out;
679 void *reg_base = plat->regbase;
680 u32 addr;
681 u8 opcode;
682
683 /* Reorder address to SPI bus order if only transferring address */
684 if (!txlen) {
685 addr = cpu_to_be32(op->addr.val);
686 if (op->addr.nbytes == 3)
687 addr >>= 8;
688 txbuf = &addr;
689 txlen = op->addr.nbytes;
690 }
691
692 if (txlen > CQSPI_STIG_DATA_LEN_MAX) {
693 printf("QSPI: Invalid input arguments txlen %u\n", txlen);
694 return -EINVAL;
695 }
696
697 if (plat->dtr)
698 opcode = op->cmd.opcode >> 8;
699 else
700 opcode = op->cmd.opcode;
701
702 reg |= opcode << CQSPI_REG_CMDCTRL_OPCODE_LSB;
703
704 if (txlen) {
705 /* writing data = yes */
706 reg |= (0x1 << CQSPI_REG_CMDCTRL_WR_EN_LSB);
707 reg |= ((txlen - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK)
708 << CQSPI_REG_CMDCTRL_WR_BYTES_LSB;
709
710 wr_len = txlen > 4 ? 4 : txlen;
711 memcpy(&wr_data, txbuf, wr_len);
712 writel(wr_data, reg_base +
713 CQSPI_REG_CMDWRITEDATALOWER);
714
715 if (txlen > 4) {
716 txbuf += wr_len;
717 wr_len = txlen - wr_len;
718 memcpy(&wr_data, txbuf, wr_len);
719 writel(wr_data, reg_base +
720 CQSPI_REG_CMDWRITEDATAUPPER);
721 }
722 }
723
724 /* Execute the command */
725 return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);
726 }
727
728 /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */
cadence_qspi_apb_read_setup(struct cadence_spi_plat * plat,const struct spi_mem_op * op)729 int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat,
730 const struct spi_mem_op *op)
731 {
732 unsigned int reg;
733 unsigned int rd_reg;
734 unsigned int dummy_clk;
735 unsigned int dummy_bytes = op->dummy.nbytes;
736 int ret;
737 u8 opcode;
738
739 ret = cadence_qspi_set_protocol(plat, op);
740 if (ret)
741 return ret;
742
743 ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_READ_LSB,
744 plat->dtr);
745 if (ret)
746 return ret;
747
748 /* Setup the indirect trigger address */
749 writel(plat->trigger_address,
750 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
751
752 /* Configure the opcode */
753 if (plat->dtr)
754 opcode = op->cmd.opcode >> 8;
755 else
756 opcode = op->cmd.opcode;
757
758 rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
759 rd_reg |= cadence_qspi_calc_rdreg(plat);
760
761 writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
762
763 if (dummy_bytes) {
764 /* Convert to clock cycles. */
765 dummy_clk = cadence_qspi_calc_dummy(op, plat->dtr);
766
767 if (dummy_clk > CQSPI_DUMMY_CLKS_MAX)
768 return -ENOTSUPP;
769
770 if (dummy_clk)
771 rd_reg |= (dummy_clk & CQSPI_REG_RD_INSTR_DUMMY_MASK)
772 << CQSPI_REG_RD_INSTR_DUMMY_LSB;
773 }
774
775 writel(rd_reg, plat->regbase + CQSPI_REG_RD_INSTR);
776
777 /* set device size */
778 reg = readl(plat->regbase + CQSPI_REG_SIZE);
779 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
780 reg |= (op->addr.nbytes - 1);
781 writel(reg, plat->regbase + CQSPI_REG_SIZE);
782 return 0;
783 }
784
cadence_qspi_get_rd_sram_level(struct cadence_spi_plat * plat)785 static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_plat *plat)
786 {
787 u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
788 reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
789 return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
790 }
791
cadence_qspi_wait_for_data(struct cadence_spi_plat * plat)792 static int cadence_qspi_wait_for_data(struct cadence_spi_plat *plat)
793 {
794 unsigned int timeout = 10000;
795 u32 reg;
796
797 while (timeout--) {
798 reg = cadence_qspi_get_rd_sram_level(plat);
799 if (reg)
800 return reg;
801 udelay(1);
802 }
803
804 return -ETIMEDOUT;
805 }
806
807 static int
cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat * plat,unsigned int n_rx,u8 * rxbuf)808 cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
809 unsigned int n_rx, u8 *rxbuf)
810 {
811 unsigned int remaining = n_rx;
812 unsigned int bytes_to_read = 0;
813 int ret;
814
815 writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
816
817 /* Start the indirect read transfer */
818 writel(CQSPI_REG_INDIRECTRD_START,
819 plat->regbase + CQSPI_REG_INDIRECTRD);
820
821 while (remaining > 0) {
822 ret = cadence_qspi_wait_for_data(plat);
823 if (ret < 0) {
824 printf("Indirect write timed out (%i)\n", ret);
825 goto failrd;
826 }
827
828 bytes_to_read = ret;
829
830 while (bytes_to_read != 0) {
831 bytes_to_read *= plat->fifo_width;
832 bytes_to_read = bytes_to_read > remaining ?
833 remaining : bytes_to_read;
834 /*
835 * Handle non-4-byte aligned access to avoid
836 * data abort.
837 */
838 if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
839 readsb(plat->ahbbase, rxbuf, bytes_to_read);
840 else
841 readsl(plat->ahbbase, rxbuf,
842 bytes_to_read >> 2);
843 rxbuf += bytes_to_read;
844 remaining -= bytes_to_read;
845 bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
846 }
847 }
848
849 /* Check indirect done status */
850 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
851 CQSPI_REG_INDIRECTRD_DONE, 1, 10, 0);
852 if (ret) {
853 printf("Indirect read completion error (%i)\n", ret);
854 goto failrd;
855 }
856
857 /* Clear indirect completion status */
858 writel(CQSPI_REG_INDIRECTRD_DONE,
859 plat->regbase + CQSPI_REG_INDIRECTRD);
860
861 return 0;
862
863 failrd:
864 /* Cancel the indirect read */
865 writel(CQSPI_REG_INDIRECTRD_CANCEL,
866 plat->regbase + CQSPI_REG_INDIRECTRD);
867 return ret;
868 }
869
cadence_qspi_apb_read_execute(struct cadence_spi_plat * plat,const struct spi_mem_op * op)870 int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat,
871 const struct spi_mem_op *op)
872 {
873 u64 from = op->addr.val;
874 void *buf = op->data.buf.in;
875 size_t len = op->data.nbytes;
876
877 if (plat->use_dac_mode && (from + len < plat->ahbsize)) {
878 if (len < 256 ||
879 dma_memcpy(buf, plat->ahbbase + from, len) < 0) {
880 memcpy_fromio(buf, plat->ahbbase + from, len);
881 }
882 if (!cadence_qspi_wait_idle(plat->regbase))
883 return -EIO;
884 return 0;
885 }
886
887 return cadence_qspi_apb_indirect_read_execute(plat, len, buf);
888 }
889
890 /* Opcode + Address (3/4 bytes) */
cadence_qspi_apb_write_setup(struct cadence_spi_plat * plat,const struct spi_mem_op * op)891 int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat,
892 const struct spi_mem_op *op)
893 {
894 unsigned int reg;
895 int ret;
896 u8 opcode;
897
898 ret = cadence_qspi_set_protocol(plat, op);
899 if (ret)
900 return ret;
901
902 ret = cadence_qspi_enable_dtr(plat, op, CQSPI_REG_OP_EXT_WRITE_LSB,
903 plat->dtr);
904 if (ret)
905 return ret;
906
907 /* Setup the indirect trigger address */
908 writel(plat->trigger_address,
909 plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
910
911 /* Configure the opcode */
912 if (plat->dtr)
913 opcode = op->cmd.opcode >> 8;
914 else
915 opcode = op->cmd.opcode;
916
917 reg = opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
918 reg |= plat->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
919 reg |= plat->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB;
920 writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
921
922 reg = cadence_qspi_calc_rdreg(plat);
923 writel(reg, plat->regbase + CQSPI_REG_RD_INSTR);
924
925 writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);
926
927 if (plat->dtr) {
928 /*
929 * Some flashes like the cypress Semper flash expect a 4-byte
930 * dummy address with the Read SR command in DTR mode, but this
931 * controller does not support sending address with the Read SR
932 * command. So, disable write completion polling on the
933 * controller's side. spi-nor will take care of polling the
934 * status register.
935 */
936 reg = readl(plat->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
937 reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
938 writel(reg, plat->regbase + CQSPI_REG_WR_COMPLETION_CTRL);
939 }
940
941 reg = readl(plat->regbase + CQSPI_REG_SIZE);
942 reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
943 reg |= (op->addr.nbytes - 1);
944 writel(reg, plat->regbase + CQSPI_REG_SIZE);
945 return 0;
946 }
947
948 static int
cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat * plat,unsigned int n_tx,const u8 * txbuf)949 cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
950 unsigned int n_tx, const u8 *txbuf)
951 {
952 unsigned int page_size = plat->page_size;
953 unsigned int remaining = n_tx;
954 const u8 *bb_txbuf = txbuf;
955 void *bounce_buf = NULL;
956 unsigned int write_bytes;
957 int ret;
958
959 /*
960 * Use bounce buffer for non 32 bit aligned txbuf to avoid data
961 * aborts
962 */
963 if ((uintptr_t)txbuf % 4) {
964 bounce_buf = malloc(n_tx);
965 if (!bounce_buf)
966 return -ENOMEM;
967 memcpy(bounce_buf, txbuf, n_tx);
968 bb_txbuf = bounce_buf;
969 }
970
971 /* Configure the indirect read transfer bytes */
972 writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
973
974 /* Start the indirect write transfer */
975 writel(CQSPI_REG_INDIRECTWR_START,
976 plat->regbase + CQSPI_REG_INDIRECTWR);
977
978 /*
979 * Some delay is required for the above bit to be internally
980 * synchronized by the QSPI module.
981 */
982 ndelay(plat->wr_delay);
983
984 while (remaining > 0) {
985 write_bytes = remaining > page_size ? page_size : remaining;
986 writesl(plat->ahbbase, bb_txbuf, write_bytes >> 2);
987 if (write_bytes % 4)
988 writesb(plat->ahbbase,
989 bb_txbuf + rounddown(write_bytes, 4),
990 write_bytes % 4);
991
992 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_SDRAMLEVEL,
993 CQSPI_REG_SDRAMLEVEL_WR_MASK <<
994 CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
995 if (ret) {
996 printf("Indirect write timed out (%i)\n", ret);
997 goto failwr;
998 }
999
1000 bb_txbuf += write_bytes;
1001 remaining -= write_bytes;
1002 }
1003
1004 /* Check indirect done status */
1005 ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
1006 CQSPI_REG_INDIRECTWR_DONE, 1, 10, 0);
1007 if (ret) {
1008 printf("Indirect write completion error (%i)\n", ret);
1009 goto failwr;
1010 }
1011
1012 /* Clear indirect completion status */
1013 writel(CQSPI_REG_INDIRECTWR_DONE,
1014 plat->regbase + CQSPI_REG_INDIRECTWR);
1015 if (bounce_buf)
1016 free(bounce_buf);
1017 return 0;
1018
1019 failwr:
1020 /* Cancel the indirect write */
1021 writel(CQSPI_REG_INDIRECTWR_CANCEL,
1022 plat->regbase + CQSPI_REG_INDIRECTWR);
1023 if (bounce_buf)
1024 free(bounce_buf);
1025 return ret;
1026 }
1027
cadence_qspi_apb_write_execute(struct cadence_spi_plat * plat,const struct spi_mem_op * op)1028 int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat,
1029 const struct spi_mem_op *op)
1030 {
1031 u32 to = op->addr.val;
1032 const void *buf = op->data.buf.out;
1033 size_t len = op->data.nbytes;
1034
1035 /*
1036 * Some flashes like the Cypress Semper flash expect a dummy 4-byte
1037 * address (all 0s) with the read status register command in DTR mode.
1038 * But this controller does not support sending dummy address bytes to
1039 * the flash when it is polling the write completion register in DTR
1040 * mode. So, we can not use direct mode when in DTR mode for writing
1041 * data.
1042 */
1043 if (!plat->dtr && plat->use_dac_mode && (to + len < plat->ahbsize)) {
1044 memcpy_toio(plat->ahbbase + to, buf, len);
1045 if (!cadence_qspi_wait_idle(plat->regbase))
1046 return -EIO;
1047 return 0;
1048 }
1049
1050 return cadence_qspi_apb_indirect_write_execute(plat, len, buf);
1051 }
1052
cadence_qspi_apb_enter_xip(void * reg_base,char xip_dummy)1053 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
1054 {
1055 unsigned int reg;
1056
1057 /* enter XiP mode immediately and enable direct mode */
1058 reg = readl(reg_base + CQSPI_REG_CONFIG);
1059 reg |= CQSPI_REG_CONFIG_ENABLE;
1060 reg |= CQSPI_REG_CONFIG_DIRECT;
1061 reg |= CQSPI_REG_CONFIG_XIP_IMM;
1062 writel(reg, reg_base + CQSPI_REG_CONFIG);
1063
1064 /* keep the XiP mode */
1065 writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);
1066
1067 /* Enable mode bit at devrd */
1068 reg = readl(reg_base + CQSPI_REG_RD_INSTR);
1069 reg |= (1 << CQSPI_REG_RD_INSTR_MODE_EN_LSB);
1070 writel(reg, reg_base + CQSPI_REG_RD_INSTR);
1071 }
1072