1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * cs42l42.c -- CS42L42 ALSA SoC audio driver
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
10 */
11
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/version.h>
15 #include <linux/types.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/gpio.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21 #include <linux/acpi.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/property.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/of_device.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/soc-dapm.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
35 #include <dt-bindings/sound/cs42l42.h>
36
37 #include "cs42l42.h"
38 #include "cirrus_legacy.h"
39
40 static const char * const cs42l42_supply_names[] = {
41 "VA",
42 "VP",
43 "VCP",
44 "VD_FILT",
45 "VL",
46 };
47
48 static const struct reg_default cs42l42_reg_defaults[] = {
49 { CS42L42_FRZ_CTL, 0x00 },
50 { CS42L42_SRC_CTL, 0x10 },
51 { CS42L42_MCLK_CTL, 0x02 },
52 { CS42L42_SFTRAMP_RATE, 0xA4 },
53 { CS42L42_SLOW_START_ENABLE, 0x70 },
54 { CS42L42_I2C_DEBOUNCE, 0x88 },
55 { CS42L42_I2C_STRETCH, 0x03 },
56 { CS42L42_I2C_TIMEOUT, 0xB7 },
57 { CS42L42_PWR_CTL1, 0xFF },
58 { CS42L42_PWR_CTL2, 0x84 },
59 { CS42L42_PWR_CTL3, 0x20 },
60 { CS42L42_RSENSE_CTL1, 0x40 },
61 { CS42L42_RSENSE_CTL2, 0x00 },
62 { CS42L42_OSC_SWITCH, 0x00 },
63 { CS42L42_RSENSE_CTL3, 0x1B },
64 { CS42L42_TSENSE_CTL, 0x1B },
65 { CS42L42_TSRS_INT_DISABLE, 0x00 },
66 { CS42L42_HSDET_CTL1, 0x77 },
67 { CS42L42_HSDET_CTL2, 0x00 },
68 { CS42L42_HS_SWITCH_CTL, 0xF3 },
69 { CS42L42_HS_CLAMP_DISABLE, 0x00 },
70 { CS42L42_MCLK_SRC_SEL, 0x00 },
71 { CS42L42_SPDIF_CLK_CFG, 0x00 },
72 { CS42L42_FSYNC_PW_LOWER, 0x00 },
73 { CS42L42_FSYNC_PW_UPPER, 0x00 },
74 { CS42L42_FSYNC_P_LOWER, 0xF9 },
75 { CS42L42_FSYNC_P_UPPER, 0x00 },
76 { CS42L42_ASP_CLK_CFG, 0x00 },
77 { CS42L42_ASP_FRM_CFG, 0x10 },
78 { CS42L42_FS_RATE_EN, 0x00 },
79 { CS42L42_IN_ASRC_CLK, 0x00 },
80 { CS42L42_OUT_ASRC_CLK, 0x00 },
81 { CS42L42_PLL_DIV_CFG1, 0x00 },
82 { CS42L42_ADC_OVFL_INT_MASK, 0x01 },
83 { CS42L42_MIXER_INT_MASK, 0x0F },
84 { CS42L42_SRC_INT_MASK, 0x0F },
85 { CS42L42_ASP_RX_INT_MASK, 0x1F },
86 { CS42L42_ASP_TX_INT_MASK, 0x0F },
87 { CS42L42_CODEC_INT_MASK, 0x03 },
88 { CS42L42_SRCPL_INT_MASK, 0x7F },
89 { CS42L42_VPMON_INT_MASK, 0x01 },
90 { CS42L42_PLL_LOCK_INT_MASK, 0x01 },
91 { CS42L42_TSRS_PLUG_INT_MASK, 0x0F },
92 { CS42L42_PLL_CTL1, 0x00 },
93 { CS42L42_PLL_DIV_FRAC0, 0x00 },
94 { CS42L42_PLL_DIV_FRAC1, 0x00 },
95 { CS42L42_PLL_DIV_FRAC2, 0x00 },
96 { CS42L42_PLL_DIV_INT, 0x40 },
97 { CS42L42_PLL_CTL3, 0x10 },
98 { CS42L42_PLL_CAL_RATIO, 0x80 },
99 { CS42L42_PLL_CTL4, 0x03 },
100 { CS42L42_LOAD_DET_EN, 0x00 },
101 { CS42L42_HSBIAS_SC_AUTOCTL, 0x03 },
102 { CS42L42_WAKE_CTL, 0xC0 },
103 { CS42L42_ADC_DISABLE_MUTE, 0x00 },
104 { CS42L42_TIPSENSE_CTL, 0x02 },
105 { CS42L42_MISC_DET_CTL, 0x03 },
106 { CS42L42_MIC_DET_CTL1, 0x1F },
107 { CS42L42_MIC_DET_CTL2, 0x2F },
108 { CS42L42_DET_INT1_MASK, 0xE0 },
109 { CS42L42_DET_INT2_MASK, 0xFF },
110 { CS42L42_HS_BIAS_CTL, 0xC2 },
111 { CS42L42_ADC_CTL, 0x00 },
112 { CS42L42_ADC_VOLUME, 0x00 },
113 { CS42L42_ADC_WNF_HPF_CTL, 0x71 },
114 { CS42L42_DAC_CTL1, 0x00 },
115 { CS42L42_DAC_CTL2, 0x02 },
116 { CS42L42_HP_CTL, 0x0D },
117 { CS42L42_CLASSH_CTL, 0x07 },
118 { CS42L42_MIXER_CHA_VOL, 0x3F },
119 { CS42L42_MIXER_ADC_VOL, 0x3F },
120 { CS42L42_MIXER_CHB_VOL, 0x3F },
121 { CS42L42_EQ_COEF_IN0, 0x00 },
122 { CS42L42_EQ_COEF_IN1, 0x00 },
123 { CS42L42_EQ_COEF_IN2, 0x00 },
124 { CS42L42_EQ_COEF_IN3, 0x00 },
125 { CS42L42_EQ_COEF_RW, 0x00 },
126 { CS42L42_EQ_COEF_OUT0, 0x00 },
127 { CS42L42_EQ_COEF_OUT1, 0x00 },
128 { CS42L42_EQ_COEF_OUT2, 0x00 },
129 { CS42L42_EQ_COEF_OUT3, 0x00 },
130 { CS42L42_EQ_INIT_STAT, 0x00 },
131 { CS42L42_EQ_START_FILT, 0x00 },
132 { CS42L42_EQ_MUTE_CTL, 0x00 },
133 { CS42L42_SP_RX_CH_SEL, 0x04 },
134 { CS42L42_SP_RX_ISOC_CTL, 0x04 },
135 { CS42L42_SP_RX_FS, 0x8C },
136 { CS42l42_SPDIF_CH_SEL, 0x0E },
137 { CS42L42_SP_TX_ISOC_CTL, 0x04 },
138 { CS42L42_SP_TX_FS, 0xCC },
139 { CS42L42_SPDIF_SW_CTL1, 0x3F },
140 { CS42L42_SRC_SDIN_FS, 0x40 },
141 { CS42L42_SRC_SDOUT_FS, 0x40 },
142 { CS42L42_SPDIF_CTL1, 0x01 },
143 { CS42L42_SPDIF_CTL2, 0x00 },
144 { CS42L42_SPDIF_CTL3, 0x00 },
145 { CS42L42_SPDIF_CTL4, 0x42 },
146 { CS42L42_ASP_TX_SZ_EN, 0x00 },
147 { CS42L42_ASP_TX_CH_EN, 0x00 },
148 { CS42L42_ASP_TX_CH_AP_RES, 0x0F },
149 { CS42L42_ASP_TX_CH1_BIT_MSB, 0x00 },
150 { CS42L42_ASP_TX_CH1_BIT_LSB, 0x00 },
151 { CS42L42_ASP_TX_HIZ_DLY_CFG, 0x00 },
152 { CS42L42_ASP_TX_CH2_BIT_MSB, 0x00 },
153 { CS42L42_ASP_TX_CH2_BIT_LSB, 0x00 },
154 { CS42L42_ASP_RX_DAI0_EN, 0x00 },
155 { CS42L42_ASP_RX_DAI0_CH1_AP_RES, 0x03 },
156 { CS42L42_ASP_RX_DAI0_CH1_BIT_MSB, 0x00 },
157 { CS42L42_ASP_RX_DAI0_CH1_BIT_LSB, 0x00 },
158 { CS42L42_ASP_RX_DAI0_CH2_AP_RES, 0x03 },
159 { CS42L42_ASP_RX_DAI0_CH2_BIT_MSB, 0x00 },
160 { CS42L42_ASP_RX_DAI0_CH2_BIT_LSB, 0x00 },
161 { CS42L42_ASP_RX_DAI0_CH3_AP_RES, 0x03 },
162 { CS42L42_ASP_RX_DAI0_CH3_BIT_MSB, 0x00 },
163 { CS42L42_ASP_RX_DAI0_CH3_BIT_LSB, 0x00 },
164 { CS42L42_ASP_RX_DAI0_CH4_AP_RES, 0x03 },
165 { CS42L42_ASP_RX_DAI0_CH4_BIT_MSB, 0x00 },
166 { CS42L42_ASP_RX_DAI0_CH4_BIT_LSB, 0x00 },
167 { CS42L42_ASP_RX_DAI1_CH1_AP_RES, 0x03 },
168 { CS42L42_ASP_RX_DAI1_CH1_BIT_MSB, 0x00 },
169 { CS42L42_ASP_RX_DAI1_CH1_BIT_LSB, 0x00 },
170 { CS42L42_ASP_RX_DAI1_CH2_AP_RES, 0x03 },
171 { CS42L42_ASP_RX_DAI1_CH2_BIT_MSB, 0x00 },
172 { CS42L42_ASP_RX_DAI1_CH2_BIT_LSB, 0x00 },
173 };
174
cs42l42_readable_register(struct device * dev,unsigned int reg)175 bool cs42l42_readable_register(struct device *dev, unsigned int reg)
176 {
177 switch (reg) {
178 case CS42L42_PAGE_REGISTER:
179 case CS42L42_DEVID_AB:
180 case CS42L42_DEVID_CD:
181 case CS42L42_DEVID_E:
182 case CS42L42_FABID:
183 case CS42L42_REVID:
184 case CS42L42_FRZ_CTL:
185 case CS42L42_SRC_CTL:
186 case CS42L42_MCLK_STATUS:
187 case CS42L42_MCLK_CTL:
188 case CS42L42_SFTRAMP_RATE:
189 case CS42L42_SLOW_START_ENABLE:
190 case CS42L42_I2C_DEBOUNCE:
191 case CS42L42_I2C_STRETCH:
192 case CS42L42_I2C_TIMEOUT:
193 case CS42L42_PWR_CTL1:
194 case CS42L42_PWR_CTL2:
195 case CS42L42_PWR_CTL3:
196 case CS42L42_RSENSE_CTL1:
197 case CS42L42_RSENSE_CTL2:
198 case CS42L42_OSC_SWITCH:
199 case CS42L42_OSC_SWITCH_STATUS:
200 case CS42L42_RSENSE_CTL3:
201 case CS42L42_TSENSE_CTL:
202 case CS42L42_TSRS_INT_DISABLE:
203 case CS42L42_TRSENSE_STATUS:
204 case CS42L42_HSDET_CTL1:
205 case CS42L42_HSDET_CTL2:
206 case CS42L42_HS_SWITCH_CTL:
207 case CS42L42_HS_DET_STATUS:
208 case CS42L42_HS_CLAMP_DISABLE:
209 case CS42L42_MCLK_SRC_SEL:
210 case CS42L42_SPDIF_CLK_CFG:
211 case CS42L42_FSYNC_PW_LOWER:
212 case CS42L42_FSYNC_PW_UPPER:
213 case CS42L42_FSYNC_P_LOWER:
214 case CS42L42_FSYNC_P_UPPER:
215 case CS42L42_ASP_CLK_CFG:
216 case CS42L42_ASP_FRM_CFG:
217 case CS42L42_FS_RATE_EN:
218 case CS42L42_IN_ASRC_CLK:
219 case CS42L42_OUT_ASRC_CLK:
220 case CS42L42_PLL_DIV_CFG1:
221 case CS42L42_ADC_OVFL_STATUS:
222 case CS42L42_MIXER_STATUS:
223 case CS42L42_SRC_STATUS:
224 case CS42L42_ASP_RX_STATUS:
225 case CS42L42_ASP_TX_STATUS:
226 case CS42L42_CODEC_STATUS:
227 case CS42L42_DET_INT_STATUS1:
228 case CS42L42_DET_INT_STATUS2:
229 case CS42L42_SRCPL_INT_STATUS:
230 case CS42L42_VPMON_STATUS:
231 case CS42L42_PLL_LOCK_STATUS:
232 case CS42L42_TSRS_PLUG_STATUS:
233 case CS42L42_ADC_OVFL_INT_MASK:
234 case CS42L42_MIXER_INT_MASK:
235 case CS42L42_SRC_INT_MASK:
236 case CS42L42_ASP_RX_INT_MASK:
237 case CS42L42_ASP_TX_INT_MASK:
238 case CS42L42_CODEC_INT_MASK:
239 case CS42L42_SRCPL_INT_MASK:
240 case CS42L42_VPMON_INT_MASK:
241 case CS42L42_PLL_LOCK_INT_MASK:
242 case CS42L42_TSRS_PLUG_INT_MASK:
243 case CS42L42_PLL_CTL1:
244 case CS42L42_PLL_DIV_FRAC0:
245 case CS42L42_PLL_DIV_FRAC1:
246 case CS42L42_PLL_DIV_FRAC2:
247 case CS42L42_PLL_DIV_INT:
248 case CS42L42_PLL_CTL3:
249 case CS42L42_PLL_CAL_RATIO:
250 case CS42L42_PLL_CTL4:
251 case CS42L42_LOAD_DET_RCSTAT:
252 case CS42L42_LOAD_DET_DONE:
253 case CS42L42_LOAD_DET_EN:
254 case CS42L42_HSBIAS_SC_AUTOCTL:
255 case CS42L42_WAKE_CTL:
256 case CS42L42_ADC_DISABLE_MUTE:
257 case CS42L42_TIPSENSE_CTL:
258 case CS42L42_MISC_DET_CTL:
259 case CS42L42_MIC_DET_CTL1:
260 case CS42L42_MIC_DET_CTL2:
261 case CS42L42_DET_STATUS1:
262 case CS42L42_DET_STATUS2:
263 case CS42L42_DET_INT1_MASK:
264 case CS42L42_DET_INT2_MASK:
265 case CS42L42_HS_BIAS_CTL:
266 case CS42L42_ADC_CTL:
267 case CS42L42_ADC_VOLUME:
268 case CS42L42_ADC_WNF_HPF_CTL:
269 case CS42L42_DAC_CTL1:
270 case CS42L42_DAC_CTL2:
271 case CS42L42_HP_CTL:
272 case CS42L42_CLASSH_CTL:
273 case CS42L42_MIXER_CHA_VOL:
274 case CS42L42_MIXER_ADC_VOL:
275 case CS42L42_MIXER_CHB_VOL:
276 case CS42L42_EQ_COEF_IN0:
277 case CS42L42_EQ_COEF_IN1:
278 case CS42L42_EQ_COEF_IN2:
279 case CS42L42_EQ_COEF_IN3:
280 case CS42L42_EQ_COEF_RW:
281 case CS42L42_EQ_COEF_OUT0:
282 case CS42L42_EQ_COEF_OUT1:
283 case CS42L42_EQ_COEF_OUT2:
284 case CS42L42_EQ_COEF_OUT3:
285 case CS42L42_EQ_INIT_STAT:
286 case CS42L42_EQ_START_FILT:
287 case CS42L42_EQ_MUTE_CTL:
288 case CS42L42_SP_RX_CH_SEL:
289 case CS42L42_SP_RX_ISOC_CTL:
290 case CS42L42_SP_RX_FS:
291 case CS42l42_SPDIF_CH_SEL:
292 case CS42L42_SP_TX_ISOC_CTL:
293 case CS42L42_SP_TX_FS:
294 case CS42L42_SPDIF_SW_CTL1:
295 case CS42L42_SRC_SDIN_FS:
296 case CS42L42_SRC_SDOUT_FS:
297 case CS42L42_SOFT_RESET_REBOOT:
298 case CS42L42_SPDIF_CTL1:
299 case CS42L42_SPDIF_CTL2:
300 case CS42L42_SPDIF_CTL3:
301 case CS42L42_SPDIF_CTL4:
302 case CS42L42_ASP_TX_SZ_EN:
303 case CS42L42_ASP_TX_CH_EN:
304 case CS42L42_ASP_TX_CH_AP_RES:
305 case CS42L42_ASP_TX_CH1_BIT_MSB:
306 case CS42L42_ASP_TX_CH1_BIT_LSB:
307 case CS42L42_ASP_TX_HIZ_DLY_CFG:
308 case CS42L42_ASP_TX_CH2_BIT_MSB:
309 case CS42L42_ASP_TX_CH2_BIT_LSB:
310 case CS42L42_ASP_RX_DAI0_EN:
311 case CS42L42_ASP_RX_DAI0_CH1_AP_RES:
312 case CS42L42_ASP_RX_DAI0_CH1_BIT_MSB:
313 case CS42L42_ASP_RX_DAI0_CH1_BIT_LSB:
314 case CS42L42_ASP_RX_DAI0_CH2_AP_RES:
315 case CS42L42_ASP_RX_DAI0_CH2_BIT_MSB:
316 case CS42L42_ASP_RX_DAI0_CH2_BIT_LSB:
317 case CS42L42_ASP_RX_DAI0_CH3_AP_RES:
318 case CS42L42_ASP_RX_DAI0_CH3_BIT_MSB:
319 case CS42L42_ASP_RX_DAI0_CH3_BIT_LSB:
320 case CS42L42_ASP_RX_DAI0_CH4_AP_RES:
321 case CS42L42_ASP_RX_DAI0_CH4_BIT_MSB:
322 case CS42L42_ASP_RX_DAI0_CH4_BIT_LSB:
323 case CS42L42_ASP_RX_DAI1_CH1_AP_RES:
324 case CS42L42_ASP_RX_DAI1_CH1_BIT_MSB:
325 case CS42L42_ASP_RX_DAI1_CH1_BIT_LSB:
326 case CS42L42_ASP_RX_DAI1_CH2_AP_RES:
327 case CS42L42_ASP_RX_DAI1_CH2_BIT_MSB:
328 case CS42L42_ASP_RX_DAI1_CH2_BIT_LSB:
329 case CS42L42_SUB_REVID:
330 return true;
331 default:
332 return false;
333 }
334 }
335 EXPORT_SYMBOL_NS_GPL(cs42l42_readable_register, SND_SOC_CS42L42_CORE);
336
cs42l42_volatile_register(struct device * dev,unsigned int reg)337 bool cs42l42_volatile_register(struct device *dev, unsigned int reg)
338 {
339 switch (reg) {
340 case CS42L42_DEVID_AB:
341 case CS42L42_DEVID_CD:
342 case CS42L42_DEVID_E:
343 case CS42L42_MCLK_STATUS:
344 case CS42L42_OSC_SWITCH_STATUS:
345 case CS42L42_TRSENSE_STATUS:
346 case CS42L42_HS_DET_STATUS:
347 case CS42L42_ADC_OVFL_STATUS:
348 case CS42L42_MIXER_STATUS:
349 case CS42L42_SRC_STATUS:
350 case CS42L42_ASP_RX_STATUS:
351 case CS42L42_ASP_TX_STATUS:
352 case CS42L42_CODEC_STATUS:
353 case CS42L42_DET_INT_STATUS1:
354 case CS42L42_DET_INT_STATUS2:
355 case CS42L42_SRCPL_INT_STATUS:
356 case CS42L42_VPMON_STATUS:
357 case CS42L42_PLL_LOCK_STATUS:
358 case CS42L42_TSRS_PLUG_STATUS:
359 case CS42L42_LOAD_DET_RCSTAT:
360 case CS42L42_LOAD_DET_DONE:
361 case CS42L42_DET_STATUS1:
362 case CS42L42_DET_STATUS2:
363 case CS42L42_SOFT_RESET_REBOOT:
364 return true;
365 default:
366 return false;
367 }
368 }
369 EXPORT_SYMBOL_NS_GPL(cs42l42_volatile_register, SND_SOC_CS42L42_CORE);
370
371 const struct regmap_range_cfg cs42l42_page_range = {
372 .name = "Pages",
373 .range_min = 0,
374 .range_max = CS42L42_MAX_REGISTER,
375 .selector_reg = CS42L42_PAGE_REGISTER,
376 .selector_mask = 0xff,
377 .selector_shift = 0,
378 .window_start = 0,
379 .window_len = 256,
380 };
381 EXPORT_SYMBOL_NS_GPL(cs42l42_page_range, SND_SOC_CS42L42_CORE);
382
383 const struct regmap_config cs42l42_regmap = {
384 .reg_bits = 8,
385 .val_bits = 8,
386
387 .readable_reg = cs42l42_readable_register,
388 .volatile_reg = cs42l42_volatile_register,
389
390 .ranges = &cs42l42_page_range,
391 .num_ranges = 1,
392
393 .max_register = CS42L42_MAX_REGISTER,
394 .reg_defaults = cs42l42_reg_defaults,
395 .num_reg_defaults = ARRAY_SIZE(cs42l42_reg_defaults),
396 .cache_type = REGCACHE_RBTREE,
397
398 .use_single_read = true,
399 .use_single_write = true,
400 };
401 EXPORT_SYMBOL_NS_GPL(cs42l42_regmap, SND_SOC_CS42L42_CORE);
402
403 static DECLARE_TLV_DB_SCALE(adc_tlv, -9700, 100, true);
404 static DECLARE_TLV_DB_SCALE(mixer_tlv, -6300, 100, true);
405
cs42l42_slow_start_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)406 static int cs42l42_slow_start_put(struct snd_kcontrol *kcontrol,
407 struct snd_ctl_elem_value *ucontrol)
408 {
409 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
410 u8 val;
411
412 /* all bits of SLOW_START_EN must change together */
413 switch (ucontrol->value.integer.value[0]) {
414 case 0:
415 val = 0;
416 break;
417 case 1:
418 val = CS42L42_SLOW_START_EN_MASK;
419 break;
420 default:
421 return -EINVAL;
422 }
423
424 return snd_soc_component_update_bits(component, CS42L42_SLOW_START_ENABLE,
425 CS42L42_SLOW_START_EN_MASK, val);
426 }
427
428 static const char * const cs42l42_hpf_freq_text[] = {
429 "1.86Hz", "120Hz", "235Hz", "466Hz"
430 };
431
432 static SOC_ENUM_SINGLE_DECL(cs42l42_hpf_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
433 CS42L42_ADC_HPF_CF_SHIFT,
434 cs42l42_hpf_freq_text);
435
436 static const char * const cs42l42_wnf3_freq_text[] = {
437 "160Hz", "180Hz", "200Hz", "220Hz",
438 "240Hz", "260Hz", "280Hz", "300Hz"
439 };
440
441 static SOC_ENUM_SINGLE_DECL(cs42l42_wnf3_freq_enum, CS42L42_ADC_WNF_HPF_CTL,
442 CS42L42_ADC_WNF_CF_SHIFT,
443 cs42l42_wnf3_freq_text);
444
445 static const struct snd_kcontrol_new cs42l42_snd_controls[] = {
446 /* ADC Volume and Filter Controls */
447 SOC_SINGLE("ADC Notch Switch", CS42L42_ADC_CTL,
448 CS42L42_ADC_NOTCH_DIS_SHIFT, true, true),
449 SOC_SINGLE("ADC Weak Force Switch", CS42L42_ADC_CTL,
450 CS42L42_ADC_FORCE_WEAK_VCM_SHIFT, true, false),
451 SOC_SINGLE("ADC Invert Switch", CS42L42_ADC_CTL,
452 CS42L42_ADC_INV_SHIFT, true, false),
453 SOC_SINGLE("ADC Boost Switch", CS42L42_ADC_CTL,
454 CS42L42_ADC_DIG_BOOST_SHIFT, true, false),
455 SOC_SINGLE_S8_TLV("ADC Volume", CS42L42_ADC_VOLUME, -97, 12, adc_tlv),
456 SOC_SINGLE("ADC WNF Switch", CS42L42_ADC_WNF_HPF_CTL,
457 CS42L42_ADC_WNF_EN_SHIFT, true, false),
458 SOC_SINGLE("ADC HPF Switch", CS42L42_ADC_WNF_HPF_CTL,
459 CS42L42_ADC_HPF_EN_SHIFT, true, false),
460 SOC_ENUM("HPF Corner Freq", cs42l42_hpf_freq_enum),
461 SOC_ENUM("WNF 3dB Freq", cs42l42_wnf3_freq_enum),
462
463 /* DAC Volume and Filter Controls */
464 SOC_SINGLE("DACA Invert Switch", CS42L42_DAC_CTL1,
465 CS42L42_DACA_INV_SHIFT, true, false),
466 SOC_SINGLE("DACB Invert Switch", CS42L42_DAC_CTL1,
467 CS42L42_DACB_INV_SHIFT, true, false),
468 SOC_SINGLE("DAC HPF Switch", CS42L42_DAC_CTL2,
469 CS42L42_DAC_HPF_EN_SHIFT, true, false),
470 SOC_DOUBLE_R_TLV("Mixer Volume", CS42L42_MIXER_CHA_VOL,
471 CS42L42_MIXER_CHB_VOL, CS42L42_MIXER_CH_VOL_SHIFT,
472 0x3f, 1, mixer_tlv),
473
474 SOC_SINGLE_EXT("Slow Start Switch", CS42L42_SLOW_START_ENABLE,
475 CS42L42_SLOW_START_EN_SHIFT, true, false,
476 snd_soc_get_volsw, cs42l42_slow_start_put),
477 };
478
cs42l42_hp_adc_ev(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)479 static int cs42l42_hp_adc_ev(struct snd_soc_dapm_widget *w,
480 struct snd_kcontrol *kcontrol, int event)
481 {
482 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
483 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
484
485 switch (event) {
486 case SND_SOC_DAPM_PRE_PMU:
487 cs42l42->hp_adc_up_pending = true;
488 break;
489 case SND_SOC_DAPM_POST_PMU:
490 /* Only need one delay if HP and ADC are both powering-up */
491 if (cs42l42->hp_adc_up_pending) {
492 usleep_range(CS42L42_HP_ADC_EN_TIME_US,
493 CS42L42_HP_ADC_EN_TIME_US + 1000);
494 cs42l42->hp_adc_up_pending = false;
495 }
496 break;
497 default:
498 break;
499 }
500
501 return 0;
502 }
503
504 static const struct snd_soc_dapm_widget cs42l42_dapm_widgets[] = {
505 /* Playback Path */
506 SND_SOC_DAPM_OUTPUT("HP"),
507 SND_SOC_DAPM_DAC_E("DAC", NULL, CS42L42_PWR_CTL1, CS42L42_HP_PDN_SHIFT, 1,
508 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
509 SND_SOC_DAPM_MIXER("MIXER", CS42L42_PWR_CTL1, CS42L42_MIXER_PDN_SHIFT, 1, NULL, 0),
510 SND_SOC_DAPM_AIF_IN("SDIN1", NULL, 0, SND_SOC_NOPM, 0, 0),
511 SND_SOC_DAPM_AIF_IN("SDIN2", NULL, 1, SND_SOC_NOPM, 0, 0),
512
513 /* Playback Requirements */
514 SND_SOC_DAPM_SUPPLY("ASP DAI0", CS42L42_PWR_CTL1, CS42L42_ASP_DAI_PDN_SHIFT, 1, NULL, 0),
515
516 /* Capture Path */
517 SND_SOC_DAPM_INPUT("HS"),
518 SND_SOC_DAPM_ADC_E("ADC", NULL, CS42L42_PWR_CTL1, CS42L42_ADC_PDN_SHIFT, 1,
519 cs42l42_hp_adc_ev, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
520 SND_SOC_DAPM_AIF_OUT("SDOUT1", NULL, 0, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH1_SHIFT, 0),
521 SND_SOC_DAPM_AIF_OUT("SDOUT2", NULL, 1, CS42L42_ASP_TX_CH_EN, CS42L42_ASP_TX0_CH2_SHIFT, 0),
522
523 /* Capture Requirements */
524 SND_SOC_DAPM_SUPPLY("ASP DAO0", CS42L42_PWR_CTL1, CS42L42_ASP_DAO_PDN_SHIFT, 1, NULL, 0),
525 SND_SOC_DAPM_SUPPLY("ASP TX EN", CS42L42_ASP_TX_SZ_EN, CS42L42_ASP_TX_EN_SHIFT, 0, NULL, 0),
526
527 /* Playback/Capture Requirements */
528 SND_SOC_DAPM_SUPPLY("SCLK", CS42L42_ASP_CLK_CFG, CS42L42_ASP_SCLK_EN_SHIFT, 0, NULL, 0),
529
530 /* Soundwire SRC power control */
531 SND_SOC_DAPM_PGA("DACSRC", CS42L42_PWR_CTL2, CS42L42_DAC_SRC_PDNB_SHIFT, 0, NULL, 0),
532 SND_SOC_DAPM_PGA("ADCSRC", CS42L42_PWR_CTL2, CS42L42_ADC_SRC_PDNB_SHIFT, 0, NULL, 0),
533 };
534
535 static const struct snd_soc_dapm_route cs42l42_audio_map[] = {
536 /* Playback Path */
537 {"HP", NULL, "DAC"},
538 {"DAC", NULL, "MIXER"},
539 {"MIXER", NULL, "SDIN1"},
540 {"MIXER", NULL, "SDIN2"},
541 {"SDIN1", NULL, "Playback"},
542 {"SDIN2", NULL, "Playback"},
543
544 /* Playback Requirements */
545 {"SDIN1", NULL, "ASP DAI0"},
546 {"SDIN2", NULL, "ASP DAI0"},
547 {"SDIN1", NULL, "SCLK"},
548 {"SDIN2", NULL, "SCLK"},
549
550 /* Capture Path */
551 {"ADC", NULL, "HS"},
552 { "SDOUT1", NULL, "ADC" },
553 { "SDOUT2", NULL, "ADC" },
554 { "Capture", NULL, "SDOUT1" },
555 { "Capture", NULL, "SDOUT2" },
556
557 /* Capture Requirements */
558 { "SDOUT1", NULL, "ASP DAO0" },
559 { "SDOUT2", NULL, "ASP DAO0" },
560 { "SDOUT1", NULL, "SCLK" },
561 { "SDOUT2", NULL, "SCLK" },
562 { "SDOUT1", NULL, "ASP TX EN" },
563 { "SDOUT2", NULL, "ASP TX EN" },
564 };
565
cs42l42_set_jack(struct snd_soc_component * component,struct snd_soc_jack * jk,void * d)566 static int cs42l42_set_jack(struct snd_soc_component *component, struct snd_soc_jack *jk, void *d)
567 {
568 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
569
570 /* Prevent race with interrupt handler */
571 mutex_lock(&cs42l42->irq_lock);
572 cs42l42->jack = jk;
573
574 if (jk) {
575 switch (cs42l42->hs_type) {
576 case CS42L42_PLUG_CTIA:
577 case CS42L42_PLUG_OMTP:
578 snd_soc_jack_report(jk, SND_JACK_HEADSET, SND_JACK_HEADSET);
579 break;
580 case CS42L42_PLUG_HEADPHONE:
581 snd_soc_jack_report(jk, SND_JACK_HEADPHONE, SND_JACK_HEADPHONE);
582 break;
583 default:
584 break;
585 }
586 }
587 mutex_unlock(&cs42l42->irq_lock);
588
589 return 0;
590 }
591
592 const struct snd_soc_component_driver cs42l42_soc_component = {
593 .set_jack = cs42l42_set_jack,
594 .dapm_widgets = cs42l42_dapm_widgets,
595 .num_dapm_widgets = ARRAY_SIZE(cs42l42_dapm_widgets),
596 .dapm_routes = cs42l42_audio_map,
597 .num_dapm_routes = ARRAY_SIZE(cs42l42_audio_map),
598 .controls = cs42l42_snd_controls,
599 .num_controls = ARRAY_SIZE(cs42l42_snd_controls),
600 .endianness = 1,
601 };
602 EXPORT_SYMBOL_NS_GPL(cs42l42_soc_component, SND_SOC_CS42L42_CORE);
603
604 /* Switch to SCLK. Atomic delay after the write to allow the switch to complete. */
605 static const struct reg_sequence cs42l42_to_sclk_seq[] = {
606 {
607 .reg = CS42L42_OSC_SWITCH,
608 .def = CS42L42_SCLK_PRESENT_MASK,
609 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
610 },
611 };
612
613 /* Switch to OSC. Atomic delay after the write to allow the switch to complete. */
614 static const struct reg_sequence cs42l42_to_osc_seq[] = {
615 {
616 .reg = CS42L42_OSC_SWITCH,
617 .def = 0,
618 .delay_us = CS42L42_CLOCK_SWITCH_DELAY_US,
619 },
620 };
621
622 struct cs42l42_pll_params {
623 u32 sclk;
624 u8 mclk_src_sel;
625 u8 sclk_prediv;
626 u8 pll_div_int;
627 u32 pll_div_frac;
628 u8 pll_mode;
629 u8 pll_divout;
630 u32 mclk_int;
631 u8 pll_cal_ratio;
632 u8 n;
633 };
634
635 /*
636 * Common PLL Settings for given SCLK
637 * Table 4-5 from the Datasheet
638 */
639 static const struct cs42l42_pll_params pll_ratio_table[] = {
640 { 1411200, 1, 0x00, 0x80, 0x000000, 0x03, 0x10, 11289600, 128, 2},
641 { 1536000, 1, 0x00, 0x7D, 0x000000, 0x03, 0x10, 12000000, 125, 2},
642 { 2304000, 1, 0x00, 0x55, 0xC00000, 0x02, 0x10, 12288000, 85, 2},
643 { 2400000, 1, 0x00, 0x50, 0x000000, 0x03, 0x10, 12000000, 80, 2},
644 { 2822400, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
645 { 3000000, 1, 0x00, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
646 { 3072000, 1, 0x00, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
647 { 4000000, 1, 0x00, 0x30, 0x800000, 0x03, 0x10, 12000000, 96, 1},
648 { 4096000, 1, 0x00, 0x2E, 0xE00000, 0x03, 0x10, 12000000, 94, 1},
649 { 5644800, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
650 { 6000000, 1, 0x01, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
651 { 6144000, 1, 0x01, 0x3E, 0x800000, 0x03, 0x10, 12000000, 125, 1},
652 { 11289600, 0, 0, 0, 0, 0, 0, 11289600, 0, 1},
653 { 12000000, 0, 0, 0, 0, 0, 0, 12000000, 0, 1},
654 { 12288000, 0, 0, 0, 0, 0, 0, 12288000, 0, 1},
655 { 22579200, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 11289600, 128, 1},
656 { 24000000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12000000, 128, 1},
657 { 24576000, 1, 0x03, 0x40, 0x000000, 0x03, 0x10, 12288000, 128, 1}
658 };
659
cs42l42_pll_config(struct snd_soc_component * component,unsigned int clk,unsigned int sample_rate)660 int cs42l42_pll_config(struct snd_soc_component *component, unsigned int clk,
661 unsigned int sample_rate)
662 {
663 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
664 int i;
665
666 /* Don't reconfigure if there is an audio stream running */
667 if (cs42l42->stream_use) {
668 if (pll_ratio_table[cs42l42->pll_config].sclk == clk)
669 return 0;
670 else
671 return -EBUSY;
672 }
673
674 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
675 /* MCLKint must be a multiple of the sample rate */
676 if (pll_ratio_table[i].mclk_int % sample_rate)
677 continue;
678
679 if (pll_ratio_table[i].sclk == clk) {
680 cs42l42->pll_config = i;
681
682 /* Configure the internal sample rate */
683 snd_soc_component_update_bits(component, CS42L42_MCLK_CTL,
684 CS42L42_INTERNAL_FS_MASK,
685 ((pll_ratio_table[i].mclk_int !=
686 12000000) &&
687 (pll_ratio_table[i].mclk_int !=
688 24000000)) <<
689 CS42L42_INTERNAL_FS_SHIFT);
690 if (pll_ratio_table[i].mclk_src_sel == 0) {
691 /* Pass the clock straight through */
692 snd_soc_component_update_bits(component,
693 CS42L42_PLL_CTL1,
694 CS42L42_PLL_START_MASK, 0);
695 } else {
696 /* Configure PLL per table 4-5 */
697 snd_soc_component_update_bits(component,
698 CS42L42_PLL_DIV_CFG1,
699 CS42L42_SCLK_PREDIV_MASK,
700 pll_ratio_table[i].sclk_prediv
701 << CS42L42_SCLK_PREDIV_SHIFT);
702 snd_soc_component_update_bits(component,
703 CS42L42_PLL_DIV_INT,
704 CS42L42_PLL_DIV_INT_MASK,
705 pll_ratio_table[i].pll_div_int
706 << CS42L42_PLL_DIV_INT_SHIFT);
707 snd_soc_component_update_bits(component,
708 CS42L42_PLL_DIV_FRAC0,
709 CS42L42_PLL_DIV_FRAC_MASK,
710 CS42L42_FRAC0_VAL(
711 pll_ratio_table[i].pll_div_frac)
712 << CS42L42_PLL_DIV_FRAC_SHIFT);
713 snd_soc_component_update_bits(component,
714 CS42L42_PLL_DIV_FRAC1,
715 CS42L42_PLL_DIV_FRAC_MASK,
716 CS42L42_FRAC1_VAL(
717 pll_ratio_table[i].pll_div_frac)
718 << CS42L42_PLL_DIV_FRAC_SHIFT);
719 snd_soc_component_update_bits(component,
720 CS42L42_PLL_DIV_FRAC2,
721 CS42L42_PLL_DIV_FRAC_MASK,
722 CS42L42_FRAC2_VAL(
723 pll_ratio_table[i].pll_div_frac)
724 << CS42L42_PLL_DIV_FRAC_SHIFT);
725 snd_soc_component_update_bits(component,
726 CS42L42_PLL_CTL4,
727 CS42L42_PLL_MODE_MASK,
728 pll_ratio_table[i].pll_mode
729 << CS42L42_PLL_MODE_SHIFT);
730 snd_soc_component_update_bits(component,
731 CS42L42_PLL_CTL3,
732 CS42L42_PLL_DIVOUT_MASK,
733 (pll_ratio_table[i].pll_divout * pll_ratio_table[i].n)
734 << CS42L42_PLL_DIVOUT_SHIFT);
735 snd_soc_component_update_bits(component,
736 CS42L42_PLL_CAL_RATIO,
737 CS42L42_PLL_CAL_RATIO_MASK,
738 pll_ratio_table[i].pll_cal_ratio
739 << CS42L42_PLL_CAL_RATIO_SHIFT);
740 }
741 return 0;
742 }
743 }
744
745 return -EINVAL;
746 }
747 EXPORT_SYMBOL_NS_GPL(cs42l42_pll_config, SND_SOC_CS42L42_CORE);
748
cs42l42_src_config(struct snd_soc_component * component,unsigned int sample_rate)749 void cs42l42_src_config(struct snd_soc_component *component, unsigned int sample_rate)
750 {
751 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
752 unsigned int fs;
753
754 /* Don't reconfigure if there is an audio stream running */
755 if (cs42l42->stream_use)
756 return;
757
758 /* SRC MCLK must be as close as possible to 125 * sample rate */
759 if (sample_rate <= 48000)
760 fs = CS42L42_CLK_IASRC_SEL_6;
761 else
762 fs = CS42L42_CLK_IASRC_SEL_12;
763
764 /* Set the sample rates (96k or lower) */
765 snd_soc_component_update_bits(component,
766 CS42L42_FS_RATE_EN,
767 CS42L42_FS_EN_MASK,
768 (CS42L42_FS_EN_IASRC_96K |
769 CS42L42_FS_EN_OASRC_96K) <<
770 CS42L42_FS_EN_SHIFT);
771
772 snd_soc_component_update_bits(component,
773 CS42L42_IN_ASRC_CLK,
774 CS42L42_CLK_IASRC_SEL_MASK,
775 fs << CS42L42_CLK_IASRC_SEL_SHIFT);
776 snd_soc_component_update_bits(component,
777 CS42L42_OUT_ASRC_CLK,
778 CS42L42_CLK_OASRC_SEL_MASK,
779 fs << CS42L42_CLK_OASRC_SEL_SHIFT);
780 }
781 EXPORT_SYMBOL_NS_GPL(cs42l42_src_config, SND_SOC_CS42L42_CORE);
782
cs42l42_asp_config(struct snd_soc_component * component,unsigned int sclk,unsigned int sample_rate)783 static int cs42l42_asp_config(struct snd_soc_component *component,
784 unsigned int sclk, unsigned int sample_rate)
785 {
786 u32 fsync = sclk / sample_rate;
787
788 /* Set up the LRCLK */
789 if (((fsync * sample_rate) != sclk) || ((fsync % 2) != 0)) {
790 dev_err(component->dev,
791 "Unsupported sclk %d/sample rate %d\n",
792 sclk,
793 sample_rate);
794 return -EINVAL;
795 }
796 /* Set the LRCLK period */
797 snd_soc_component_update_bits(component,
798 CS42L42_FSYNC_P_LOWER,
799 CS42L42_FSYNC_PERIOD_MASK,
800 CS42L42_FRAC0_VAL(fsync - 1) <<
801 CS42L42_FSYNC_PERIOD_SHIFT);
802 snd_soc_component_update_bits(component,
803 CS42L42_FSYNC_P_UPPER,
804 CS42L42_FSYNC_PERIOD_MASK,
805 CS42L42_FRAC1_VAL(fsync - 1) <<
806 CS42L42_FSYNC_PERIOD_SHIFT);
807 /* Set the LRCLK to 50% duty cycle */
808 fsync = fsync / 2;
809 snd_soc_component_update_bits(component,
810 CS42L42_FSYNC_PW_LOWER,
811 CS42L42_FSYNC_PULSE_WIDTH_MASK,
812 CS42L42_FRAC0_VAL(fsync - 1) <<
813 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
814 snd_soc_component_update_bits(component,
815 CS42L42_FSYNC_PW_UPPER,
816 CS42L42_FSYNC_PULSE_WIDTH_MASK,
817 CS42L42_FRAC1_VAL(fsync - 1) <<
818 CS42L42_FSYNC_PULSE_WIDTH_SHIFT);
819
820 return 0;
821 }
822
cs42l42_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)823 static int cs42l42_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
824 {
825 struct snd_soc_component *component = codec_dai->component;
826 u32 asp_cfg_val = 0;
827
828 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
829 case SND_SOC_DAIFMT_CBS_CFM:
830 asp_cfg_val |= CS42L42_ASP_MASTER_MODE <<
831 CS42L42_ASP_MODE_SHIFT;
832 break;
833 case SND_SOC_DAIFMT_CBS_CFS:
834 asp_cfg_val |= CS42L42_ASP_SLAVE_MODE <<
835 CS42L42_ASP_MODE_SHIFT;
836 break;
837 default:
838 return -EINVAL;
839 }
840
841 /* interface format */
842 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
843 case SND_SOC_DAIFMT_I2S:
844 /*
845 * 5050 mode, frame starts on falling edge of LRCLK,
846 * frame delayed by 1.0 SCLKs
847 */
848 snd_soc_component_update_bits(component,
849 CS42L42_ASP_FRM_CFG,
850 CS42L42_ASP_STP_MASK |
851 CS42L42_ASP_5050_MASK |
852 CS42L42_ASP_FSD_MASK,
853 CS42L42_ASP_5050_MASK |
854 (CS42L42_ASP_FSD_1_0 <<
855 CS42L42_ASP_FSD_SHIFT));
856 break;
857 default:
858 return -EINVAL;
859 }
860
861 /* Bitclock/frame inversion */
862 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
863 case SND_SOC_DAIFMT_NB_NF:
864 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
865 break;
866 case SND_SOC_DAIFMT_NB_IF:
867 asp_cfg_val |= CS42L42_ASP_SCPOL_NOR << CS42L42_ASP_SCPOL_SHIFT;
868 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
869 break;
870 case SND_SOC_DAIFMT_IB_NF:
871 break;
872 case SND_SOC_DAIFMT_IB_IF:
873 asp_cfg_val |= CS42L42_ASP_LCPOL_INV << CS42L42_ASP_LCPOL_SHIFT;
874 break;
875 }
876
877 snd_soc_component_update_bits(component, CS42L42_ASP_CLK_CFG, CS42L42_ASP_MODE_MASK |
878 CS42L42_ASP_SCPOL_MASK |
879 CS42L42_ASP_LCPOL_MASK,
880 asp_cfg_val);
881
882 return 0;
883 }
884
cs42l42_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)885 static int cs42l42_dai_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
886 {
887 struct snd_soc_component *component = dai->component;
888 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
889
890 /*
891 * Sample rates < 44.1 kHz would produce an out-of-range SCLK with
892 * a standard I2S frame. If the machine driver sets SCLK it must be
893 * legal.
894 */
895 if (cs42l42->sclk)
896 return 0;
897
898 /* Machine driver has not set a SCLK, limit bottom end to 44.1 kHz */
899 return snd_pcm_hw_constraint_minmax(substream->runtime,
900 SNDRV_PCM_HW_PARAM_RATE,
901 44100, 96000);
902 }
903
cs42l42_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)904 static int cs42l42_pcm_hw_params(struct snd_pcm_substream *substream,
905 struct snd_pcm_hw_params *params,
906 struct snd_soc_dai *dai)
907 {
908 struct snd_soc_component *component = dai->component;
909 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
910 unsigned int channels = params_channels(params);
911 unsigned int width = (params_width(params) / 8) - 1;
912 unsigned int sample_rate = params_rate(params);
913 unsigned int slot_width = 0;
914 unsigned int val = 0;
915 unsigned int bclk;
916 int ret;
917
918 if (cs42l42->bclk_ratio) {
919 /* machine driver has set the BCLK/samp-rate ratio */
920 bclk = cs42l42->bclk_ratio * params_rate(params);
921 } else if (cs42l42->sclk) {
922 /* machine driver has set the SCLK */
923 bclk = cs42l42->sclk;
924 } else {
925 /*
926 * Assume 24-bit samples are in 32-bit slots, to prevent SCLK being
927 * more than assumed (which would result in overclocking).
928 */
929 if (params_width(params) == 24)
930 slot_width = 32;
931
932 /* I2S frame always has multiple of 2 channels */
933 bclk = snd_soc_tdm_params_to_bclk(params, slot_width, 0, 2);
934 }
935
936 switch (substream->stream) {
937 case SNDRV_PCM_STREAM_CAPTURE:
938 /* channel 2 on high LRCLK */
939 val = CS42L42_ASP_TX_CH2_AP_MASK |
940 (width << CS42L42_ASP_TX_CH2_RES_SHIFT) |
941 (width << CS42L42_ASP_TX_CH1_RES_SHIFT);
942
943 snd_soc_component_update_bits(component, CS42L42_ASP_TX_CH_AP_RES,
944 CS42L42_ASP_TX_CH1_AP_MASK | CS42L42_ASP_TX_CH2_AP_MASK |
945 CS42L42_ASP_TX_CH2_RES_MASK | CS42L42_ASP_TX_CH1_RES_MASK, val);
946 break;
947 case SNDRV_PCM_STREAM_PLAYBACK:
948 val |= width << CS42L42_ASP_RX_CH_RES_SHIFT;
949 /* channel 1 on low LRCLK */
950 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH1_AP_RES,
951 CS42L42_ASP_RX_CH_AP_MASK |
952 CS42L42_ASP_RX_CH_RES_MASK, val);
953 /* Channel 2 on high LRCLK */
954 val |= CS42L42_ASP_RX_CH_AP_HI << CS42L42_ASP_RX_CH_AP_SHIFT;
955 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_CH2_AP_RES,
956 CS42L42_ASP_RX_CH_AP_MASK |
957 CS42L42_ASP_RX_CH_RES_MASK, val);
958
959 /* Channel B comes from the last active channel */
960 snd_soc_component_update_bits(component, CS42L42_SP_RX_CH_SEL,
961 CS42L42_SP_RX_CHB_SEL_MASK,
962 (channels - 1) << CS42L42_SP_RX_CHB_SEL_SHIFT);
963
964 /* Both LRCLK slots must be enabled */
965 snd_soc_component_update_bits(component, CS42L42_ASP_RX_DAI0_EN,
966 CS42L42_ASP_RX0_CH_EN_MASK,
967 BIT(CS42L42_ASP_RX0_CH1_SHIFT) |
968 BIT(CS42L42_ASP_RX0_CH2_SHIFT));
969 break;
970 default:
971 break;
972 }
973
974 ret = cs42l42_pll_config(component, bclk, sample_rate);
975 if (ret)
976 return ret;
977
978 ret = cs42l42_asp_config(component, bclk, sample_rate);
979 if (ret)
980 return ret;
981
982 cs42l42_src_config(component, sample_rate);
983
984 return 0;
985 }
986
cs42l42_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)987 static int cs42l42_set_sysclk(struct snd_soc_dai *dai,
988 int clk_id, unsigned int freq, int dir)
989 {
990 struct snd_soc_component *component = dai->component;
991 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
992 int i;
993
994 if (freq == 0) {
995 cs42l42->sclk = 0;
996 return 0;
997 }
998
999 for (i = 0; i < ARRAY_SIZE(pll_ratio_table); i++) {
1000 if (pll_ratio_table[i].sclk == freq) {
1001 cs42l42->sclk = freq;
1002 return 0;
1003 }
1004 }
1005
1006 dev_err(component->dev, "SCLK %u not supported\n", freq);
1007
1008 return -EINVAL;
1009 }
1010
cs42l42_set_bclk_ratio(struct snd_soc_dai * dai,unsigned int bclk_ratio)1011 static int cs42l42_set_bclk_ratio(struct snd_soc_dai *dai,
1012 unsigned int bclk_ratio)
1013 {
1014 struct snd_soc_component *component = dai->component;
1015 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
1016
1017 cs42l42->bclk_ratio = bclk_ratio;
1018
1019 return 0;
1020 }
1021
cs42l42_mute_stream(struct snd_soc_dai * dai,int mute,int stream)1022 int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
1023 {
1024 struct snd_soc_component *component = dai->component;
1025 struct cs42l42_private *cs42l42 = snd_soc_component_get_drvdata(component);
1026 unsigned int regval;
1027 int ret;
1028
1029 if (mute) {
1030 /* Mute the headphone */
1031 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
1032 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1033 CS42L42_HP_ANA_AMUTE_MASK |
1034 CS42L42_HP_ANA_BMUTE_MASK,
1035 CS42L42_HP_ANA_AMUTE_MASK |
1036 CS42L42_HP_ANA_BMUTE_MASK);
1037
1038 cs42l42->stream_use &= ~(1 << stream);
1039 if (!cs42l42->stream_use) {
1040 /*
1041 * Switch to the internal oscillator.
1042 * SCLK must remain running until after this clock switch.
1043 * Without a source of clock the I2C bus doesn't work.
1044 */
1045 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_osc_seq,
1046 ARRAY_SIZE(cs42l42_to_osc_seq));
1047
1048 /* Must disconnect PLL before stopping it */
1049 snd_soc_component_update_bits(component,
1050 CS42L42_MCLK_SRC_SEL,
1051 CS42L42_MCLK_SRC_SEL_MASK,
1052 0);
1053 usleep_range(100, 200);
1054
1055 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1056 CS42L42_PLL_START_MASK, 0);
1057 }
1058 } else {
1059 if (!cs42l42->stream_use) {
1060 /* SCLK must be running before codec unmute.
1061 *
1062 * PLL must not be started with ADC and HP both off
1063 * otherwise the FILT+ supply will not charge properly.
1064 * DAPM widgets power-up before stream unmute so at least
1065 * one of the "DAC" or "ADC" widgets will already have
1066 * powered-up.
1067 */
1068 if (pll_ratio_table[cs42l42->pll_config].mclk_src_sel) {
1069 snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
1070 CS42L42_PLL_START_MASK, 1);
1071
1072 if (pll_ratio_table[cs42l42->pll_config].n > 1) {
1073 usleep_range(CS42L42_PLL_DIVOUT_TIME_US,
1074 CS42L42_PLL_DIVOUT_TIME_US * 2);
1075 regval = pll_ratio_table[cs42l42->pll_config].pll_divout;
1076 snd_soc_component_update_bits(component, CS42L42_PLL_CTL3,
1077 CS42L42_PLL_DIVOUT_MASK,
1078 regval <<
1079 CS42L42_PLL_DIVOUT_SHIFT);
1080 }
1081
1082 ret = regmap_read_poll_timeout(cs42l42->regmap,
1083 CS42L42_PLL_LOCK_STATUS,
1084 regval,
1085 (regval & 1),
1086 CS42L42_PLL_LOCK_POLL_US,
1087 CS42L42_PLL_LOCK_TIMEOUT_US);
1088 if (ret < 0)
1089 dev_warn(component->dev, "PLL failed to lock: %d\n", ret);
1090
1091 /* PLL must be running to drive glitchless switch logic */
1092 snd_soc_component_update_bits(component,
1093 CS42L42_MCLK_SRC_SEL,
1094 CS42L42_MCLK_SRC_SEL_MASK,
1095 CS42L42_MCLK_SRC_SEL_MASK);
1096 }
1097
1098 /* Mark SCLK as present, turn off internal oscillator */
1099 regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
1100 ARRAY_SIZE(cs42l42_to_sclk_seq));
1101 }
1102 cs42l42->stream_use |= 1 << stream;
1103
1104 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1105 /* Un-mute the headphone */
1106 snd_soc_component_update_bits(component, CS42L42_HP_CTL,
1107 CS42L42_HP_ANA_AMUTE_MASK |
1108 CS42L42_HP_ANA_BMUTE_MASK,
1109 0);
1110 }
1111 }
1112
1113 return 0;
1114 }
1115 EXPORT_SYMBOL_NS_GPL(cs42l42_mute_stream, SND_SOC_CS42L42_CORE);
1116
1117 #define CS42L42_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1118 SNDRV_PCM_FMTBIT_S24_LE |\
1119 SNDRV_PCM_FMTBIT_S32_LE)
1120
1121 static const struct snd_soc_dai_ops cs42l42_ops = {
1122 .startup = cs42l42_dai_startup,
1123 .hw_params = cs42l42_pcm_hw_params,
1124 .set_fmt = cs42l42_set_dai_fmt,
1125 .set_sysclk = cs42l42_set_sysclk,
1126 .set_bclk_ratio = cs42l42_set_bclk_ratio,
1127 .mute_stream = cs42l42_mute_stream,
1128 };
1129
1130 struct snd_soc_dai_driver cs42l42_dai = {
1131 .name = "cs42l42",
1132 .playback = {
1133 .stream_name = "Playback",
1134 .channels_min = 1,
1135 .channels_max = 2,
1136 .rates = SNDRV_PCM_RATE_8000_96000,
1137 .formats = CS42L42_FORMATS,
1138 },
1139 .capture = {
1140 .stream_name = "Capture",
1141 .channels_min = 1,
1142 .channels_max = 2,
1143 .rates = SNDRV_PCM_RATE_8000_96000,
1144 .formats = CS42L42_FORMATS,
1145 },
1146 .symmetric_rate = 1,
1147 .symmetric_sample_bits = 1,
1148 .ops = &cs42l42_ops,
1149 };
1150 EXPORT_SYMBOL_NS_GPL(cs42l42_dai, SND_SOC_CS42L42_CORE);
1151
cs42l42_manual_hs_type_detect(struct cs42l42_private * cs42l42)1152 static void cs42l42_manual_hs_type_detect(struct cs42l42_private *cs42l42)
1153 {
1154 unsigned int hs_det_status;
1155 unsigned int hs_det_comp1;
1156 unsigned int hs_det_comp2;
1157 unsigned int hs_det_sw;
1158
1159 /* Set hs detect to manual, active mode */
1160 regmap_update_bits(cs42l42->regmap,
1161 CS42L42_HSDET_CTL2,
1162 CS42L42_HSDET_CTRL_MASK |
1163 CS42L42_HSDET_SET_MASK |
1164 CS42L42_HSBIAS_REF_MASK |
1165 CS42L42_HSDET_AUTO_TIME_MASK,
1166 (1 << CS42L42_HSDET_CTRL_SHIFT) |
1167 (0 << CS42L42_HSDET_SET_SHIFT) |
1168 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1169 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1170
1171 /* Configure HS DET comparator reference levels. */
1172 regmap_update_bits(cs42l42->regmap,
1173 CS42L42_HSDET_CTL1,
1174 CS42L42_HSDET_COMP1_LVL_MASK |
1175 CS42L42_HSDET_COMP2_LVL_MASK,
1176 (CS42L42_HSDET_COMP1_LVL_VAL << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1177 (CS42L42_HSDET_COMP2_LVL_VAL << CS42L42_HSDET_COMP2_LVL_SHIFT));
1178
1179 /* Open the SW_HSB_HS3 switch and close SW_HSB_HS4 for a Type 1 headset. */
1180 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP1);
1181
1182 msleep(100);
1183
1184 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1185
1186 hs_det_comp1 = (hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1187 CS42L42_HSDET_COMP1_OUT_SHIFT;
1188 hs_det_comp2 = (hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1189 CS42L42_HSDET_COMP2_OUT_SHIFT;
1190
1191 /* Close the SW_HSB_HS3 switch for a Type 2 headset. */
1192 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, CS42L42_HSDET_SW_COMP2);
1193
1194 msleep(100);
1195
1196 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1197
1198 hs_det_comp1 |= ((hs_det_status & CS42L42_HSDET_COMP1_OUT_MASK) >>
1199 CS42L42_HSDET_COMP1_OUT_SHIFT) << 1;
1200 hs_det_comp2 |= ((hs_det_status & CS42L42_HSDET_COMP2_OUT_MASK) >>
1201 CS42L42_HSDET_COMP2_OUT_SHIFT) << 1;
1202
1203 /* Use Comparator 1 with 1.25V Threshold. */
1204 switch (hs_det_comp1) {
1205 case CS42L42_HSDET_COMP_TYPE1:
1206 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1207 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1208 break;
1209 case CS42L42_HSDET_COMP_TYPE2:
1210 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1211 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1212 break;
1213 default:
1214 /* Fallback to Comparator 2 with 1.75V Threshold. */
1215 switch (hs_det_comp2) {
1216 case CS42L42_HSDET_COMP_TYPE1:
1217 cs42l42->hs_type = CS42L42_PLUG_CTIA;
1218 hs_det_sw = CS42L42_HSDET_SW_TYPE1;
1219 break;
1220 case CS42L42_HSDET_COMP_TYPE2:
1221 cs42l42->hs_type = CS42L42_PLUG_OMTP;
1222 hs_det_sw = CS42L42_HSDET_SW_TYPE2;
1223 break;
1224 /* Detect Type 3 and Type 4 Headsets as Headphones */
1225 default:
1226 cs42l42->hs_type = CS42L42_PLUG_HEADPHONE;
1227 hs_det_sw = CS42L42_HSDET_SW_TYPE3;
1228 break;
1229 }
1230 }
1231
1232 /* Set Switches */
1233 regmap_write(cs42l42->regmap, CS42L42_HS_SWITCH_CTL, hs_det_sw);
1234
1235 /* Set HSDET mode to Manual—Disabled */
1236 regmap_update_bits(cs42l42->regmap,
1237 CS42L42_HSDET_CTL2,
1238 CS42L42_HSDET_CTRL_MASK |
1239 CS42L42_HSDET_SET_MASK |
1240 CS42L42_HSBIAS_REF_MASK |
1241 CS42L42_HSDET_AUTO_TIME_MASK,
1242 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1243 (0 << CS42L42_HSDET_SET_SHIFT) |
1244 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1245 (0 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1246
1247 /* Configure HS DET comparator reference levels. */
1248 regmap_update_bits(cs42l42->regmap,
1249 CS42L42_HSDET_CTL1,
1250 CS42L42_HSDET_COMP1_LVL_MASK |
1251 CS42L42_HSDET_COMP2_LVL_MASK,
1252 (CS42L42_HSDET_COMP1_LVL_DEFAULT << CS42L42_HSDET_COMP1_LVL_SHIFT) |
1253 (CS42L42_HSDET_COMP2_LVL_DEFAULT << CS42L42_HSDET_COMP2_LVL_SHIFT));
1254 }
1255
cs42l42_process_hs_type_detect(struct cs42l42_private * cs42l42)1256 static void cs42l42_process_hs_type_detect(struct cs42l42_private *cs42l42)
1257 {
1258 unsigned int hs_det_status;
1259 unsigned int int_status;
1260
1261 /* Read and save the hs detection result */
1262 regmap_read(cs42l42->regmap, CS42L42_HS_DET_STATUS, &hs_det_status);
1263
1264 /* Mask the auto detect interrupt */
1265 regmap_update_bits(cs42l42->regmap,
1266 CS42L42_CODEC_INT_MASK,
1267 CS42L42_PDN_DONE_MASK |
1268 CS42L42_HSDET_AUTO_DONE_MASK,
1269 (1 << CS42L42_PDN_DONE_SHIFT) |
1270 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1271
1272
1273 cs42l42->hs_type = (hs_det_status & CS42L42_HSDET_TYPE_MASK) >>
1274 CS42L42_HSDET_TYPE_SHIFT;
1275
1276 /* Set hs detect to automatic, disabled mode */
1277 regmap_update_bits(cs42l42->regmap,
1278 CS42L42_HSDET_CTL2,
1279 CS42L42_HSDET_CTRL_MASK |
1280 CS42L42_HSDET_SET_MASK |
1281 CS42L42_HSBIAS_REF_MASK |
1282 CS42L42_HSDET_AUTO_TIME_MASK,
1283 (2 << CS42L42_HSDET_CTRL_SHIFT) |
1284 (2 << CS42L42_HSDET_SET_SHIFT) |
1285 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1286 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1287
1288 /* Run Manual detection if auto detect has not found a headset.
1289 * We Re-Run with Manual Detection if the original detection was invalid or headphones,
1290 * to ensure that a headset mic is detected in all cases.
1291 */
1292 if (cs42l42->hs_type == CS42L42_PLUG_INVALID ||
1293 cs42l42->hs_type == CS42L42_PLUG_HEADPHONE) {
1294 dev_dbg(cs42l42->dev, "Running Manual Detection Fallback\n");
1295 cs42l42_manual_hs_type_detect(cs42l42);
1296 }
1297
1298 /* Set up button detection */
1299 if ((cs42l42->hs_type == CS42L42_PLUG_CTIA) ||
1300 (cs42l42->hs_type == CS42L42_PLUG_OMTP)) {
1301 /* Set auto HS bias settings to default */
1302 regmap_update_bits(cs42l42->regmap,
1303 CS42L42_HSBIAS_SC_AUTOCTL,
1304 CS42L42_HSBIAS_SENSE_EN_MASK |
1305 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1306 CS42L42_TIP_SENSE_EN_MASK |
1307 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1308 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1309 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1310 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1311 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1312
1313 /* Set up hs detect level sensitivity */
1314 regmap_update_bits(cs42l42->regmap,
1315 CS42L42_MIC_DET_CTL1,
1316 CS42L42_LATCH_TO_VP_MASK |
1317 CS42L42_EVENT_STAT_SEL_MASK |
1318 CS42L42_HS_DET_LEVEL_MASK,
1319 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1320 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1321 (cs42l42->bias_thresholds[0] <<
1322 CS42L42_HS_DET_LEVEL_SHIFT));
1323
1324 /* Set auto HS bias settings to default */
1325 regmap_update_bits(cs42l42->regmap,
1326 CS42L42_HSBIAS_SC_AUTOCTL,
1327 CS42L42_HSBIAS_SENSE_EN_MASK |
1328 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1329 CS42L42_TIP_SENSE_EN_MASK |
1330 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1331 (cs42l42->hs_bias_sense_en << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1332 (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1333 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1334 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1335
1336 /* Turn on level detect circuitry */
1337 regmap_update_bits(cs42l42->regmap,
1338 CS42L42_MISC_DET_CTL,
1339 CS42L42_HSBIAS_CTL_MASK |
1340 CS42L42_PDN_MIC_LVL_DET_MASK,
1341 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1342 (0 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1343
1344 msleep(cs42l42->btn_det_init_dbnce);
1345
1346 /* Clear any button interrupts before unmasking them */
1347 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1348 &int_status);
1349
1350 /* Unmask button detect interrupts */
1351 regmap_update_bits(cs42l42->regmap,
1352 CS42L42_DET_INT2_MASK,
1353 CS42L42_M_DETECT_TF_MASK |
1354 CS42L42_M_DETECT_FT_MASK |
1355 CS42L42_M_HSBIAS_HIZ_MASK |
1356 CS42L42_M_SHORT_RLS_MASK |
1357 CS42L42_M_SHORT_DET_MASK,
1358 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1359 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1360 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1361 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1362 (1 << CS42L42_M_SHORT_DET_SHIFT));
1363 } else {
1364 /* Make sure button detect and HS bias circuits are off */
1365 regmap_update_bits(cs42l42->regmap,
1366 CS42L42_MISC_DET_CTL,
1367 CS42L42_HSBIAS_CTL_MASK |
1368 CS42L42_PDN_MIC_LVL_DET_MASK,
1369 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1370 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1371 }
1372
1373 regmap_update_bits(cs42l42->regmap,
1374 CS42L42_DAC_CTL2,
1375 CS42L42_HPOUT_PULLDOWN_MASK |
1376 CS42L42_HPOUT_LOAD_MASK |
1377 CS42L42_HPOUT_CLAMP_MASK |
1378 CS42L42_DAC_HPF_EN_MASK |
1379 CS42L42_DAC_MON_EN_MASK,
1380 (0 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1381 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1382 (0 << CS42L42_HPOUT_CLAMP_SHIFT) |
1383 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1384 (0 << CS42L42_DAC_MON_EN_SHIFT));
1385
1386 /* Unmask tip sense interrupts */
1387 regmap_update_bits(cs42l42->regmap,
1388 CS42L42_TSRS_PLUG_INT_MASK,
1389 CS42L42_TS_PLUG_MASK |
1390 CS42L42_TS_UNPLUG_MASK,
1391 (0 << CS42L42_TS_PLUG_SHIFT) |
1392 (0 << CS42L42_TS_UNPLUG_SHIFT));
1393 }
1394
cs42l42_init_hs_type_detect(struct cs42l42_private * cs42l42)1395 static void cs42l42_init_hs_type_detect(struct cs42l42_private *cs42l42)
1396 {
1397 /* Mask tip sense interrupts */
1398 regmap_update_bits(cs42l42->regmap,
1399 CS42L42_TSRS_PLUG_INT_MASK,
1400 CS42L42_TS_PLUG_MASK |
1401 CS42L42_TS_UNPLUG_MASK,
1402 (1 << CS42L42_TS_PLUG_SHIFT) |
1403 (1 << CS42L42_TS_UNPLUG_SHIFT));
1404
1405 /* Make sure button detect and HS bias circuits are off */
1406 regmap_update_bits(cs42l42->regmap,
1407 CS42L42_MISC_DET_CTL,
1408 CS42L42_HSBIAS_CTL_MASK |
1409 CS42L42_PDN_MIC_LVL_DET_MASK,
1410 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1411 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1412
1413 /* Set auto HS bias settings to default */
1414 regmap_update_bits(cs42l42->regmap,
1415 CS42L42_HSBIAS_SC_AUTOCTL,
1416 CS42L42_HSBIAS_SENSE_EN_MASK |
1417 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1418 CS42L42_TIP_SENSE_EN_MASK |
1419 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1420 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1421 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1422 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1423 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1424
1425 /* Set hs detect to manual, disabled mode */
1426 regmap_update_bits(cs42l42->regmap,
1427 CS42L42_HSDET_CTL2,
1428 CS42L42_HSDET_CTRL_MASK |
1429 CS42L42_HSDET_SET_MASK |
1430 CS42L42_HSBIAS_REF_MASK |
1431 CS42L42_HSDET_AUTO_TIME_MASK,
1432 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1433 (2 << CS42L42_HSDET_SET_SHIFT) |
1434 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1435 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1436
1437 regmap_update_bits(cs42l42->regmap,
1438 CS42L42_DAC_CTL2,
1439 CS42L42_HPOUT_PULLDOWN_MASK |
1440 CS42L42_HPOUT_LOAD_MASK |
1441 CS42L42_HPOUT_CLAMP_MASK |
1442 CS42L42_DAC_HPF_EN_MASK |
1443 CS42L42_DAC_MON_EN_MASK,
1444 (8 << CS42L42_HPOUT_PULLDOWN_SHIFT) |
1445 (0 << CS42L42_HPOUT_LOAD_SHIFT) |
1446 (1 << CS42L42_HPOUT_CLAMP_SHIFT) |
1447 (1 << CS42L42_DAC_HPF_EN_SHIFT) |
1448 (1 << CS42L42_DAC_MON_EN_SHIFT));
1449
1450 /* Power up HS bias to 2.7V */
1451 regmap_update_bits(cs42l42->regmap,
1452 CS42L42_MISC_DET_CTL,
1453 CS42L42_HSBIAS_CTL_MASK |
1454 CS42L42_PDN_MIC_LVL_DET_MASK,
1455 (3 << CS42L42_HSBIAS_CTL_SHIFT) |
1456 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1457
1458 /* Wait for HS bias to ramp up */
1459 msleep(cs42l42->hs_bias_ramp_time);
1460
1461 /* Unmask auto detect interrupt */
1462 regmap_update_bits(cs42l42->regmap,
1463 CS42L42_CODEC_INT_MASK,
1464 CS42L42_PDN_DONE_MASK |
1465 CS42L42_HSDET_AUTO_DONE_MASK,
1466 (1 << CS42L42_PDN_DONE_SHIFT) |
1467 (0 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1468
1469 /* Set hs detect to automatic, enabled mode */
1470 regmap_update_bits(cs42l42->regmap,
1471 CS42L42_HSDET_CTL2,
1472 CS42L42_HSDET_CTRL_MASK |
1473 CS42L42_HSDET_SET_MASK |
1474 CS42L42_HSBIAS_REF_MASK |
1475 CS42L42_HSDET_AUTO_TIME_MASK,
1476 (3 << CS42L42_HSDET_CTRL_SHIFT) |
1477 (2 << CS42L42_HSDET_SET_SHIFT) |
1478 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1479 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1480 }
1481
cs42l42_cancel_hs_type_detect(struct cs42l42_private * cs42l42)1482 static void cs42l42_cancel_hs_type_detect(struct cs42l42_private *cs42l42)
1483 {
1484 /* Mask button detect interrupts */
1485 regmap_update_bits(cs42l42->regmap,
1486 CS42L42_DET_INT2_MASK,
1487 CS42L42_M_DETECT_TF_MASK |
1488 CS42L42_M_DETECT_FT_MASK |
1489 CS42L42_M_HSBIAS_HIZ_MASK |
1490 CS42L42_M_SHORT_RLS_MASK |
1491 CS42L42_M_SHORT_DET_MASK,
1492 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1493 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1494 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1495 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1496 (1 << CS42L42_M_SHORT_DET_SHIFT));
1497
1498 /* Ground HS bias */
1499 regmap_update_bits(cs42l42->regmap,
1500 CS42L42_MISC_DET_CTL,
1501 CS42L42_HSBIAS_CTL_MASK |
1502 CS42L42_PDN_MIC_LVL_DET_MASK,
1503 (1 << CS42L42_HSBIAS_CTL_SHIFT) |
1504 (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT));
1505
1506 /* Set auto HS bias settings to default */
1507 regmap_update_bits(cs42l42->regmap,
1508 CS42L42_HSBIAS_SC_AUTOCTL,
1509 CS42L42_HSBIAS_SENSE_EN_MASK |
1510 CS42L42_AUTO_HSBIAS_HIZ_MASK |
1511 CS42L42_TIP_SENSE_EN_MASK |
1512 CS42L42_HSBIAS_SENSE_TRIP_MASK,
1513 (0 << CS42L42_HSBIAS_SENSE_EN_SHIFT) |
1514 (0 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) |
1515 (0 << CS42L42_TIP_SENSE_EN_SHIFT) |
1516 (3 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT));
1517
1518 /* Set hs detect to manual, disabled mode */
1519 regmap_update_bits(cs42l42->regmap,
1520 CS42L42_HSDET_CTL2,
1521 CS42L42_HSDET_CTRL_MASK |
1522 CS42L42_HSDET_SET_MASK |
1523 CS42L42_HSBIAS_REF_MASK |
1524 CS42L42_HSDET_AUTO_TIME_MASK,
1525 (0 << CS42L42_HSDET_CTRL_SHIFT) |
1526 (2 << CS42L42_HSDET_SET_SHIFT) |
1527 (0 << CS42L42_HSBIAS_REF_SHIFT) |
1528 (3 << CS42L42_HSDET_AUTO_TIME_SHIFT));
1529 }
1530
cs42l42_handle_button_press(struct cs42l42_private * cs42l42)1531 static int cs42l42_handle_button_press(struct cs42l42_private *cs42l42)
1532 {
1533 int bias_level;
1534 unsigned int detect_status;
1535
1536 /* Mask button detect interrupts */
1537 regmap_update_bits(cs42l42->regmap,
1538 CS42L42_DET_INT2_MASK,
1539 CS42L42_M_DETECT_TF_MASK |
1540 CS42L42_M_DETECT_FT_MASK |
1541 CS42L42_M_HSBIAS_HIZ_MASK |
1542 CS42L42_M_SHORT_RLS_MASK |
1543 CS42L42_M_SHORT_DET_MASK,
1544 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1545 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1546 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1547 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1548 (1 << CS42L42_M_SHORT_DET_SHIFT));
1549
1550 usleep_range(cs42l42->btn_det_event_dbnce * 1000,
1551 cs42l42->btn_det_event_dbnce * 2000);
1552
1553 /* Test all 4 level detect biases */
1554 bias_level = 1;
1555 do {
1556 /* Adjust button detect level sensitivity */
1557 regmap_update_bits(cs42l42->regmap,
1558 CS42L42_MIC_DET_CTL1,
1559 CS42L42_LATCH_TO_VP_MASK |
1560 CS42L42_EVENT_STAT_SEL_MASK |
1561 CS42L42_HS_DET_LEVEL_MASK,
1562 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1563 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1564 (cs42l42->bias_thresholds[bias_level] <<
1565 CS42L42_HS_DET_LEVEL_SHIFT));
1566
1567 regmap_read(cs42l42->regmap, CS42L42_DET_STATUS2,
1568 &detect_status);
1569 } while ((detect_status & CS42L42_HS_TRUE_MASK) &&
1570 (++bias_level < CS42L42_NUM_BIASES));
1571
1572 switch (bias_level) {
1573 case 1: /* Function C button press */
1574 bias_level = SND_JACK_BTN_2;
1575 dev_dbg(cs42l42->dev, "Function C button press\n");
1576 break;
1577 case 2: /* Function B button press */
1578 bias_level = SND_JACK_BTN_1;
1579 dev_dbg(cs42l42->dev, "Function B button press\n");
1580 break;
1581 case 3: /* Function D button press */
1582 bias_level = SND_JACK_BTN_3;
1583 dev_dbg(cs42l42->dev, "Function D button press\n");
1584 break;
1585 case 4: /* Function A button press */
1586 bias_level = SND_JACK_BTN_0;
1587 dev_dbg(cs42l42->dev, "Function A button press\n");
1588 break;
1589 default:
1590 bias_level = 0;
1591 break;
1592 }
1593
1594 /* Set button detect level sensitivity back to default */
1595 regmap_update_bits(cs42l42->regmap,
1596 CS42L42_MIC_DET_CTL1,
1597 CS42L42_LATCH_TO_VP_MASK |
1598 CS42L42_EVENT_STAT_SEL_MASK |
1599 CS42L42_HS_DET_LEVEL_MASK,
1600 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1601 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1602 (cs42l42->bias_thresholds[0] << CS42L42_HS_DET_LEVEL_SHIFT));
1603
1604 /* Clear any button interrupts before unmasking them */
1605 regmap_read(cs42l42->regmap, CS42L42_DET_INT_STATUS2,
1606 &detect_status);
1607
1608 /* Unmask button detect interrupts */
1609 regmap_update_bits(cs42l42->regmap,
1610 CS42L42_DET_INT2_MASK,
1611 CS42L42_M_DETECT_TF_MASK |
1612 CS42L42_M_DETECT_FT_MASK |
1613 CS42L42_M_HSBIAS_HIZ_MASK |
1614 CS42L42_M_SHORT_RLS_MASK |
1615 CS42L42_M_SHORT_DET_MASK,
1616 (0 << CS42L42_M_DETECT_TF_SHIFT) |
1617 (0 << CS42L42_M_DETECT_FT_SHIFT) |
1618 (0 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1619 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1620 (1 << CS42L42_M_SHORT_DET_SHIFT));
1621
1622 return bias_level;
1623 }
1624
1625 struct cs42l42_irq_params {
1626 u16 status_addr;
1627 u16 mask_addr;
1628 u8 mask;
1629 };
1630
1631 static const struct cs42l42_irq_params irq_params_table[] = {
1632 {CS42L42_ADC_OVFL_STATUS, CS42L42_ADC_OVFL_INT_MASK,
1633 CS42L42_ADC_OVFL_VAL_MASK},
1634 {CS42L42_MIXER_STATUS, CS42L42_MIXER_INT_MASK,
1635 CS42L42_MIXER_VAL_MASK},
1636 {CS42L42_SRC_STATUS, CS42L42_SRC_INT_MASK,
1637 CS42L42_SRC_VAL_MASK},
1638 {CS42L42_ASP_RX_STATUS, CS42L42_ASP_RX_INT_MASK,
1639 CS42L42_ASP_RX_VAL_MASK},
1640 {CS42L42_ASP_TX_STATUS, CS42L42_ASP_TX_INT_MASK,
1641 CS42L42_ASP_TX_VAL_MASK},
1642 {CS42L42_CODEC_STATUS, CS42L42_CODEC_INT_MASK,
1643 CS42L42_CODEC_VAL_MASK},
1644 {CS42L42_DET_INT_STATUS1, CS42L42_DET_INT1_MASK,
1645 CS42L42_DET_INT_VAL1_MASK},
1646 {CS42L42_DET_INT_STATUS2, CS42L42_DET_INT2_MASK,
1647 CS42L42_DET_INT_VAL2_MASK},
1648 {CS42L42_SRCPL_INT_STATUS, CS42L42_SRCPL_INT_MASK,
1649 CS42L42_SRCPL_VAL_MASK},
1650 {CS42L42_VPMON_STATUS, CS42L42_VPMON_INT_MASK,
1651 CS42L42_VPMON_VAL_MASK},
1652 {CS42L42_PLL_LOCK_STATUS, CS42L42_PLL_LOCK_INT_MASK,
1653 CS42L42_PLL_LOCK_VAL_MASK},
1654 {CS42L42_TSRS_PLUG_STATUS, CS42L42_TSRS_PLUG_INT_MASK,
1655 CS42L42_TSRS_PLUG_VAL_MASK}
1656 };
1657
cs42l42_irq_thread(int irq,void * data)1658 irqreturn_t cs42l42_irq_thread(int irq, void *data)
1659 {
1660 struct cs42l42_private *cs42l42 = (struct cs42l42_private *)data;
1661 unsigned int stickies[12];
1662 unsigned int masks[12];
1663 unsigned int current_plug_status;
1664 unsigned int current_button_status;
1665 unsigned int i;
1666
1667 pm_runtime_get_sync(cs42l42->dev);
1668 mutex_lock(&cs42l42->irq_lock);
1669 if (cs42l42->suspended || !cs42l42->init_done) {
1670 mutex_unlock(&cs42l42->irq_lock);
1671 pm_runtime_put_autosuspend(cs42l42->dev);
1672 return IRQ_NONE;
1673 }
1674
1675 /* Read sticky registers to clear interurpt */
1676 for (i = 0; i < ARRAY_SIZE(stickies); i++) {
1677 regmap_read(cs42l42->regmap, irq_params_table[i].status_addr,
1678 &(stickies[i]));
1679 regmap_read(cs42l42->regmap, irq_params_table[i].mask_addr,
1680 &(masks[i]));
1681 stickies[i] = stickies[i] & (~masks[i]) &
1682 irq_params_table[i].mask;
1683 }
1684
1685 /* Read tip sense status before handling type detect */
1686 current_plug_status = (stickies[11] &
1687 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1688 CS42L42_TS_PLUG_SHIFT;
1689
1690 /* Read button sense status */
1691 current_button_status = stickies[7] &
1692 (CS42L42_M_DETECT_TF_MASK |
1693 CS42L42_M_DETECT_FT_MASK |
1694 CS42L42_M_HSBIAS_HIZ_MASK);
1695
1696 /*
1697 * Check auto-detect status. Don't assume a previous unplug event has
1698 * cleared the flags. If the jack is unplugged and plugged during
1699 * system suspend there won't have been an unplug event.
1700 */
1701 if ((~masks[5]) & irq_params_table[5].mask) {
1702 if (stickies[5] & CS42L42_HSDET_AUTO_DONE_MASK) {
1703 cs42l42_process_hs_type_detect(cs42l42);
1704 switch (cs42l42->hs_type) {
1705 case CS42L42_PLUG_CTIA:
1706 case CS42L42_PLUG_OMTP:
1707 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADSET,
1708 SND_JACK_HEADSET |
1709 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1710 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1711 break;
1712 case CS42L42_PLUG_HEADPHONE:
1713 snd_soc_jack_report(cs42l42->jack, SND_JACK_HEADPHONE,
1714 SND_JACK_HEADSET |
1715 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1716 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1717 break;
1718 default:
1719 break;
1720 }
1721 dev_dbg(cs42l42->dev, "Auto detect done (%d)\n", cs42l42->hs_type);
1722 }
1723 }
1724
1725 /* Check tip sense status */
1726 if ((~masks[11]) & irq_params_table[11].mask) {
1727 switch (current_plug_status) {
1728 case CS42L42_TS_PLUG:
1729 if (cs42l42->plug_state != CS42L42_TS_PLUG) {
1730 cs42l42->plug_state = CS42L42_TS_PLUG;
1731 cs42l42_init_hs_type_detect(cs42l42);
1732 }
1733 break;
1734
1735 case CS42L42_TS_UNPLUG:
1736 if (cs42l42->plug_state != CS42L42_TS_UNPLUG) {
1737 cs42l42->plug_state = CS42L42_TS_UNPLUG;
1738 cs42l42_cancel_hs_type_detect(cs42l42);
1739
1740 snd_soc_jack_report(cs42l42->jack, 0,
1741 SND_JACK_HEADSET |
1742 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1743 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1744
1745 dev_dbg(cs42l42->dev, "Unplug event\n");
1746 }
1747 break;
1748
1749 default:
1750 cs42l42->plug_state = CS42L42_TS_TRANS;
1751 }
1752 }
1753
1754 /* Check button detect status */
1755 if (cs42l42->plug_state == CS42L42_TS_PLUG && ((~masks[7]) & irq_params_table[7].mask)) {
1756 if (!(current_button_status &
1757 CS42L42_M_HSBIAS_HIZ_MASK)) {
1758
1759 if (current_button_status & CS42L42_M_DETECT_TF_MASK) {
1760 dev_dbg(cs42l42->dev, "Button released\n");
1761 snd_soc_jack_report(cs42l42->jack, 0,
1762 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1763 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1764 } else if (current_button_status & CS42L42_M_DETECT_FT_MASK) {
1765 snd_soc_jack_report(cs42l42->jack,
1766 cs42l42_handle_button_press(cs42l42),
1767 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1768 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1769 }
1770 }
1771 }
1772
1773 mutex_unlock(&cs42l42->irq_lock);
1774 pm_runtime_mark_last_busy(cs42l42->dev);
1775 pm_runtime_put_autosuspend(cs42l42->dev);
1776
1777 return IRQ_HANDLED;
1778 }
1779 EXPORT_SYMBOL_NS_GPL(cs42l42_irq_thread, SND_SOC_CS42L42_CORE);
1780
cs42l42_set_interrupt_masks(struct cs42l42_private * cs42l42)1781 static void cs42l42_set_interrupt_masks(struct cs42l42_private *cs42l42)
1782 {
1783 regmap_update_bits(cs42l42->regmap, CS42L42_ADC_OVFL_INT_MASK,
1784 CS42L42_ADC_OVFL_MASK,
1785 (1 << CS42L42_ADC_OVFL_SHIFT));
1786
1787 regmap_update_bits(cs42l42->regmap, CS42L42_MIXER_INT_MASK,
1788 CS42L42_MIX_CHB_OVFL_MASK |
1789 CS42L42_MIX_CHA_OVFL_MASK |
1790 CS42L42_EQ_OVFL_MASK |
1791 CS42L42_EQ_BIQUAD_OVFL_MASK,
1792 (1 << CS42L42_MIX_CHB_OVFL_SHIFT) |
1793 (1 << CS42L42_MIX_CHA_OVFL_SHIFT) |
1794 (1 << CS42L42_EQ_OVFL_SHIFT) |
1795 (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT));
1796
1797 regmap_update_bits(cs42l42->regmap, CS42L42_SRC_INT_MASK,
1798 CS42L42_SRC_ILK_MASK |
1799 CS42L42_SRC_OLK_MASK |
1800 CS42L42_SRC_IUNLK_MASK |
1801 CS42L42_SRC_OUNLK_MASK,
1802 (1 << CS42L42_SRC_ILK_SHIFT) |
1803 (1 << CS42L42_SRC_OLK_SHIFT) |
1804 (1 << CS42L42_SRC_IUNLK_SHIFT) |
1805 (1 << CS42L42_SRC_OUNLK_SHIFT));
1806
1807 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_RX_INT_MASK,
1808 CS42L42_ASPRX_NOLRCK_MASK |
1809 CS42L42_ASPRX_EARLY_MASK |
1810 CS42L42_ASPRX_LATE_MASK |
1811 CS42L42_ASPRX_ERROR_MASK |
1812 CS42L42_ASPRX_OVLD_MASK,
1813 (1 << CS42L42_ASPRX_NOLRCK_SHIFT) |
1814 (1 << CS42L42_ASPRX_EARLY_SHIFT) |
1815 (1 << CS42L42_ASPRX_LATE_SHIFT) |
1816 (1 << CS42L42_ASPRX_ERROR_SHIFT) |
1817 (1 << CS42L42_ASPRX_OVLD_SHIFT));
1818
1819 regmap_update_bits(cs42l42->regmap, CS42L42_ASP_TX_INT_MASK,
1820 CS42L42_ASPTX_NOLRCK_MASK |
1821 CS42L42_ASPTX_EARLY_MASK |
1822 CS42L42_ASPTX_LATE_MASK |
1823 CS42L42_ASPTX_SMERROR_MASK,
1824 (1 << CS42L42_ASPTX_NOLRCK_SHIFT) |
1825 (1 << CS42L42_ASPTX_EARLY_SHIFT) |
1826 (1 << CS42L42_ASPTX_LATE_SHIFT) |
1827 (1 << CS42L42_ASPTX_SMERROR_SHIFT));
1828
1829 regmap_update_bits(cs42l42->regmap, CS42L42_CODEC_INT_MASK,
1830 CS42L42_PDN_DONE_MASK |
1831 CS42L42_HSDET_AUTO_DONE_MASK,
1832 (1 << CS42L42_PDN_DONE_SHIFT) |
1833 (1 << CS42L42_HSDET_AUTO_DONE_SHIFT));
1834
1835 regmap_update_bits(cs42l42->regmap, CS42L42_SRCPL_INT_MASK,
1836 CS42L42_SRCPL_ADC_LK_MASK |
1837 CS42L42_SRCPL_DAC_LK_MASK |
1838 CS42L42_SRCPL_ADC_UNLK_MASK |
1839 CS42L42_SRCPL_DAC_UNLK_MASK,
1840 (1 << CS42L42_SRCPL_ADC_LK_SHIFT) |
1841 (1 << CS42L42_SRCPL_DAC_LK_SHIFT) |
1842 (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) |
1843 (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT));
1844
1845 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT1_MASK,
1846 CS42L42_TIP_SENSE_UNPLUG_MASK |
1847 CS42L42_TIP_SENSE_PLUG_MASK |
1848 CS42L42_HSBIAS_SENSE_MASK,
1849 (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) |
1850 (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) |
1851 (1 << CS42L42_HSBIAS_SENSE_SHIFT));
1852
1853 regmap_update_bits(cs42l42->regmap, CS42L42_DET_INT2_MASK,
1854 CS42L42_M_DETECT_TF_MASK |
1855 CS42L42_M_DETECT_FT_MASK |
1856 CS42L42_M_HSBIAS_HIZ_MASK |
1857 CS42L42_M_SHORT_RLS_MASK |
1858 CS42L42_M_SHORT_DET_MASK,
1859 (1 << CS42L42_M_DETECT_TF_SHIFT) |
1860 (1 << CS42L42_M_DETECT_FT_SHIFT) |
1861 (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) |
1862 (1 << CS42L42_M_SHORT_RLS_SHIFT) |
1863 (1 << CS42L42_M_SHORT_DET_SHIFT));
1864
1865 regmap_update_bits(cs42l42->regmap, CS42L42_VPMON_INT_MASK,
1866 CS42L42_VPMON_MASK,
1867 (1 << CS42L42_VPMON_SHIFT));
1868
1869 regmap_update_bits(cs42l42->regmap, CS42L42_PLL_LOCK_INT_MASK,
1870 CS42L42_PLL_LOCK_MASK,
1871 (1 << CS42L42_PLL_LOCK_SHIFT));
1872
1873 regmap_update_bits(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK,
1874 CS42L42_RS_PLUG_MASK |
1875 CS42L42_RS_UNPLUG_MASK |
1876 CS42L42_TS_PLUG_MASK |
1877 CS42L42_TS_UNPLUG_MASK,
1878 (1 << CS42L42_RS_PLUG_SHIFT) |
1879 (1 << CS42L42_RS_UNPLUG_SHIFT) |
1880 (0 << CS42L42_TS_PLUG_SHIFT) |
1881 (0 << CS42L42_TS_UNPLUG_SHIFT));
1882 }
1883
cs42l42_setup_hs_type_detect(struct cs42l42_private * cs42l42)1884 static void cs42l42_setup_hs_type_detect(struct cs42l42_private *cs42l42)
1885 {
1886 unsigned int reg;
1887
1888 cs42l42->hs_type = CS42L42_PLUG_INVALID;
1889
1890 /*
1891 * DETECT_MODE must always be 0 with ADC and HP both off otherwise the
1892 * FILT+ supply will not charge properly.
1893 */
1894 regmap_update_bits(cs42l42->regmap, CS42L42_MISC_DET_CTL,
1895 CS42L42_DETECT_MODE_MASK, 0);
1896
1897 /* Latch analog controls to VP power domain */
1898 regmap_update_bits(cs42l42->regmap, CS42L42_MIC_DET_CTL1,
1899 CS42L42_LATCH_TO_VP_MASK |
1900 CS42L42_EVENT_STAT_SEL_MASK |
1901 CS42L42_HS_DET_LEVEL_MASK,
1902 (1 << CS42L42_LATCH_TO_VP_SHIFT) |
1903 (0 << CS42L42_EVENT_STAT_SEL_SHIFT) |
1904 (cs42l42->bias_thresholds[0] <<
1905 CS42L42_HS_DET_LEVEL_SHIFT));
1906
1907 /* Remove ground noise-suppression clamps */
1908 regmap_update_bits(cs42l42->regmap,
1909 CS42L42_HS_CLAMP_DISABLE,
1910 CS42L42_HS_CLAMP_DISABLE_MASK,
1911 (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT));
1912
1913 /* Enable the tip sense circuit */
1914 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1915 CS42L42_TS_INV_MASK, CS42L42_TS_INV_MASK);
1916
1917 regmap_update_bits(cs42l42->regmap, CS42L42_TIPSENSE_CTL,
1918 CS42L42_TIP_SENSE_CTRL_MASK |
1919 CS42L42_TIP_SENSE_INV_MASK |
1920 CS42L42_TIP_SENSE_DEBOUNCE_MASK,
1921 (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) |
1922 (!cs42l42->ts_inv << CS42L42_TIP_SENSE_INV_SHIFT) |
1923 (2 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT));
1924
1925 /* Save the initial status of the tip sense */
1926 regmap_read(cs42l42->regmap,
1927 CS42L42_TSRS_PLUG_STATUS,
1928 ®);
1929 cs42l42->plug_state = (((char) reg) &
1930 (CS42L42_TS_PLUG_MASK | CS42L42_TS_UNPLUG_MASK)) >>
1931 CS42L42_TS_PLUG_SHIFT;
1932 }
1933
1934 static const unsigned int threshold_defaults[] = {
1935 CS42L42_HS_DET_LEVEL_15,
1936 CS42L42_HS_DET_LEVEL_8,
1937 CS42L42_HS_DET_LEVEL_4,
1938 CS42L42_HS_DET_LEVEL_1
1939 };
1940
cs42l42_handle_device_data(struct device * dev,struct cs42l42_private * cs42l42)1941 static int cs42l42_handle_device_data(struct device *dev,
1942 struct cs42l42_private *cs42l42)
1943 {
1944 unsigned int val;
1945 u32 thresholds[CS42L42_NUM_BIASES];
1946 int ret;
1947 int i;
1948
1949 ret = device_property_read_u32(dev, "cirrus,ts-inv", &val);
1950 if (!ret) {
1951 switch (val) {
1952 case CS42L42_TS_INV_EN:
1953 case CS42L42_TS_INV_DIS:
1954 cs42l42->ts_inv = val;
1955 break;
1956 default:
1957 dev_err(dev,
1958 "Wrong cirrus,ts-inv DT value %d\n",
1959 val);
1960 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1961 }
1962 } else {
1963 cs42l42->ts_inv = CS42L42_TS_INV_DIS;
1964 }
1965
1966 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-rise", &val);
1967 if (!ret) {
1968 switch (val) {
1969 case CS42L42_TS_DBNCE_0:
1970 case CS42L42_TS_DBNCE_125:
1971 case CS42L42_TS_DBNCE_250:
1972 case CS42L42_TS_DBNCE_500:
1973 case CS42L42_TS_DBNCE_750:
1974 case CS42L42_TS_DBNCE_1000:
1975 case CS42L42_TS_DBNCE_1250:
1976 case CS42L42_TS_DBNCE_1500:
1977 cs42l42->ts_dbnc_rise = val;
1978 break;
1979 default:
1980 dev_err(dev,
1981 "Wrong cirrus,ts-dbnc-rise DT value %d\n",
1982 val);
1983 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1984 }
1985 } else {
1986 cs42l42->ts_dbnc_rise = CS42L42_TS_DBNCE_1000;
1987 }
1988
1989 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
1990 CS42L42_TS_RISE_DBNCE_TIME_MASK,
1991 (cs42l42->ts_dbnc_rise <<
1992 CS42L42_TS_RISE_DBNCE_TIME_SHIFT));
1993
1994 ret = device_property_read_u32(dev, "cirrus,ts-dbnc-fall", &val);
1995 if (!ret) {
1996 switch (val) {
1997 case CS42L42_TS_DBNCE_0:
1998 case CS42L42_TS_DBNCE_125:
1999 case CS42L42_TS_DBNCE_250:
2000 case CS42L42_TS_DBNCE_500:
2001 case CS42L42_TS_DBNCE_750:
2002 case CS42L42_TS_DBNCE_1000:
2003 case CS42L42_TS_DBNCE_1250:
2004 case CS42L42_TS_DBNCE_1500:
2005 cs42l42->ts_dbnc_fall = val;
2006 break;
2007 default:
2008 dev_err(dev,
2009 "Wrong cirrus,ts-dbnc-fall DT value %d\n",
2010 val);
2011 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
2012 }
2013 } else {
2014 cs42l42->ts_dbnc_fall = CS42L42_TS_DBNCE_0;
2015 }
2016
2017 regmap_update_bits(cs42l42->regmap, CS42L42_TSENSE_CTL,
2018 CS42L42_TS_FALL_DBNCE_TIME_MASK,
2019 (cs42l42->ts_dbnc_fall <<
2020 CS42L42_TS_FALL_DBNCE_TIME_SHIFT));
2021
2022 ret = device_property_read_u32(dev, "cirrus,btn-det-init-dbnce", &val);
2023 if (!ret) {
2024 if (val <= CS42L42_BTN_DET_INIT_DBNCE_MAX)
2025 cs42l42->btn_det_init_dbnce = val;
2026 else {
2027 dev_err(dev,
2028 "Wrong cirrus,btn-det-init-dbnce DT value %d\n",
2029 val);
2030 cs42l42->btn_det_init_dbnce =
2031 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
2032 }
2033 } else {
2034 cs42l42->btn_det_init_dbnce =
2035 CS42L42_BTN_DET_INIT_DBNCE_DEFAULT;
2036 }
2037
2038 ret = device_property_read_u32(dev, "cirrus,btn-det-event-dbnce", &val);
2039 if (!ret) {
2040 if (val <= CS42L42_BTN_DET_EVENT_DBNCE_MAX)
2041 cs42l42->btn_det_event_dbnce = val;
2042 else {
2043 dev_err(dev,
2044 "Wrong cirrus,btn-det-event-dbnce DT value %d\n", val);
2045 cs42l42->btn_det_event_dbnce =
2046 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2047 }
2048 } else {
2049 cs42l42->btn_det_event_dbnce =
2050 CS42L42_BTN_DET_EVENT_DBNCE_DEFAULT;
2051 }
2052
2053 ret = device_property_read_u32_array(dev, "cirrus,bias-lvls",
2054 thresholds, ARRAY_SIZE(thresholds));
2055 if (!ret) {
2056 for (i = 0; i < CS42L42_NUM_BIASES; i++) {
2057 if (thresholds[i] <= CS42L42_HS_DET_LEVEL_MAX)
2058 cs42l42->bias_thresholds[i] = thresholds[i];
2059 else {
2060 dev_err(dev,
2061 "Wrong cirrus,bias-lvls[%d] DT value %d\n", i,
2062 thresholds[i]);
2063 cs42l42->bias_thresholds[i] = threshold_defaults[i];
2064 }
2065 }
2066 } else {
2067 for (i = 0; i < CS42L42_NUM_BIASES; i++)
2068 cs42l42->bias_thresholds[i] = threshold_defaults[i];
2069 }
2070
2071 ret = device_property_read_u32(dev, "cirrus,hs-bias-ramp-rate", &val);
2072 if (!ret) {
2073 switch (val) {
2074 case CS42L42_HSBIAS_RAMP_FAST_RISE_SLOW_FALL:
2075 cs42l42->hs_bias_ramp_rate = val;
2076 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME0;
2077 break;
2078 case CS42L42_HSBIAS_RAMP_FAST:
2079 cs42l42->hs_bias_ramp_rate = val;
2080 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME1;
2081 break;
2082 case CS42L42_HSBIAS_RAMP_SLOW:
2083 cs42l42->hs_bias_ramp_rate = val;
2084 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2085 break;
2086 case CS42L42_HSBIAS_RAMP_SLOWEST:
2087 cs42l42->hs_bias_ramp_rate = val;
2088 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME3;
2089 break;
2090 default:
2091 dev_err(dev,
2092 "Wrong cirrus,hs-bias-ramp-rate DT value %d\n",
2093 val);
2094 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2095 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2096 }
2097 } else {
2098 cs42l42->hs_bias_ramp_rate = CS42L42_HSBIAS_RAMP_SLOW;
2099 cs42l42->hs_bias_ramp_time = CS42L42_HSBIAS_RAMP_TIME2;
2100 }
2101
2102 regmap_update_bits(cs42l42->regmap, CS42L42_HS_BIAS_CTL,
2103 CS42L42_HSBIAS_RAMP_MASK,
2104 (cs42l42->hs_bias_ramp_rate <<
2105 CS42L42_HSBIAS_RAMP_SHIFT));
2106
2107 if (device_property_read_bool(dev, "cirrus,hs-bias-sense-disable"))
2108 cs42l42->hs_bias_sense_en = 0;
2109 else
2110 cs42l42->hs_bias_sense_en = 1;
2111
2112 return 0;
2113 }
2114
2115 /* Datasheet suspend sequence */
2116 static const struct reg_sequence __maybe_unused cs42l42_shutdown_seq[] = {
2117 REG_SEQ0(CS42L42_MIC_DET_CTL1, 0x9F),
2118 REG_SEQ0(CS42L42_ADC_OVFL_INT_MASK, 0x01),
2119 REG_SEQ0(CS42L42_MIXER_INT_MASK, 0x0F),
2120 REG_SEQ0(CS42L42_SRC_INT_MASK, 0x0F),
2121 REG_SEQ0(CS42L42_ASP_RX_INT_MASK, 0x1F),
2122 REG_SEQ0(CS42L42_ASP_TX_INT_MASK, 0x0F),
2123 REG_SEQ0(CS42L42_CODEC_INT_MASK, 0x03),
2124 REG_SEQ0(CS42L42_SRCPL_INT_MASK, 0x7F),
2125 REG_SEQ0(CS42L42_VPMON_INT_MASK, 0x01),
2126 REG_SEQ0(CS42L42_PLL_LOCK_INT_MASK, 0x01),
2127 REG_SEQ0(CS42L42_TSRS_PLUG_INT_MASK, 0x0F),
2128 REG_SEQ0(CS42L42_WAKE_CTL, 0xE1),
2129 REG_SEQ0(CS42L42_DET_INT1_MASK, 0xE0),
2130 REG_SEQ0(CS42L42_DET_INT2_MASK, 0xFF),
2131 REG_SEQ0(CS42L42_MIXER_CHA_VOL, 0x3F),
2132 REG_SEQ0(CS42L42_MIXER_ADC_VOL, 0x3F),
2133 REG_SEQ0(CS42L42_MIXER_CHB_VOL, 0x3F),
2134 REG_SEQ0(CS42L42_HP_CTL, 0x0F),
2135 REG_SEQ0(CS42L42_ASP_RX_DAI0_EN, 0x00),
2136 REG_SEQ0(CS42L42_ASP_CLK_CFG, 0x00),
2137 REG_SEQ0(CS42L42_HSDET_CTL2, 0x00),
2138 REG_SEQ0(CS42L42_PWR_CTL1, 0xFE),
2139 REG_SEQ0(CS42L42_PWR_CTL2, 0x8C),
2140 REG_SEQ0(CS42L42_DAC_CTL2, 0x02),
2141 REG_SEQ0(CS42L42_HS_CLAMP_DISABLE, 0x00),
2142 REG_SEQ0(CS42L42_MISC_DET_CTL, 0x03),
2143 REG_SEQ0(CS42L42_TIPSENSE_CTL, 0x02),
2144 REG_SEQ0(CS42L42_HSBIAS_SC_AUTOCTL, 0x03),
2145 REG_SEQ0(CS42L42_PWR_CTL1, 0xFF)
2146 };
2147
cs42l42_suspend(struct device * dev)2148 int cs42l42_suspend(struct device *dev)
2149 {
2150 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2151 unsigned int reg;
2152 u8 save_regs[ARRAY_SIZE(cs42l42_shutdown_seq)];
2153 int i, ret;
2154
2155 if (!cs42l42->init_done)
2156 return 0;
2157
2158 /*
2159 * Wait for threaded irq handler to be idle and stop it processing
2160 * future interrupts. This ensures a safe disable if the interrupt
2161 * is shared.
2162 */
2163 mutex_lock(&cs42l42->irq_lock);
2164 cs42l42->suspended = true;
2165
2166 /* Save register values that will be overwritten by shutdown sequence */
2167 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i) {
2168 regmap_read(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, ®);
2169 save_regs[i] = (u8)reg;
2170 }
2171
2172 /* Shutdown codec */
2173 regmap_multi_reg_write(cs42l42->regmap,
2174 cs42l42_shutdown_seq,
2175 ARRAY_SIZE(cs42l42_shutdown_seq));
2176
2177 /* All interrupt sources are now disabled */
2178 mutex_unlock(&cs42l42->irq_lock);
2179
2180 /* Wait for power-down complete */
2181 msleep(CS42L42_PDN_DONE_TIME_MS);
2182 ret = regmap_read_poll_timeout(cs42l42->regmap,
2183 CS42L42_CODEC_STATUS, reg,
2184 (reg & CS42L42_PDN_DONE_MASK),
2185 CS42L42_PDN_DONE_POLL_US,
2186 CS42L42_PDN_DONE_TIMEOUT_US);
2187 if (ret)
2188 dev_warn(dev, "Failed to get PDN_DONE: %d\n", ret);
2189
2190 /* Discharge FILT+ */
2191 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
2192 CS42L42_DISCHARGE_FILT_MASK, CS42L42_DISCHARGE_FILT_MASK);
2193 msleep(CS42L42_FILT_DISCHARGE_TIME_MS);
2194
2195 regcache_cache_only(cs42l42->regmap, true);
2196 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2197 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2198
2199 /* Restore register values to the regmap cache */
2200 for (i = 0; i < ARRAY_SIZE(cs42l42_shutdown_seq); ++i)
2201 regmap_write(cs42l42->regmap, cs42l42_shutdown_seq[i].reg, save_regs[i]);
2202
2203 /* The cached address page register value is now stale */
2204 regcache_drop_region(cs42l42->regmap, CS42L42_PAGE_REGISTER, CS42L42_PAGE_REGISTER);
2205
2206 dev_dbg(dev, "System suspended\n");
2207
2208 return 0;
2209
2210 }
2211 EXPORT_SYMBOL_NS_GPL(cs42l42_suspend, SND_SOC_CS42L42_CORE);
2212
cs42l42_resume(struct device * dev)2213 int cs42l42_resume(struct device *dev)
2214 {
2215 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2216 int ret;
2217
2218 if (!cs42l42->init_done)
2219 return 0;
2220
2221 /*
2222 * If jack was unplugged and re-plugged during suspend it could
2223 * have changed type but the tip-sense state hasn't changed.
2224 * Force a plugged state to be re-evaluated.
2225 */
2226 if (cs42l42->plug_state != CS42L42_TS_UNPLUG)
2227 cs42l42->plug_state = CS42L42_TS_TRANS;
2228
2229 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2230 if (ret != 0) {
2231 dev_err(dev, "Failed to enable supplies: %d\n", ret);
2232 return ret;
2233 }
2234
2235 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2236 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2237
2238 dev_dbg(dev, "System resume powered up\n");
2239
2240 return 0;
2241 }
2242 EXPORT_SYMBOL_NS_GPL(cs42l42_resume, SND_SOC_CS42L42_CORE);
2243
cs42l42_resume_restore(struct device * dev)2244 void cs42l42_resume_restore(struct device *dev)
2245 {
2246 struct cs42l42_private *cs42l42 = dev_get_drvdata(dev);
2247
2248 regcache_cache_only(cs42l42->regmap, false);
2249 regcache_mark_dirty(cs42l42->regmap);
2250
2251 mutex_lock(&cs42l42->irq_lock);
2252 /* Sync LATCH_TO_VP first so the VP domain registers sync correctly */
2253 regcache_sync_region(cs42l42->regmap, CS42L42_MIC_DET_CTL1, CS42L42_MIC_DET_CTL1);
2254 regcache_sync(cs42l42->regmap);
2255
2256 cs42l42->suspended = false;
2257 mutex_unlock(&cs42l42->irq_lock);
2258
2259 dev_dbg(dev, "System resumed\n");
2260 }
2261 EXPORT_SYMBOL_NS_GPL(cs42l42_resume_restore, SND_SOC_CS42L42_CORE);
2262
cs42l42_i2c_resume(struct device * dev)2263 static int __maybe_unused cs42l42_i2c_resume(struct device *dev)
2264 {
2265 int ret;
2266
2267 ret = cs42l42_resume(dev);
2268 if (ret)
2269 return ret;
2270
2271 cs42l42_resume_restore(dev);
2272
2273 return 0;
2274 }
2275
cs42l42_common_probe(struct cs42l42_private * cs42l42,const struct snd_soc_component_driver * component_drv,struct snd_soc_dai_driver * dai)2276 int cs42l42_common_probe(struct cs42l42_private *cs42l42,
2277 const struct snd_soc_component_driver *component_drv,
2278 struct snd_soc_dai_driver *dai)
2279 {
2280 int ret, i;
2281
2282 dev_set_drvdata(cs42l42->dev, cs42l42);
2283 mutex_init(&cs42l42->irq_lock);
2284
2285 BUILD_BUG_ON(ARRAY_SIZE(cs42l42_supply_names) != ARRAY_SIZE(cs42l42->supplies));
2286 for (i = 0; i < ARRAY_SIZE(cs42l42->supplies); i++)
2287 cs42l42->supplies[i].supply = cs42l42_supply_names[i];
2288
2289 ret = devm_regulator_bulk_get(cs42l42->dev,
2290 ARRAY_SIZE(cs42l42->supplies),
2291 cs42l42->supplies);
2292 if (ret != 0) {
2293 dev_err(cs42l42->dev,
2294 "Failed to request supplies: %d\n", ret);
2295 return ret;
2296 }
2297
2298 ret = regulator_bulk_enable(ARRAY_SIZE(cs42l42->supplies),
2299 cs42l42->supplies);
2300 if (ret != 0) {
2301 dev_err(cs42l42->dev,
2302 "Failed to enable supplies: %d\n", ret);
2303 return ret;
2304 }
2305
2306 /* Reset the Device */
2307 cs42l42->reset_gpio = devm_gpiod_get_optional(cs42l42->dev,
2308 "reset", GPIOD_OUT_LOW);
2309 if (IS_ERR(cs42l42->reset_gpio)) {
2310 ret = PTR_ERR(cs42l42->reset_gpio);
2311 goto err_disable_noreset;
2312 }
2313
2314 if (cs42l42->reset_gpio) {
2315 dev_dbg(cs42l42->dev, "Found reset GPIO\n");
2316 gpiod_set_value_cansleep(cs42l42->reset_gpio, 1);
2317 }
2318 usleep_range(CS42L42_BOOT_TIME_US, CS42L42_BOOT_TIME_US * 2);
2319
2320 /* Request IRQ if one was specified */
2321 if (cs42l42->irq) {
2322 ret = request_threaded_irq(cs42l42->irq,
2323 NULL, cs42l42_irq_thread,
2324 IRQF_ONESHOT | IRQF_TRIGGER_LOW,
2325 "cs42l42", cs42l42);
2326 if (ret) {
2327 dev_err_probe(cs42l42->dev, ret,
2328 "Failed to request IRQ\n");
2329 goto err_disable_noirq;
2330 }
2331 }
2332
2333 /* Register codec now so it can EPROBE_DEFER */
2334 ret = devm_snd_soc_register_component(cs42l42->dev, component_drv, dai, 1);
2335 if (ret < 0)
2336 goto err;
2337
2338 return 0;
2339
2340 err:
2341 if (cs42l42->irq)
2342 free_irq(cs42l42->irq, cs42l42);
2343
2344 err_disable_noirq:
2345 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2346 err_disable_noreset:
2347 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2348
2349 return ret;
2350 }
2351 EXPORT_SYMBOL_NS_GPL(cs42l42_common_probe, SND_SOC_CS42L42_CORE);
2352
cs42l42_init(struct cs42l42_private * cs42l42)2353 int cs42l42_init(struct cs42l42_private *cs42l42)
2354 {
2355 unsigned int reg;
2356 int devid, ret;
2357
2358 /* initialize codec */
2359 devid = cirrus_read_device_id(cs42l42->regmap, CS42L42_DEVID_AB);
2360 if (devid < 0) {
2361 ret = devid;
2362 dev_err(cs42l42->dev, "Failed to read device ID: %d\n", ret);
2363 goto err_disable;
2364 }
2365
2366 if (devid != cs42l42->devid) {
2367 ret = -ENODEV;
2368 dev_err(cs42l42->dev,
2369 "CS42L%x Device ID (%X). Expected %X\n",
2370 cs42l42->devid & 0xff, devid, cs42l42->devid);
2371 goto err_disable;
2372 }
2373
2374 ret = regmap_read(cs42l42->regmap, CS42L42_REVID, ®);
2375 if (ret < 0) {
2376 dev_err(cs42l42->dev, "Get Revision ID failed\n");
2377 goto err_shutdown;
2378 }
2379
2380 dev_info(cs42l42->dev,
2381 "Cirrus Logic CS42L%x, Revision: %02X\n",
2382 cs42l42->devid & 0xff, reg & 0xFF);
2383
2384 /* Power up the codec */
2385 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL1,
2386 CS42L42_ASP_DAO_PDN_MASK |
2387 CS42L42_ASP_DAI_PDN_MASK |
2388 CS42L42_MIXER_PDN_MASK |
2389 CS42L42_EQ_PDN_MASK |
2390 CS42L42_HP_PDN_MASK |
2391 CS42L42_ADC_PDN_MASK |
2392 CS42L42_PDN_ALL_MASK,
2393 (1 << CS42L42_ASP_DAO_PDN_SHIFT) |
2394 (1 << CS42L42_ASP_DAI_PDN_SHIFT) |
2395 (1 << CS42L42_MIXER_PDN_SHIFT) |
2396 (1 << CS42L42_EQ_PDN_SHIFT) |
2397 (1 << CS42L42_HP_PDN_SHIFT) |
2398 (1 << CS42L42_ADC_PDN_SHIFT) |
2399 (0 << CS42L42_PDN_ALL_SHIFT));
2400
2401 ret = cs42l42_handle_device_data(cs42l42->dev, cs42l42);
2402 if (ret != 0)
2403 goto err_shutdown;
2404
2405 /*
2406 * SRC power is linked to ASP power so doesn't work in Soundwire mode.
2407 * Override it and use DAPM to control SRC power for Soundwire.
2408 */
2409 if (cs42l42->sdw_peripheral) {
2410 regmap_update_bits(cs42l42->regmap, CS42L42_PWR_CTL2,
2411 CS42L42_SRC_PDN_OVERRIDE_MASK |
2412 CS42L42_DAC_SRC_PDNB_MASK |
2413 CS42L42_ADC_SRC_PDNB_MASK,
2414 CS42L42_SRC_PDN_OVERRIDE_MASK);
2415 }
2416
2417 /* Setup headset detection */
2418 cs42l42_setup_hs_type_detect(cs42l42);
2419
2420 /*
2421 * Set init_done before unmasking interrupts so any triggered
2422 * immediately will be handled.
2423 */
2424 cs42l42->init_done = true;
2425
2426 /* Mask/Unmask Interrupts */
2427 cs42l42_set_interrupt_masks(cs42l42);
2428
2429 return 0;
2430
2431 err_shutdown:
2432 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2433 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2434 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2435
2436 err_disable:
2437 if (cs42l42->irq)
2438 free_irq(cs42l42->irq, cs42l42);
2439
2440 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2441 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies),
2442 cs42l42->supplies);
2443 return ret;
2444 }
2445 EXPORT_SYMBOL_NS_GPL(cs42l42_init, SND_SOC_CS42L42_CORE);
2446
cs42l42_common_remove(struct cs42l42_private * cs42l42)2447 void cs42l42_common_remove(struct cs42l42_private *cs42l42)
2448 {
2449 if (cs42l42->irq)
2450 free_irq(cs42l42->irq, cs42l42);
2451
2452 /*
2453 * The driver might not have control of reset and power supplies,
2454 * so ensure that the chip internals are powered down.
2455 */
2456 if (cs42l42->init_done) {
2457 regmap_write(cs42l42->regmap, CS42L42_CODEC_INT_MASK, 0xff);
2458 regmap_write(cs42l42->regmap, CS42L42_TSRS_PLUG_INT_MASK, 0xff);
2459 regmap_write(cs42l42->regmap, CS42L42_PWR_CTL1, 0xff);
2460 }
2461
2462 gpiod_set_value_cansleep(cs42l42->reset_gpio, 0);
2463 regulator_bulk_disable(ARRAY_SIZE(cs42l42->supplies), cs42l42->supplies);
2464 }
2465 EXPORT_SYMBOL_NS_GPL(cs42l42_common_remove, SND_SOC_CS42L42_CORE);
2466
2467 MODULE_DESCRIPTION("ASoC CS42L42 driver");
2468 MODULE_AUTHOR("James Schulman, Cirrus Logic Inc, <james.schulman@cirrus.com>");
2469 MODULE_AUTHOR("Brian Austin, Cirrus Logic Inc, <brian.austin@cirrus.com>");
2470 MODULE_AUTHOR("Michael White, Cirrus Logic Inc, <michael.white@cirrus.com>");
2471 MODULE_AUTHOR("Lucas Tanure <tanureal@opensource.cirrus.com>");
2472 MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
2473 MODULE_AUTHOR("Vitaly Rodionov <vitalyr@opensource.cirrus.com>");
2474 MODULE_LICENSE("GPL");
2475