1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dc_bios_types.h"
28 #include "dcn30_dio_stream_encoder.h"
29 #include "reg_helper.h"
30 #include "hw_shared.h"
31 #include "core_types.h"
32 #include <linux/delay.h>
33
34
35 #define DC_LOGGER \
36 enc1->base.ctx->logger
37
38 #define REG(reg)\
39 (enc1->regs->reg)
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 enc1->se_shift->field_name, enc1->se_mask->field_name
44
45 #define VBI_LINE_0 0
46 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
47
48 #define CTX \
49 enc1->base.ctx
50
51
enc3_update_hdmi_info_packet(struct dcn10_stream_encoder * enc1,uint32_t packet_index,const struct dc_info_packet * info_packet)52 static void enc3_update_hdmi_info_packet(
53 struct dcn10_stream_encoder *enc1,
54 uint32_t packet_index,
55 const struct dc_info_packet *info_packet)
56 {
57 uint32_t cont, send, line;
58
59 if (info_packet->valid) {
60 enc1->base.vpg->funcs->update_generic_info_packet(
61 enc1->base.vpg,
62 packet_index,
63 info_packet,
64 true);
65
66 /* enable transmission of packet(s) -
67 * packet transmission begins on the next frame */
68 cont = 1;
69 /* send packet(s) every frame */
70 send = 1;
71 /* select line number to send packets on */
72 line = 2;
73 } else {
74 cont = 0;
75 send = 0;
76 line = 0;
77 }
78
79 /* DP_SEC_GSP[x]_LINE_REFERENCE - keep default value REFER_TO_DP_SOF */
80
81 /* choose which generic packet control to use */
82 switch (packet_index) {
83 case 0:
84 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
85 HDMI_GENERIC0_CONT, cont,
86 HDMI_GENERIC0_SEND, send);
87 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
88 HDMI_GENERIC0_LINE, line);
89 break;
90 case 1:
91 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
92 HDMI_GENERIC1_CONT, cont,
93 HDMI_GENERIC1_SEND, send);
94 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL1,
95 HDMI_GENERIC1_LINE, line);
96 break;
97 case 2:
98 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
99 HDMI_GENERIC2_CONT, cont,
100 HDMI_GENERIC2_SEND, send);
101 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
102 HDMI_GENERIC2_LINE, line);
103 break;
104 case 3:
105 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
106 HDMI_GENERIC3_CONT, cont,
107 HDMI_GENERIC3_SEND, send);
108 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL2,
109 HDMI_GENERIC3_LINE, line);
110 break;
111 case 4:
112 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
113 HDMI_GENERIC4_CONT, cont,
114 HDMI_GENERIC4_SEND, send);
115 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
116 HDMI_GENERIC4_LINE, line);
117 break;
118 case 5:
119 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
120 HDMI_GENERIC5_CONT, cont,
121 HDMI_GENERIC5_SEND, send);
122 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL3,
123 HDMI_GENERIC5_LINE, line);
124 break;
125 case 6:
126 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
127 HDMI_GENERIC6_CONT, cont,
128 HDMI_GENERIC6_SEND, send);
129 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
130 HDMI_GENERIC6_LINE, line);
131 break;
132 case 7:
133 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL0,
134 HDMI_GENERIC7_CONT, cont,
135 HDMI_GENERIC7_SEND, send);
136 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL4,
137 HDMI_GENERIC7_LINE, line);
138 break;
139 case 8:
140 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
141 HDMI_GENERIC8_CONT, cont,
142 HDMI_GENERIC8_SEND, send);
143 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
144 HDMI_GENERIC8_LINE, line);
145 break;
146 case 9:
147 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
148 HDMI_GENERIC9_CONT, cont,
149 HDMI_GENERIC9_SEND, send);
150 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL7,
151 HDMI_GENERIC9_LINE, line);
152 break;
153 case 10:
154 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
155 HDMI_GENERIC10_CONT, cont,
156 HDMI_GENERIC10_SEND, send);
157 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
158 HDMI_GENERIC10_LINE, line);
159 break;
160 case 11:
161 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
162 HDMI_GENERIC11_CONT, cont,
163 HDMI_GENERIC11_SEND, send);
164 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL8,
165 HDMI_GENERIC11_LINE, line);
166 break;
167 case 12:
168 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
169 HDMI_GENERIC12_CONT, cont,
170 HDMI_GENERIC12_SEND, send);
171 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
172 HDMI_GENERIC12_LINE, line);
173 break;
174 case 13:
175 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
176 HDMI_GENERIC13_CONT, cont,
177 HDMI_GENERIC13_SEND, send);
178 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL9,
179 HDMI_GENERIC13_LINE, line);
180 break;
181 case 14:
182 REG_UPDATE_2(HDMI_GENERIC_PACKET_CONTROL6,
183 HDMI_GENERIC14_CONT, cont,
184 HDMI_GENERIC14_SEND, send);
185 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
186 HDMI_GENERIC14_LINE, line);
187 break;
188 default:
189 /* invalid HW packet index */
190 DC_LOG_WARNING(
191 "Invalid HW packet index: %s()\n",
192 __func__);
193 return;
194 }
195 }
196
enc3_stream_encoder_update_hdmi_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)197 void enc3_stream_encoder_update_hdmi_info_packets(
198 struct stream_encoder *enc,
199 const struct encoder_info_frame *info_frame)
200 {
201 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
202
203 /* for bring up, disable dp double TODO */
204 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1);
205 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
206
207 /*Always add mandatory packets first followed by optional ones*/
208 enc3_update_hdmi_info_packet(enc1, 0, &info_frame->avi);
209 enc3_update_hdmi_info_packet(enc1, 5, &info_frame->hfvsif);
210 enc3_update_hdmi_info_packet(enc1, 2, &info_frame->gamut);
211 enc3_update_hdmi_info_packet(enc1, 1, &info_frame->vendor);
212 enc3_update_hdmi_info_packet(enc1, 3, &info_frame->spd);
213 enc3_update_hdmi_info_packet(enc1, 4, &info_frame->hdrsmd);
214 enc3_update_hdmi_info_packet(enc1, 6, &info_frame->vtem);
215 }
216
enc3_stream_encoder_stop_hdmi_info_packets(struct stream_encoder * enc)217 void enc3_stream_encoder_stop_hdmi_info_packets(
218 struct stream_encoder *enc)
219 {
220 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
221
222 /* stop generic packets 0,1 on HDMI */
223 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
224 HDMI_GENERIC0_CONT, 0,
225 HDMI_GENERIC0_SEND, 0,
226 HDMI_GENERIC1_CONT, 0,
227 HDMI_GENERIC1_SEND, 0);
228 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL1, 0,
229 HDMI_GENERIC0_LINE, 0,
230 HDMI_GENERIC1_LINE, 0);
231
232 /* stop generic packets 2,3 on HDMI */
233 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
234 HDMI_GENERIC2_CONT, 0,
235 HDMI_GENERIC2_SEND, 0,
236 HDMI_GENERIC3_CONT, 0,
237 HDMI_GENERIC3_SEND, 0);
238 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL2, 0,
239 HDMI_GENERIC2_LINE, 0,
240 HDMI_GENERIC3_LINE, 0);
241
242 /* stop generic packets 4,5 on HDMI */
243 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
244 HDMI_GENERIC4_CONT, 0,
245 HDMI_GENERIC4_SEND, 0,
246 HDMI_GENERIC5_CONT, 0,
247 HDMI_GENERIC5_SEND, 0);
248 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL3, 0,
249 HDMI_GENERIC4_LINE, 0,
250 HDMI_GENERIC5_LINE, 0);
251
252 /* stop generic packets 6,7 on HDMI */
253 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL0, 0,
254 HDMI_GENERIC6_CONT, 0,
255 HDMI_GENERIC6_SEND, 0,
256 HDMI_GENERIC7_CONT, 0,
257 HDMI_GENERIC7_SEND, 0);
258 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL4, 0,
259 HDMI_GENERIC6_LINE, 0,
260 HDMI_GENERIC7_LINE, 0);
261
262 /* stop generic packets 8,9 on HDMI */
263 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
264 HDMI_GENERIC8_CONT, 0,
265 HDMI_GENERIC8_SEND, 0,
266 HDMI_GENERIC9_CONT, 0,
267 HDMI_GENERIC9_SEND, 0);
268 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL7, 0,
269 HDMI_GENERIC8_LINE, 0,
270 HDMI_GENERIC9_LINE, 0);
271
272 /* stop generic packets 10,11 on HDMI */
273 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
274 HDMI_GENERIC10_CONT, 0,
275 HDMI_GENERIC10_SEND, 0,
276 HDMI_GENERIC11_CONT, 0,
277 HDMI_GENERIC11_SEND, 0);
278 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL8, 0,
279 HDMI_GENERIC10_LINE, 0,
280 HDMI_GENERIC11_LINE, 0);
281
282 /* stop generic packets 12,13 on HDMI */
283 REG_SET_4(HDMI_GENERIC_PACKET_CONTROL6, 0,
284 HDMI_GENERIC12_CONT, 0,
285 HDMI_GENERIC12_SEND, 0,
286 HDMI_GENERIC13_CONT, 0,
287 HDMI_GENERIC13_SEND, 0);
288 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL9, 0,
289 HDMI_GENERIC12_LINE, 0,
290 HDMI_GENERIC13_LINE, 0);
291
292 /* stop generic packet 14 on HDMI */
293 REG_SET_2(HDMI_GENERIC_PACKET_CONTROL6, 0,
294 HDMI_GENERIC14_CONT, 0,
295 HDMI_GENERIC14_SEND, 0);
296 REG_UPDATE(HDMI_GENERIC_PACKET_CONTROL10,
297 HDMI_GENERIC14_LINE, 0);
298 }
299
300 /* Set DSC-related configuration.
301 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
302 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
303 * dsc_slice_width: Slice width in pixels
304 */
enc3_dp_set_dsc_config(struct stream_encoder * enc,enum optc_dsc_mode dsc_mode,uint32_t dsc_bytes_per_pixel,uint32_t dsc_slice_width)305 static void enc3_dp_set_dsc_config(struct stream_encoder *enc,
306 enum optc_dsc_mode dsc_mode,
307 uint32_t dsc_bytes_per_pixel,
308 uint32_t dsc_slice_width)
309 {
310 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
311
312 REG_UPDATE_2(DP_DSC_CNTL,
313 DP_DSC_MODE, dsc_mode,
314 DP_DSC_SLICE_WIDTH, dsc_slice_width);
315
316 REG_SET(DP_DSC_BYTES_PER_PIXEL, 0,
317 DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel);
318 }
319
320
enc3_dp_set_dsc_pps_info_packet(struct stream_encoder * enc,bool enable,uint8_t * dsc_packed_pps,bool immediate_update)321 void enc3_dp_set_dsc_pps_info_packet(struct stream_encoder *enc,
322 bool enable,
323 uint8_t *dsc_packed_pps,
324 bool immediate_update)
325 {
326 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
327
328 if (enable) {
329 struct dc_info_packet pps_sdp;
330 int i;
331
332 /* Configure for PPS packet size (128 bytes) */
333 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 1);
334
335 /* We need turn on clock before programming AFMT block
336 *
337 * TODO: We may not need this here anymore since update_generic_info_packet
338 * no longer touches AFMT
339 */
340 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1);
341
342 /* Load PPS into infoframe (SDP) registers */
343 pps_sdp.valid = true;
344 pps_sdp.hb0 = 0;
345 pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS;
346 pps_sdp.hb2 = 127;
347 pps_sdp.hb3 = 0;
348
349 for (i = 0; i < 4; i++) {
350 memcpy(pps_sdp.sb, &dsc_packed_pps[i * 32], 32);
351 enc1->base.vpg->funcs->update_generic_info_packet(
352 enc1->base.vpg,
353 11 + i,
354 &pps_sdp,
355 immediate_update);
356 }
357
358 /* SW should make sure VBID[6] update line number is bigger
359 * than PPS transmit line number
360 */
361 REG_UPDATE(DP_GSP11_CNTL,
362 DP_SEC_GSP11_LINE_NUM, 2);
363 REG_UPDATE_2(DP_MSA_VBID_MISC,
364 DP_VBID6_LINE_REFERENCE, 0,
365 DP_VBID6_LINE_NUM, 3);
366
367 /* Send PPS data at the line number specified above.
368 * DP spec requires PPS to be sent only when it changes, however since
369 * decoder has to be able to handle its change on every frame, we're
370 * sending it always (i.e. on every frame) to reduce the chance it'd be
371 * missed by decoder. If it turns out required to send PPS only when it
372 * changes, we can use DP_SEC_GSP11_SEND register.
373 */
374 REG_UPDATE(DP_GSP11_CNTL,
375 DP_SEC_GSP11_ENABLE, 1);
376 REG_UPDATE(DP_SEC_CNTL,
377 DP_SEC_STREAM_ENABLE, 1);
378 } else {
379 /* Disable Generic Stream Packet 11 (GSP) transmission */
380 REG_UPDATE(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, 0);
381 REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP11_PPS, 0);
382 }
383 }
384
385
386 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state
387 * into a dcn_dsc_state struct.
388 */
enc3_read_state(struct stream_encoder * enc,struct enc_state * s)389 static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s)
390 {
391 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
392
393 //if dsc is enabled, continue to read
394 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode);
395 if (s->dsc_mode) {
396 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width);
397 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_LINE_NUM, &s->sec_gsp_pps_line_num);
398
399 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference);
400 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num);
401
402 REG_GET(DP_GSP11_CNTL, DP_SEC_GSP11_ENABLE, &s->sec_gsp_pps_enable);
403 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable);
404 }
405 }
406
enc3_stream_encoder_update_dp_info_packets_sdp_line_num(struct stream_encoder * enc,struct encoder_info_frame * info_frame)407 void enc3_stream_encoder_update_dp_info_packets_sdp_line_num(
408 struct stream_encoder *enc,
409 struct encoder_info_frame *info_frame)
410 {
411 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
412
413 if (info_frame->adaptive_sync.valid == true &&
414 info_frame->sdp_line_num.adaptive_sync_line_num_valid == true) {
415 //00: REFER_TO_DP_SOF, 01: REFER_TO_OTG_SOF
416 REG_UPDATE(DP_SEC_CNTL1, DP_SEC_GSP5_LINE_REFERENCE, 1);
417
418 REG_UPDATE(DP_SEC_CNTL5, DP_SEC_GSP5_LINE_NUM,
419 info_frame->sdp_line_num.adaptive_sync_line_num);
420 }
421 }
422
enc3_stream_encoder_update_dp_info_packets(struct stream_encoder * enc,const struct encoder_info_frame * info_frame)423 void enc3_stream_encoder_update_dp_info_packets(
424 struct stream_encoder *enc,
425 const struct encoder_info_frame *info_frame)
426 {
427 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
428 uint32_t value = 0;
429 uint32_t dmdata_packet_enabled = 0;
430
431 if (info_frame->vsc.valid) {
432 enc->vpg->funcs->update_generic_info_packet(
433 enc->vpg,
434 0, /* packetIndex */
435 &info_frame->vsc,
436 true);
437 }
438 /* TODO: VSC SDP at packetIndex 1 should be restricted only if PSR-SU on.
439 * There should have another Infopacket type (e.g. vsc_psrsu) for PSR_SU.
440 * In addition, currently the driver check the valid bit then update and
441 * send the corresponding Infopacket. For PSR-SU, the SDP only be sent
442 * while entering PSR-SU mode. So we need another parameter(e.g. send)
443 * in dc_info_packet to indicate which infopacket should be enabled by
444 * default here.
445 */
446 if (info_frame->vsc.valid) {
447 enc->vpg->funcs->update_generic_info_packet(
448 enc->vpg,
449 1, /* packetIndex */
450 &info_frame->vsc,
451 true);
452 }
453 if (info_frame->spd.valid) {
454 enc->vpg->funcs->update_generic_info_packet(
455 enc->vpg,
456 2, /* packetIndex */
457 &info_frame->spd,
458 true);
459 }
460 if (info_frame->hdrsmd.valid) {
461 enc->vpg->funcs->update_generic_info_packet(
462 enc->vpg,
463 3, /* packetIndex */
464 &info_frame->hdrsmd,
465 true);
466 }
467 /* packetIndex 4 is used for send immediate sdp message, and please
468 * use other packetIndex (such as 5,6) for other info packet
469 */
470
471 if (info_frame->adaptive_sync.valid)
472 enc->vpg->funcs->update_generic_info_packet(
473 enc->vpg,
474 5, /* packetIndex */
475 &info_frame->adaptive_sync,
476 true);
477
478 /* enable/disable transmission of packet(s).
479 * If enabled, packet transmission begins on the next frame
480 */
481 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid);
482 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid);
483 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid);
484 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, info_frame->adaptive_sync.valid);
485
486 /* This bit is the master enable bit.
487 * When enabling secondary stream engine,
488 * this master bit must also be set.
489 * This register shared with audio info frame.
490 * Therefore we need to enable master bit
491 * if at least on of the fields is not 0
492 */
493 value = REG_READ(DP_SEC_CNTL);
494 if (value)
495 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
496
497 /* check if dynamic metadata packet transmission is enabled */
498 REG_GET(DP_SEC_METADATA_TRANSMISSION,
499 DP_SEC_METADATA_PACKET_ENABLE, &dmdata_packet_enabled);
500
501 if (dmdata_packet_enabled)
502 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
503 }
504
enc3_dp_set_odm_combine(struct stream_encoder * enc,bool odm_combine)505 static void enc3_dp_set_odm_combine(
506 struct stream_encoder *enc,
507 bool odm_combine)
508 {
509 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
510
511 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine);
512 }
513
514 /* setup stream encoder in dvi mode */
enc3_stream_encoder_dvi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,bool is_dual_link)515 static void enc3_stream_encoder_dvi_set_stream_attribute(
516 struct stream_encoder *enc,
517 struct dc_crtc_timing *crtc_timing,
518 bool is_dual_link)
519 {
520 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
521
522 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
523 struct bp_encoder_control cntl = {0};
524
525 cntl.action = ENCODER_CONTROL_SETUP;
526 cntl.engine_id = enc1->base.id;
527 cntl.signal = is_dual_link ?
528 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK;
529 cntl.enable_dp_audio = false;
530 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10;
531 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR;
532
533 if (enc1->base.bp->funcs->encoder_control(
534 enc1->base.bp, &cntl) != BP_RESULT_OK)
535 return;
536
537 } else {
538
539 //Set pattern for clock channel, default vlue 0x63 does not work
540 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
541
542 //DIG_BE_TMDS_DVI_MODE : TMDS-DVI mode is already set in link_encoder_setup
543
544 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
545
546 /* set DIG_START to 0x1 to reset FIFO */
547 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
548 udelay(1);
549
550 /* write 0 to take the FIFO out of reset */
551 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
552 udelay(1);
553 }
554
555 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB);
556 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888);
557 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
558 }
559
560 /* setup stream encoder in hdmi mode */
enc3_stream_encoder_hdmi_set_stream_attribute(struct stream_encoder * enc,struct dc_crtc_timing * crtc_timing,int actual_pix_clk_khz,bool enable_audio)561 static void enc3_stream_encoder_hdmi_set_stream_attribute(
562 struct stream_encoder *enc,
563 struct dc_crtc_timing *crtc_timing,
564 int actual_pix_clk_khz,
565 bool enable_audio)
566 {
567 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
568
569 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
570 struct bp_encoder_control cntl = {0};
571
572 cntl.action = ENCODER_CONTROL_SETUP;
573 cntl.engine_id = enc1->base.id;
574 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A;
575 cntl.enable_dp_audio = enable_audio;
576 cntl.pixel_clock = actual_pix_clk_khz;
577 cntl.lanes_number = LANE_COUNT_FOUR;
578
579 if (enc1->base.bp->funcs->encoder_control(
580 enc1->base.bp, &cntl) != BP_RESULT_OK)
581 return;
582
583 } else {
584
585 //Set pattern for clock channel, default vlue 0x63 does not work
586 REG_UPDATE(DIG_CLOCK_PATTERN, DIG_CLOCK_PATTERN, 0x1F);
587
588 //DIG_BE_TMDS_HDMI_MODE : TMDS-HDMI mode is already set in link_encoder_setup
589
590 //DIG_SOURCE_SELECT is already set in dig_connect_to_otg
591
592 /* set DIG_START to 0x1 to reset FIFO */
593 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
594 udelay(1);
595
596 /* write 0 to take the FIFO out of reset */
597 REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
598 udelay(1);
599 }
600
601 /* Configure pixel encoding */
602 enc1_stream_encoder_set_stream_attribute_helper(enc1, crtc_timing);
603
604 /* setup HDMI engine */
605 REG_UPDATE_6(HDMI_CONTROL,
606 HDMI_PACKET_GEN_VERSION, 1,
607 HDMI_KEEPOUT_MODE, 1,
608 HDMI_DEEP_COLOR_ENABLE, 0,
609 HDMI_DATA_SCRAMBLE_EN, 0,
610 HDMI_NO_EXTRA_NULL_PACKET_FILLED, 1,
611 HDMI_CLOCK_CHANNEL_RATE, 0);
612
613 /* Configure color depth */
614 switch (crtc_timing->display_color_depth) {
615 case COLOR_DEPTH_888:
616 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
617 break;
618 case COLOR_DEPTH_101010:
619 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
620 REG_UPDATE_2(HDMI_CONTROL,
621 HDMI_DEEP_COLOR_DEPTH, 1,
622 HDMI_DEEP_COLOR_ENABLE, 0);
623 } else {
624 REG_UPDATE_2(HDMI_CONTROL,
625 HDMI_DEEP_COLOR_DEPTH, 1,
626 HDMI_DEEP_COLOR_ENABLE, 1);
627 }
628 break;
629 case COLOR_DEPTH_121212:
630 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) {
631 REG_UPDATE_2(HDMI_CONTROL,
632 HDMI_DEEP_COLOR_DEPTH, 2,
633 HDMI_DEEP_COLOR_ENABLE, 0);
634 } else {
635 REG_UPDATE_2(HDMI_CONTROL,
636 HDMI_DEEP_COLOR_DEPTH, 2,
637 HDMI_DEEP_COLOR_ENABLE, 1);
638 }
639 break;
640 case COLOR_DEPTH_161616:
641 REG_UPDATE_2(HDMI_CONTROL,
642 HDMI_DEEP_COLOR_DEPTH, 3,
643 HDMI_DEEP_COLOR_ENABLE, 1);
644 break;
645 default:
646 break;
647 }
648
649 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) {
650 /* enable HDMI data scrambler
651 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M
652 * Clock channel frequency is 1/4 of character rate.
653 */
654 REG_UPDATE_2(HDMI_CONTROL,
655 HDMI_DATA_SCRAMBLE_EN, 1,
656 HDMI_CLOCK_CHANNEL_RATE, 1);
657 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) {
658
659 /* TODO: New feature for DCE11, still need to implement */
660
661 /* enable HDMI data scrambler
662 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE
663 * Clock channel frequency is the same
664 * as character rate
665 */
666 REG_UPDATE_2(HDMI_CONTROL,
667 HDMI_DATA_SCRAMBLE_EN, 1,
668 HDMI_CLOCK_CHANNEL_RATE, 0);
669 }
670
671
672 /* Enable transmission of General Control packet on every frame */
673 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL,
674 HDMI_GC_CONT, 1,
675 HDMI_GC_SEND, 1,
676 HDMI_NULL_SEND, 1);
677
678 /* Disable Audio Content Protection packet transmission */
679 REG_UPDATE(HDMI_VBI_PACKET_CONTROL, HDMI_ACP_SEND, 0);
680
681 /* following belongs to audio */
682 /* Enable Audio InfoFrame packet transmission. */
683 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
684
685 /* update double-buffered AUDIO_INFO registers immediately */
686 ASSERT (enc->afmt);
687 enc->afmt->funcs->audio_info_immediate_update(enc->afmt);
688
689 /* Select line number on which to send Audio InfoFrame packets */
690 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE,
691 VBI_LINE_0 + 2);
692
693 /* set HDMI GC AVMUTE */
694 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0);
695 }
696
enc3_audio_mute_control(struct stream_encoder * enc,bool mute)697 void enc3_audio_mute_control(
698 struct stream_encoder *enc,
699 bool mute)
700 {
701 ASSERT (enc->afmt);
702 enc->afmt->funcs->audio_mute_control(enc->afmt, mute);
703 }
704
enc3_se_dp_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info)705 void enc3_se_dp_audio_setup(
706 struct stream_encoder *enc,
707 unsigned int az_inst,
708 struct audio_info *info)
709 {
710 ASSERT (enc->afmt);
711 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
712 }
713
714 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000
715 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1
716
enc3_se_setup_dp_audio(struct stream_encoder * enc)717 static void enc3_se_setup_dp_audio(
718 struct stream_encoder *enc)
719 {
720 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
721
722 /* --- DP Audio packet configurations --- */
723
724 /* ATP Configuration */
725 REG_SET(DP_SEC_AUD_N, 0,
726 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT);
727
728 /* Async/auto-calc timestamp mode */
729 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE,
730 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC);
731
732 ASSERT (enc->afmt);
733 enc->afmt->funcs->setup_dp_audio(enc->afmt);
734 }
735
enc3_se_dp_audio_enable(struct stream_encoder * enc)736 void enc3_se_dp_audio_enable(
737 struct stream_encoder *enc)
738 {
739 enc1_se_enable_audio_clock(enc, true);
740 enc3_se_setup_dp_audio(enc);
741 enc1_se_enable_dp_audio(enc);
742 }
743
enc3_se_setup_hdmi_audio(struct stream_encoder * enc,const struct audio_crtc_info * crtc_info)744 static void enc3_se_setup_hdmi_audio(
745 struct stream_encoder *enc,
746 const struct audio_crtc_info *crtc_info)
747 {
748 struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
749
750 struct audio_clock_info audio_clock_info = {0};
751
752 /* Setup audio in AFMT - program AFMT block associated with DIO */
753 ASSERT (enc->afmt);
754 enc->afmt->funcs->setup_hdmi_audio(enc->afmt);
755
756 /* HDMI_AUDIO_PACKET_CONTROL */
757 REG_UPDATE(HDMI_AUDIO_PACKET_CONTROL,
758 HDMI_AUDIO_DELAY_EN, 1);
759
760 /* HDMI_ACR_PACKET_CONTROL */
761 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL,
762 HDMI_ACR_AUTO_SEND, 1,
763 HDMI_ACR_SOURCE, 0,
764 HDMI_ACR_AUDIO_PRIORITY, 0);
765
766 /* Program audio clock sample/regeneration parameters */
767 get_audio_clock_info(crtc_info->color_depth,
768 crtc_info->requested_pixel_clock_100Hz,
769 crtc_info->calculated_pixel_clock_100Hz,
770 &audio_clock_info);
771 DC_LOG_HW_AUDIO(
772 "\n%s:Input::requested_pixel_clock_100Hz = %d" \
773 "calculated_pixel_clock_100Hz = %d \n", __func__, \
774 crtc_info->requested_pixel_clock_100Hz, \
775 crtc_info->calculated_pixel_clock_100Hz);
776
777 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
778 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
779
780 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
781 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
782
783 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
784 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
785
786 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
787 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
788
789 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
790 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
791
792 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
793 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
794
795 /* Video driver cannot know in advance which sample rate will
796 * be used by HD Audio driver
797 * HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
798 * programmed below in interruppt callback
799 */
800 }
801
enc3_se_hdmi_audio_setup(struct stream_encoder * enc,unsigned int az_inst,struct audio_info * info,struct audio_crtc_info * audio_crtc_info)802 void enc3_se_hdmi_audio_setup(
803 struct stream_encoder *enc,
804 unsigned int az_inst,
805 struct audio_info *info,
806 struct audio_crtc_info *audio_crtc_info)
807 {
808 enc1_se_enable_audio_clock(enc, true);
809 enc3_se_setup_hdmi_audio(enc, audio_crtc_info);
810 ASSERT (enc->afmt);
811 enc->afmt->funcs->se_audio_setup(enc->afmt, az_inst, info);
812 }
813
814
815 static const struct stream_encoder_funcs dcn30_str_enc_funcs = {
816 .dp_set_odm_combine =
817 enc3_dp_set_odm_combine,
818 .dp_set_stream_attribute =
819 enc2_stream_encoder_dp_set_stream_attribute,
820 .hdmi_set_stream_attribute =
821 enc3_stream_encoder_hdmi_set_stream_attribute,
822 .dvi_set_stream_attribute =
823 enc3_stream_encoder_dvi_set_stream_attribute,
824 .set_throttled_vcp_size =
825 enc1_stream_encoder_set_throttled_vcp_size,
826 .update_hdmi_info_packets =
827 enc3_stream_encoder_update_hdmi_info_packets,
828 .stop_hdmi_info_packets =
829 enc3_stream_encoder_stop_hdmi_info_packets,
830 .update_dp_info_packets_sdp_line_num =
831 enc3_stream_encoder_update_dp_info_packets_sdp_line_num,
832 .update_dp_info_packets =
833 enc3_stream_encoder_update_dp_info_packets,
834 .stop_dp_info_packets =
835 enc1_stream_encoder_stop_dp_info_packets,
836 .dp_blank =
837 enc1_stream_encoder_dp_blank,
838 .dp_unblank =
839 enc2_stream_encoder_dp_unblank,
840 .audio_mute_control = enc3_audio_mute_control,
841
842 .dp_audio_setup = enc3_se_dp_audio_setup,
843 .dp_audio_enable = enc3_se_dp_audio_enable,
844 .dp_audio_disable = enc1_se_dp_audio_disable,
845
846 .hdmi_audio_setup = enc3_se_hdmi_audio_setup,
847 .hdmi_audio_disable = enc1_se_hdmi_audio_disable,
848 .setup_stereo_sync = enc1_setup_stereo_sync,
849 .set_avmute = enc1_stream_encoder_set_avmute,
850 .dig_connect_to_otg = enc1_dig_connect_to_otg,
851 .dig_source_otg = enc1_dig_source_otg,
852
853 .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format,
854
855 .enc_read_state = enc3_read_state,
856 .dp_set_dsc_config = enc3_dp_set_dsc_config,
857 .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet,
858 .set_dynamic_metadata = enc2_set_dynamic_metadata,
859 .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute,
860
861 .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level,
862 };
863
dcn30_dio_stream_encoder_construct(struct dcn10_stream_encoder * enc1,struct dc_context * ctx,struct dc_bios * bp,enum engine_id eng_id,struct vpg * vpg,struct afmt * afmt,const struct dcn10_stream_enc_registers * regs,const struct dcn10_stream_encoder_shift * se_shift,const struct dcn10_stream_encoder_mask * se_mask)864 void dcn30_dio_stream_encoder_construct(
865 struct dcn10_stream_encoder *enc1,
866 struct dc_context *ctx,
867 struct dc_bios *bp,
868 enum engine_id eng_id,
869 struct vpg *vpg,
870 struct afmt *afmt,
871 const struct dcn10_stream_enc_registers *regs,
872 const struct dcn10_stream_encoder_shift *se_shift,
873 const struct dcn10_stream_encoder_mask *se_mask)
874 {
875 enc1->base.funcs = &dcn30_str_enc_funcs;
876 enc1->base.ctx = ctx;
877 enc1->base.id = eng_id;
878 enc1->base.bp = bp;
879 enc1->base.vpg = vpg;
880 enc1->base.afmt = afmt;
881 enc1->regs = regs;
882 enc1->se_shift = se_shift;
883 enc1->se_mask = se_mask;
884 enc1->base.stream_enc_inst = vpg->inst;
885 }
886
887