1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 // header file of functions being implemented
27 #include "dcn32_resource.h"
28 #include "dcn20/dcn20_resource.h"
29 #include "dml/dcn32/display_mode_vba_util_32.h"
30
is_dual_plane(enum surface_pixel_format format)31 static bool is_dual_plane(enum surface_pixel_format format)
32 {
33 return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
34 }
35
36
dcn32_helper_mall_bytes_to_ways(struct dc * dc,uint32_t total_size_in_mall_bytes)37 uint32_t dcn32_helper_mall_bytes_to_ways(
38 struct dc *dc,
39 uint32_t total_size_in_mall_bytes)
40 {
41 uint32_t cache_lines_used, lines_per_way, total_cache_lines, num_ways;
42
43 /* add 2 lines for worst case alignment */
44 cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2;
45
46 total_cache_lines = dc->caps.max_cab_allocation_bytes / dc->caps.cache_line_size;
47 lines_per_way = total_cache_lines / dc->caps.cache_num_ways;
48 num_ways = cache_lines_used / lines_per_way;
49 if (cache_lines_used % lines_per_way > 0)
50 num_ways++;
51
52 return num_ways;
53 }
54
dcn32_helper_calculate_mall_bytes_for_cursor(struct dc * dc,struct pipe_ctx * pipe_ctx,bool ignore_cursor_buf)55 uint32_t dcn32_helper_calculate_mall_bytes_for_cursor(
56 struct dc *dc,
57 struct pipe_ctx *pipe_ctx,
58 bool ignore_cursor_buf)
59 {
60 struct hubp *hubp = pipe_ctx->plane_res.hubp;
61 uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height;
62 uint32_t cursor_bpp = 4;
63 uint32_t cursor_mall_size_bytes = 0;
64
65 switch (pipe_ctx->stream->cursor_attributes.color_format) {
66 case CURSOR_MODE_MONO:
67 cursor_size /= 2;
68 cursor_bpp = 4;
69 break;
70 case CURSOR_MODE_COLOR_1BIT_AND:
71 case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
72 case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
73 cursor_size *= 4;
74 cursor_bpp = 4;
75 break;
76
77 case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
78 case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
79 cursor_size *= 8;
80 cursor_bpp = 8;
81 break;
82 }
83
84 /* only count if cursor is enabled, and if additional allocation needed outside of the
85 * DCN cursor buffer
86 */
87 if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf ||
88 cursor_size > 16384)) {
89 /* cursor_num_mblk = CEILING(num_cursors*cursor_width*cursor_width*cursor_Bpe/mblk_bytes, 1)
90 * Note: add 1 mblk in case of cursor misalignment
91 */
92 cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) /
93 DCN3_2_MALL_MBLK_SIZE_BYTES + 1) * DCN3_2_MALL_MBLK_SIZE_BYTES;
94 }
95
96 return cursor_mall_size_bytes;
97 }
98
99 /**
100 * ********************************************************************************************
101 * dcn32_helper_calculate_num_ways_for_subvp: Calculate number of ways needed for SubVP
102 *
103 * Gets total allocation required for the phantom viewport calculated by DML in bytes and
104 * converts to number of cache ways.
105 *
106 * @param [in] dc: current dc state
107 * @param [in] context: new dc state
108 *
109 * @return: number of ways required for SubVP
110 *
111 * ********************************************************************************************
112 */
dcn32_helper_calculate_num_ways_for_subvp(struct dc * dc,struct dc_state * context)113 uint32_t dcn32_helper_calculate_num_ways_for_subvp(
114 struct dc *dc,
115 struct dc_state *context)
116 {
117 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) {
118 if (dc->debug.force_subvp_num_ways) {
119 return dc->debug.force_subvp_num_ways;
120 } else {
121 return dcn32_helper_mall_bytes_to_ways(dc, context->bw_ctx.bw.dcn.mall_subvp_size_bytes);
122 }
123 } else {
124 return 0;
125 }
126 }
127
dcn32_merge_pipes_for_subvp(struct dc * dc,struct dc_state * context)128 void dcn32_merge_pipes_for_subvp(struct dc *dc,
129 struct dc_state *context)
130 {
131 uint32_t i;
132
133 /* merge pipes if necessary */
134 for (i = 0; i < dc->res_pool->pipe_count; i++) {
135 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
136
137 // For now merge all pipes for SubVP since pipe split case isn't supported yet
138
139 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
140 if (pipe->prev_odm_pipe) {
141 /*split off odm pipe*/
142 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
143 if (pipe->next_odm_pipe)
144 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
145
146 pipe->bottom_pipe = NULL;
147 pipe->next_odm_pipe = NULL;
148 pipe->plane_state = NULL;
149 pipe->stream = NULL;
150 pipe->top_pipe = NULL;
151 pipe->prev_odm_pipe = NULL;
152 if (pipe->stream_res.dsc)
153 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
154 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
155 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
156 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
157 struct pipe_ctx *top_pipe = pipe->top_pipe;
158 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
159
160 top_pipe->bottom_pipe = bottom_pipe;
161 if (bottom_pipe)
162 bottom_pipe->top_pipe = top_pipe;
163
164 pipe->top_pipe = NULL;
165 pipe->bottom_pipe = NULL;
166 pipe->plane_state = NULL;
167 pipe->stream = NULL;
168 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
169 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
170 }
171 }
172 }
173
dcn32_all_pipes_have_stream_and_plane(struct dc * dc,struct dc_state * context)174 bool dcn32_all_pipes_have_stream_and_plane(struct dc *dc,
175 struct dc_state *context)
176 {
177 uint32_t i;
178
179 for (i = 0; i < dc->res_pool->pipe_count; i++) {
180 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
181
182 if (!pipe->stream)
183 continue;
184
185 if (!pipe->plane_state)
186 return false;
187 }
188 return true;
189 }
190
dcn32_subvp_in_use(struct dc * dc,struct dc_state * context)191 bool dcn32_subvp_in_use(struct dc *dc,
192 struct dc_state *context)
193 {
194 uint32_t i;
195
196 for (i = 0; i < dc->res_pool->pipe_count; i++) {
197 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
198
199 if (pipe->stream && pipe->stream->mall_stream_config.type != SUBVP_NONE)
200 return true;
201 }
202 return false;
203 }
204
dcn32_mpo_in_use(struct dc_state * context)205 bool dcn32_mpo_in_use(struct dc_state *context)
206 {
207 uint32_t i;
208
209 for (i = 0; i < context->stream_count; i++) {
210 if (context->stream_status[i].plane_count > 1)
211 return true;
212 }
213 return false;
214 }
215
216
dcn32_any_surfaces_rotated(struct dc * dc,struct dc_state * context)217 bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context)
218 {
219 uint32_t i;
220
221 for (i = 0; i < dc->res_pool->pipe_count; i++) {
222 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
223
224 if (!pipe->stream)
225 continue;
226
227 if (pipe->plane_state && pipe->plane_state->rotation != ROTATION_ANGLE_0)
228 return true;
229 }
230 return false;
231 }
232
dcn32_is_center_timing(struct pipe_ctx * pipe)233 bool dcn32_is_center_timing(struct pipe_ctx *pipe)
234 {
235 bool is_center_timing = false;
236
237 if (pipe->stream) {
238 if (pipe->stream->timing.v_addressable != pipe->stream->dst.height ||
239 pipe->stream->timing.v_addressable != pipe->stream->src.height) {
240 is_center_timing = true;
241 }
242 }
243
244 if (pipe->plane_state) {
245 if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&
246 pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {
247 is_center_timing = true;
248 }
249 }
250
251 return is_center_timing;
252 }
253
dcn32_is_psr_capable(struct pipe_ctx * pipe)254 bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
255 {
256 bool psr_capable = false;
257
258 if (pipe->stream && pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
259 psr_capable = true;
260 }
261 return psr_capable;
262 }
263
264 /**
265 * *******************************************************************************************
266 * dcn32_determine_det_override: Determine DET allocation for each pipe
267 *
268 * This function determines how much DET to allocate for each pipe. The total number of
269 * DET segments will be split equally among each of the streams, and after that the DET
270 * segments per stream will be split equally among the planes for the given stream.
271 *
272 * If there is a plane that's driven by more than 1 pipe (i.e. pipe split), then the
273 * number of DET for that given plane will be split among the pipes driving that plane.
274 *
275 *
276 * High level algorithm:
277 * 1. Split total DET among number of streams
278 * 2. For each stream, split DET among the planes
279 * 3. For each plane, check if there is a pipe split. If yes, split the DET allocation
280 * among those pipes.
281 * 4. Assign the DET override to the DML pipes.
282 *
283 * @param [in]: dc: Current DC state
284 * @param [in]: context: New DC state to be programmed
285 * @param [in]: pipes: Array of DML pipes
286 *
287 * @return: void
288 *
289 * *******************************************************************************************
290 */
dcn32_determine_det_override(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes)291 void dcn32_determine_det_override(struct dc *dc,
292 struct dc_state *context,
293 display_e2e_pipe_params_st *pipes)
294 {
295 uint32_t i, j, k;
296 uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0};
297 uint8_t pipe_counted[MAX_PIPES] = {0};
298 uint8_t pipe_cnt = 0;
299 struct dc_plane_state *current_plane = NULL;
300 uint8_t stream_count = 0;
301
302 for (i = 0; i < context->stream_count; i++) {
303 /* Don't count SubVP streams for DET allocation */
304 if (context->streams[i]->mall_stream_config.type != SUBVP_PHANTOM) {
305 stream_count++;
306 }
307 }
308
309 if (stream_count > 0) {
310 stream_segments = 18 / stream_count;
311 for (i = 0; i < context->stream_count; i++) {
312 if (context->streams[i]->mall_stream_config.type == SUBVP_PHANTOM)
313 continue;
314 if (context->stream_status[i].plane_count > 0)
315 plane_segments = stream_segments / context->stream_status[i].plane_count;
316 else
317 plane_segments = stream_segments;
318 for (j = 0; j < dc->res_pool->pipe_count; j++) {
319 pipe_plane_count = 0;
320 if (context->res_ctx.pipe_ctx[j].stream == context->streams[i] &&
321 pipe_counted[j] != 1) {
322 /* Note: pipe_plane_count indicates the number of pipes to be used for a
323 * given plane. e.g. pipe_plane_count = 1 means single pipe (i.e. not split),
324 * pipe_plane_count = 2 means 2:1 split, etc.
325 */
326 pipe_plane_count++;
327 pipe_counted[j] = 1;
328 current_plane = context->res_ctx.pipe_ctx[j].plane_state;
329 for (k = 0; k < dc->res_pool->pipe_count; k++) {
330 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
331 context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
332 pipe_plane_count++;
333 pipe_counted[k] = 1;
334 }
335 }
336
337 pipe_segments[j] = plane_segments / pipe_plane_count;
338 for (k = 0; k < dc->res_pool->pipe_count; k++) {
339 if (k != j && context->res_ctx.pipe_ctx[k].stream == context->streams[i] &&
340 context->res_ctx.pipe_ctx[k].plane_state == current_plane) {
341 pipe_segments[k] = plane_segments / pipe_plane_count;
342 }
343 }
344 }
345 }
346 }
347
348 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
349 if (!context->res_ctx.pipe_ctx[i].stream)
350 continue;
351 pipes[pipe_cnt].pipe.src.det_size_override = pipe_segments[i] * DCN3_2_DET_SEG_SIZE;
352 pipe_cnt++;
353 }
354 } else {
355 for (i = 0; i < dc->res_pool->pipe_count; i++)
356 pipes[i].pipe.src.det_size_override = 4 * DCN3_2_DET_SEG_SIZE; //DCN3_2_DEFAULT_DET_SIZE
357 }
358 }
359
dcn32_set_det_allocations(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes)360 void dcn32_set_det_allocations(struct dc *dc, struct dc_state *context,
361 display_e2e_pipe_params_st *pipes)
362 {
363 int i, pipe_cnt;
364 struct resource_context *res_ctx = &context->res_ctx;
365 struct pipe_ctx *pipe;
366 bool disable_unbounded_requesting = dc->debug.disable_z9_mpc || dc->debug.disable_unbounded_requesting;
367
368 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
369
370 if (!res_ctx->pipe_ctx[i].stream)
371 continue;
372
373 pipe = &res_ctx->pipe_ctx[i];
374 pipe_cnt++;
375 }
376
377 /* For DET allocation, we don't want to use DML policy (not optimal for utilizing all
378 * the DET available for each pipe). Use the DET override input to maintain our driver
379 * policy.
380 */
381 if (pipe_cnt == 1) {
382 pipes[0].pipe.src.det_size_override = DCN3_2_MAX_DET_SIZE;
383 if (pipe->plane_state && !disable_unbounded_requesting && pipe->plane_state->tiling_info.gfx9.swizzle != DC_SW_LINEAR) {
384 if (!is_dual_plane(pipe->plane_state->format)) {
385 pipes[0].pipe.src.det_size_override = DCN3_2_DEFAULT_DET_SIZE;
386 pipes[0].pipe.src.unbounded_req_mode = true;
387 if (pipe->plane_state->src_rect.width >= 5120 &&
388 pipe->plane_state->src_rect.height >= 2880)
389 pipes[0].pipe.src.det_size_override = 320; // 5K or higher
390 }
391 }
392 } else
393 dcn32_determine_det_override(dc, context, pipes);
394 }
395
396 /**
397 * *******************************************************************************************
398 * dcn32_save_mall_state: Save MALL (SubVP) state for fast validation cases
399 *
400 * This function saves the MALL (SubVP) case for fast validation cases. For fast validation,
401 * there are situations where a shallow copy of the dc->current_state is created for the
402 * validation. In this case we want to save and restore the mall config because we always
403 * teardown subvp at the beginning of validation (and don't attempt to add it back if it's
404 * fast validation). If we don't restore the subvp config in cases of fast validation +
405 * shallow copy of the dc->current_state, the dc->current_state will have a partially
406 * removed subvp state when we did not intend to remove it.
407 *
408 * NOTE: This function ONLY works if the streams are not moved to a different pipe in the
409 * validation. We don't expect this to happen in fast_validation=1 cases.
410 *
411 * @param [in]: dc: Current DC state
412 * @param [in]: context: New DC state to be programmed
413 * @param [out]: temp_config: struct used to cache the existing MALL state
414 *
415 * @return: void
416 *
417 * *******************************************************************************************
418 */
dcn32_save_mall_state(struct dc * dc,struct dc_state * context,struct mall_temp_config * temp_config)419 void dcn32_save_mall_state(struct dc *dc,
420 struct dc_state *context,
421 struct mall_temp_config *temp_config)
422 {
423 uint32_t i;
424
425 for (i = 0; i < dc->res_pool->pipe_count; i++) {
426 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
427
428 if (pipe->stream)
429 temp_config->mall_stream_config[i] = pipe->stream->mall_stream_config;
430
431 if (pipe->plane_state)
432 temp_config->is_phantom_plane[i] = pipe->plane_state->is_phantom;
433 }
434 }
435
436 /**
437 * *******************************************************************************************
438 * dcn32_restore_mall_state: Restore MALL (SubVP) state for fast validation cases
439 *
440 * Restore the MALL state based on the previously saved state from dcn32_save_mall_state
441 *
442 * @param [in]: dc: Current DC state
443 * @param [in/out]: context: New DC state to be programmed, restore MALL state into here
444 * @param [in]: temp_config: struct that has the cached MALL state
445 *
446 * @return: void
447 *
448 * *******************************************************************************************
449 */
dcn32_restore_mall_state(struct dc * dc,struct dc_state * context,struct mall_temp_config * temp_config)450 void dcn32_restore_mall_state(struct dc *dc,
451 struct dc_state *context,
452 struct mall_temp_config *temp_config)
453 {
454 uint32_t i;
455
456 for (i = 0; i < dc->res_pool->pipe_count; i++) {
457 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
458
459 if (pipe->stream)
460 pipe->stream->mall_stream_config = temp_config->mall_stream_config[i];
461
462 if (pipe->plane_state)
463 pipe->plane_state->is_phantom = temp_config->is_phantom_plane[i];
464 }
465 }
466