1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 */
9
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <env.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <memalign.h>
17 #include <miiphy.h>
18 #include <net.h>
19 #include <netdev.h>
20 #include <asm/cache.h>
21 #include <asm/global_data.h>
22 #include <linux/delay.h>
23 #include <power/regulator.h>
24
25 #include <asm/io.h>
26 #include <linux/errno.h>
27 #include <linux/compiler.h>
28
29 #include <asm/arch/clock.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/mach-imx/sys_proto.h>
32 #include <asm-generic/gpio.h>
33
34 #include "fec_mxc.h"
35 #include <eth_phy.h>
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 /*
40 * Timeout the transfer after 5 mS. This is usually a bit more, since
41 * the code in the tightloops this timeout is used in adds some overhead.
42 */
43 #define FEC_XFER_TIMEOUT 5000
44
45 /*
46 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
47 * 64-byte alignment in the DMA RX FEC buffer.
48 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
49 * satisfies the alignment on other SoCs (32-bytes)
50 */
51 #define FEC_DMA_RX_MINALIGN 64
52
53 #ifndef CONFIG_MII
54 #error "CONFIG_MII has to be defined!"
55 #endif
56
57 #ifndef CONFIG_FEC_XCV_TYPE
58 #define CONFIG_FEC_XCV_TYPE MII100
59 #endif
60
61 /*
62 * The i.MX28 operates with packets in big endian. We need to swap them before
63 * sending and after receiving.
64 */
65 #ifdef CONFIG_MX28
66 #define CONFIG_FEC_MXC_SWAP_PACKET
67 #endif
68
69 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
70
71 /* Check various alignment issues at compile time */
72 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
73 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
74 #endif
75
76 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
77 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
78 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
79 #endif
80
81 #undef DEBUG
82
83 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet(uint32_t * packet,int length)84 static void swap_packet(uint32_t *packet, int length)
85 {
86 int i;
87
88 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
89 packet[i] = __swab32(packet[i]);
90 }
91 #endif
92
93 /* MII-interface related functions */
fec_mdio_read(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr)94 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
95 uint8_t regaddr)
96 {
97 uint32_t reg; /* convenient holder for the PHY register */
98 uint32_t phy; /* convenient holder for the PHY */
99 uint32_t start;
100 int val;
101
102 /*
103 * reading from any PHY's register is done by properly
104 * programming the FEC's MII data register.
105 */
106 writel(FEC_IEVENT_MII, ð->ievent);
107 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
108 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
109
110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
111 phy | reg, ð->mii_data);
112
113 /* wait for the related interrupt */
114 start = get_timer(0);
115 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
116 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
117 printf("Read MDIO failed...\n");
118 return -1;
119 }
120 }
121
122 /* clear mii interrupt bit */
123 writel(FEC_IEVENT_MII, ð->ievent);
124
125 /* it's now safe to read the PHY's register */
126 val = (unsigned short)readl(ð->mii_data);
127 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
128 regaddr, val);
129 return val;
130 }
131
132 #ifndef imx_get_fecclk
imx_get_fecclk(void)133 u32 __weak imx_get_fecclk(void)
134 {
135 return 0;
136 }
137 #endif
138
fec_get_clk_rate(void * udev,int idx)139 static int fec_get_clk_rate(void *udev, int idx)
140 {
141 struct fec_priv *fec;
142 struct udevice *dev;
143 int ret;
144
145 if (IS_ENABLED(CONFIG_IMX8) ||
146 CONFIG_IS_ENABLED(CLK_CCF)) {
147 dev = udev;
148 if (!dev) {
149 ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev);
150 if (ret < 0) {
151 debug("Can't get FEC udev: %d\n", ret);
152 return ret;
153 }
154 }
155
156 fec = dev_get_priv(dev);
157 if (fec)
158 return fec->clk_rate;
159
160 return -EINVAL;
161 } else {
162 return imx_get_fecclk();
163 }
164 }
165
fec_mii_setspeed(struct ethernet_regs * eth)166 static void fec_mii_setspeed(struct ethernet_regs *eth)
167 {
168 /*
169 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
170 * and do not drop the Preamble.
171 *
172 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
173 * MII_SPEED) register that defines the MDIO output hold time. Earlier
174 * versions are RAZ there, so just ignore the difference and write the
175 * register always.
176 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
177 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
178 * output.
179 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
180 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
181 * holdtime cannot result in a value greater than 3.
182 */
183 u32 pclk;
184 u32 speed;
185 u32 hold;
186 int ret;
187
188 ret = fec_get_clk_rate(NULL, 0);
189 if (ret < 0) {
190 printf("Can't find FEC0 clk rate: %d\n", ret);
191 return;
192 }
193 pclk = ret;
194 speed = DIV_ROUND_UP(pclk, 5000000);
195 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
196
197 #ifdef FEC_QUIRK_ENET_MAC
198 speed--;
199 #endif
200 writel(speed << 1 | hold << 8, ð->mii_speed);
201 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
202 }
203
fec_mdio_write(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr,uint16_t data)204 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
205 uint8_t regaddr, uint16_t data)
206 {
207 uint32_t reg; /* convenient holder for the PHY register */
208 uint32_t phy; /* convenient holder for the PHY */
209 uint32_t start;
210
211 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
212 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
213
214 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
215 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
216
217 /* wait for the MII interrupt */
218 start = get_timer(0);
219 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
220 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
221 printf("Write MDIO failed...\n");
222 return -1;
223 }
224 }
225
226 /* clear MII interrupt bit */
227 writel(FEC_IEVENT_MII, ð->ievent);
228 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
229 regaddr, data);
230
231 return 0;
232 }
233
fec_phy_read(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr)234 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
235 int regaddr)
236 {
237 return fec_mdio_read(bus->priv, phyaddr, regaddr);
238 }
239
fec_phy_write(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr,u16 data)240 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
241 int regaddr, u16 data)
242 {
243 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
244 }
245
246 #ifndef CONFIG_PHYLIB
miiphy_restart_aneg(struct eth_device * dev)247 static int miiphy_restart_aneg(struct eth_device *dev)
248 {
249 int ret = 0;
250 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
251 struct fec_priv *fec = (struct fec_priv *)dev->priv;
252 struct ethernet_regs *eth = fec->bus->priv;
253
254 /*
255 * Wake up from sleep if necessary
256 * Reset PHY, then delay 300ns
257 */
258 #ifdef CONFIG_MX27
259 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
260 #endif
261 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
262 udelay(1000);
263
264 /* Set the auto-negotiation advertisement register bits */
265 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
266 LPA_100FULL | LPA_100HALF | LPA_10FULL |
267 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
268 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
269 BMCR_ANENABLE | BMCR_ANRESTART);
270
271 if (fec->mii_postcall)
272 ret = fec->mii_postcall(fec->phy_id);
273
274 #endif
275 return ret;
276 }
277
278 #ifndef CONFIG_FEC_FIXED_SPEED
miiphy_wait_aneg(struct eth_device * dev)279 static int miiphy_wait_aneg(struct eth_device *dev)
280 {
281 uint32_t start;
282 int status;
283 struct fec_priv *fec = (struct fec_priv *)dev->priv;
284 struct ethernet_regs *eth = fec->bus->priv;
285
286 /* Wait for AN completion */
287 start = get_timer(0);
288 do {
289 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
290 printf("%s: Autonegotiation timeout\n", dev->name);
291 return -1;
292 }
293
294 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
295 if (status < 0) {
296 printf("%s: Autonegotiation failed. status: %d\n",
297 dev->name, status);
298 return -1;
299 }
300 } while (!(status & BMSR_LSTATUS));
301
302 return 0;
303 }
304 #endif /* CONFIG_FEC_FIXED_SPEED */
305 #endif
306
fec_rx_task_enable(struct fec_priv * fec)307 static int fec_rx_task_enable(struct fec_priv *fec)
308 {
309 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
310 return 0;
311 }
312
fec_rx_task_disable(struct fec_priv * fec)313 static int fec_rx_task_disable(struct fec_priv *fec)
314 {
315 return 0;
316 }
317
fec_tx_task_enable(struct fec_priv * fec)318 static int fec_tx_task_enable(struct fec_priv *fec)
319 {
320 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
321 return 0;
322 }
323
fec_tx_task_disable(struct fec_priv * fec)324 static int fec_tx_task_disable(struct fec_priv *fec)
325 {
326 return 0;
327 }
328
329 /**
330 * Initialize receive task's buffer descriptors
331 * @param[in] fec all we know about the device yet
332 * @param[in] count receive buffer count to be allocated
333 * @param[in] dsize desired size of each receive buffer
334 * @return 0 on success
335 *
336 * Init all RX descriptors to default values.
337 */
fec_rbd_init(struct fec_priv * fec,int count,int dsize)338 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
339 {
340 uint32_t size;
341 ulong data;
342 int i;
343
344 /*
345 * Reload the RX descriptors with default values and wipe
346 * the RX buffers.
347 */
348 size = roundup(dsize, ARCH_DMA_MINALIGN);
349 for (i = 0; i < count; i++) {
350 data = fec->rbd_base[i].data_pointer;
351 memset((void *)data, 0, dsize);
352 flush_dcache_range(data, data + size);
353
354 fec->rbd_base[i].status = FEC_RBD_EMPTY;
355 fec->rbd_base[i].data_length = 0;
356 }
357
358 /* Mark the last RBD to close the ring. */
359 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
360 fec->rbd_index = 0;
361
362 flush_dcache_range((ulong)fec->rbd_base,
363 (ulong)fec->rbd_base + size);
364 }
365
366 /**
367 * Initialize transmit task's buffer descriptors
368 * @param[in] fec all we know about the device yet
369 *
370 * Transmit buffers are created externally. We only have to init the BDs here.\n
371 * Note: There is a race condition in the hardware. When only one BD is in
372 * use it must be marked with the WRAP bit to use it for every transmitt.
373 * This bit in combination with the READY bit results into double transmit
374 * of each data buffer. It seems the state machine checks READY earlier then
375 * resetting it after the first transfer.
376 * Using two BDs solves this issue.
377 */
fec_tbd_init(struct fec_priv * fec)378 static void fec_tbd_init(struct fec_priv *fec)
379 {
380 ulong addr = (ulong)fec->tbd_base;
381 unsigned size = roundup(2 * sizeof(struct fec_bd),
382 ARCH_DMA_MINALIGN);
383
384 memset(fec->tbd_base, 0, size);
385 fec->tbd_base[0].status = 0;
386 fec->tbd_base[1].status = FEC_TBD_WRAP;
387 fec->tbd_index = 0;
388 flush_dcache_range(addr, addr + size);
389 }
390
391 /**
392 * Mark the given read buffer descriptor as free
393 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
394 * @param[in] prbd buffer descriptor to mark free again
395 */
fec_rbd_clean(int last,struct fec_bd * prbd)396 static void fec_rbd_clean(int last, struct fec_bd *prbd)
397 {
398 unsigned short flags = FEC_RBD_EMPTY;
399 if (last)
400 flags |= FEC_RBD_WRAP;
401 writew(flags, &prbd->status);
402 writew(0, &prbd->data_length);
403 }
404
fec_get_hwaddr(int dev_id,unsigned char * mac)405 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
406 {
407 imx_get_mac_from_fuse(dev_id, mac);
408 return !is_valid_ethaddr(mac);
409 }
410
411 #ifdef CONFIG_DM_ETH
fecmxc_set_hwaddr(struct udevice * dev)412 static int fecmxc_set_hwaddr(struct udevice *dev)
413 #else
414 static int fec_set_hwaddr(struct eth_device *dev)
415 #endif
416 {
417 #ifdef CONFIG_DM_ETH
418 struct fec_priv *fec = dev_get_priv(dev);
419 struct eth_pdata *pdata = dev_get_plat(dev);
420 uchar *mac = pdata->enetaddr;
421 #else
422 uchar *mac = dev->enetaddr;
423 struct fec_priv *fec = (struct fec_priv *)dev->priv;
424 #endif
425
426 writel(0, &fec->eth->iaddr1);
427 writel(0, &fec->eth->iaddr2);
428 writel(0, &fec->eth->gaddr1);
429 writel(0, &fec->eth->gaddr2);
430
431 /* Set physical address */
432 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
433 &fec->eth->paddr1);
434 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
435
436 return 0;
437 }
438
439 /* Do initial configuration of the FEC registers */
fec_reg_setup(struct fec_priv * fec)440 static void fec_reg_setup(struct fec_priv *fec)
441 {
442 uint32_t rcntrl;
443
444 /* Set interrupt mask register */
445 writel(0x00000000, &fec->eth->imask);
446
447 /* Clear FEC-Lite interrupt event register(IEVENT) */
448 writel(0xffffffff, &fec->eth->ievent);
449
450 /* Set FEC-Lite receive control register(R_CNTRL): */
451
452 /* Start with frame length = 1518, common for all modes. */
453 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
454 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
455 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
456 if (fec->xcv_type == RGMII)
457 rcntrl |= FEC_RCNTRL_RGMII;
458 else if (fec->xcv_type == RMII)
459 rcntrl |= FEC_RCNTRL_RMII;
460
461 if (fec->promisc)
462 rcntrl |= 0x8;
463
464 writel(rcntrl, &fec->eth->r_cntrl);
465 }
466
467 /**
468 * Start the FEC engine
469 * @param[in] dev Our device to handle
470 */
471 #ifdef CONFIG_DM_ETH
fec_open(struct udevice * dev)472 static int fec_open(struct udevice *dev)
473 #else
474 static int fec_open(struct eth_device *edev)
475 #endif
476 {
477 #ifdef CONFIG_DM_ETH
478 struct fec_priv *fec = dev_get_priv(dev);
479 #else
480 struct fec_priv *fec = (struct fec_priv *)edev->priv;
481 #endif
482 int speed;
483 ulong addr, size;
484 int i;
485
486 debug("fec_open: fec_open(dev)\n");
487 /* full-duplex, heartbeat disabled */
488 writel(1 << 2, &fec->eth->x_cntrl);
489 fec->rbd_index = 0;
490
491 /* Invalidate all descriptors */
492 for (i = 0; i < FEC_RBD_NUM - 1; i++)
493 fec_rbd_clean(0, &fec->rbd_base[i]);
494 fec_rbd_clean(1, &fec->rbd_base[i]);
495
496 /* Flush the descriptors into RAM */
497 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
498 ARCH_DMA_MINALIGN);
499 addr = (ulong)fec->rbd_base;
500 flush_dcache_range(addr, addr + size);
501
502 #ifdef FEC_QUIRK_ENET_MAC
503 /* Enable ENET HW endian SWAP */
504 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
505 &fec->eth->ecntrl);
506 /* Enable ENET store and forward mode */
507 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
508 &fec->eth->x_wmrk);
509 #endif
510 /* Enable FEC-Lite controller */
511 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
512 &fec->eth->ecntrl);
513
514 #ifdef FEC_ENET_ENABLE_TXC_DELAY
515 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
516 &fec->eth->ecntrl);
517 #endif
518
519 #ifdef FEC_ENET_ENABLE_RXC_DELAY
520 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
521 &fec->eth->ecntrl);
522 #endif
523
524 #if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
525 udelay(100);
526
527 /* setup the MII gasket for RMII mode */
528 /* disable the gasket */
529 writew(0, &fec->eth->miigsk_enr);
530
531 /* wait for the gasket to be disabled */
532 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
533 udelay(2);
534
535 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
536 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
537
538 /* re-enable the gasket */
539 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
540
541 /* wait until MII gasket is ready */
542 int max_loops = 10;
543 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
544 if (--max_loops <= 0) {
545 printf("WAIT for MII Gasket ready timed out\n");
546 break;
547 }
548 }
549 #endif
550
551 #ifdef CONFIG_PHYLIB
552 {
553 /* Start up the PHY */
554 int ret = phy_startup(fec->phydev);
555
556 if (ret) {
557 printf("Could not initialize PHY %s\n",
558 fec->phydev->dev->name);
559 return ret;
560 }
561 speed = fec->phydev->speed;
562 }
563 #elif CONFIG_FEC_FIXED_SPEED
564 speed = CONFIG_FEC_FIXED_SPEED;
565 #else
566 miiphy_wait_aneg(edev);
567 speed = miiphy_speed(edev->name, fec->phy_id);
568 miiphy_duplex(edev->name, fec->phy_id);
569 #endif
570
571 #ifdef FEC_QUIRK_ENET_MAC
572 {
573 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
574 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
575 if (speed == _1000BASET)
576 ecr |= FEC_ECNTRL_SPEED;
577 else if (speed != _100BASET)
578 rcr |= FEC_RCNTRL_RMII_10T;
579 writel(ecr, &fec->eth->ecntrl);
580 writel(rcr, &fec->eth->r_cntrl);
581 }
582 #endif
583 debug("%s:Speed=%i\n", __func__, speed);
584
585 /* Enable SmartDMA receive task */
586 fec_rx_task_enable(fec);
587
588 udelay(100000);
589 return 0;
590 }
591
592 #ifdef CONFIG_DM_ETH
fecmxc_init(struct udevice * dev)593 static int fecmxc_init(struct udevice *dev)
594 #else
595 static int fec_init(struct eth_device *dev, struct bd_info *bd)
596 #endif
597 {
598 #ifdef CONFIG_DM_ETH
599 struct fec_priv *fec = dev_get_priv(dev);
600 #else
601 struct fec_priv *fec = (struct fec_priv *)dev->priv;
602 #endif
603 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
604 u8 *i;
605 ulong addr;
606
607 /* Initialize MAC address */
608 #ifdef CONFIG_DM_ETH
609 fecmxc_set_hwaddr(dev);
610 #else
611 fec_set_hwaddr(dev);
612 #endif
613
614 /* Setup transmit descriptors, there are two in total. */
615 fec_tbd_init(fec);
616
617 /* Setup receive descriptors. */
618 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
619
620 fec_reg_setup(fec);
621
622 if (fec->xcv_type != SEVENWIRE)
623 fec_mii_setspeed(fec->bus->priv);
624
625 /* Set Opcode/Pause Duration Register */
626 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
627 writel(0x2, &fec->eth->x_wmrk);
628
629 /* Set multicast address filter */
630 writel(0x00000000, &fec->eth->gaddr1);
631 writel(0x00000000, &fec->eth->gaddr2);
632
633 /* Do not access reserved register */
634 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) {
635 /* clear MIB RAM */
636 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
637 writel(0, i);
638
639 /* FIFO receive start register */
640 writel(0x520, &fec->eth->r_fstart);
641 }
642
643 /* size and address of each buffer */
644 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
645
646 addr = (ulong)fec->tbd_base;
647 writel((uint32_t)addr, &fec->eth->etdsr);
648
649 addr = (ulong)fec->rbd_base;
650 writel((uint32_t)addr, &fec->eth->erdsr);
651
652 #ifndef CONFIG_PHYLIB
653 if (fec->xcv_type != SEVENWIRE)
654 miiphy_restart_aneg(dev);
655 #endif
656 fec_open(dev);
657 return 0;
658 }
659
660 /**
661 * Halt the FEC engine
662 * @param[in] dev Our device to handle
663 */
664 #ifdef CONFIG_DM_ETH
fecmxc_halt(struct udevice * dev)665 static void fecmxc_halt(struct udevice *dev)
666 #else
667 static void fec_halt(struct eth_device *dev)
668 #endif
669 {
670 #ifdef CONFIG_DM_ETH
671 struct fec_priv *fec = dev_get_priv(dev);
672 #else
673 struct fec_priv *fec = (struct fec_priv *)dev->priv;
674 #endif
675 int counter = 0xffff;
676
677 /* issue graceful stop command to the FEC transmitter if necessary */
678 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
679 &fec->eth->x_cntrl);
680
681 debug("eth_halt: wait for stop regs\n");
682 /* wait for graceful stop to register */
683 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
684 udelay(1);
685
686 /* Disable SmartDMA tasks */
687 fec_tx_task_disable(fec);
688 fec_rx_task_disable(fec);
689
690 /*
691 * Disable the Ethernet Controller
692 * Note: this will also reset the BD index counter!
693 */
694 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
695 &fec->eth->ecntrl);
696 fec->rbd_index = 0;
697 fec->tbd_index = 0;
698 debug("eth_halt: done\n");
699 }
700
701 /**
702 * Transmit one frame
703 * @param[in] dev Our ethernet device to handle
704 * @param[in] packet Pointer to the data to be transmitted
705 * @param[in] length Data count in bytes
706 * @return 0 on success
707 */
708 #ifdef CONFIG_DM_ETH
fecmxc_send(struct udevice * dev,void * packet,int length)709 static int fecmxc_send(struct udevice *dev, void *packet, int length)
710 #else
711 static int fec_send(struct eth_device *dev, void *packet, int length)
712 #endif
713 {
714 unsigned int status;
715 u32 size;
716 ulong addr, end;
717 int timeout = FEC_XFER_TIMEOUT;
718 int ret = 0;
719
720 /*
721 * This routine transmits one frame. This routine only accepts
722 * 6-byte Ethernet addresses.
723 */
724 #ifdef CONFIG_DM_ETH
725 struct fec_priv *fec = dev_get_priv(dev);
726 #else
727 struct fec_priv *fec = (struct fec_priv *)dev->priv;
728 #endif
729
730 /*
731 * Check for valid length of data.
732 */
733 if ((length > 1500) || (length <= 0)) {
734 printf("Payload (%d) too large\n", length);
735 return -1;
736 }
737
738 /*
739 * Setup the transmit buffer. We are always using the first buffer for
740 * transmission, the second will be empty and only used to stop the DMA
741 * engine. We also flush the packet to RAM here to avoid cache trouble.
742 */
743 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
744 swap_packet((uint32_t *)packet, length);
745 #endif
746
747 addr = (ulong)packet;
748 end = roundup(addr + length, ARCH_DMA_MINALIGN);
749 addr &= ~(ARCH_DMA_MINALIGN - 1);
750 flush_dcache_range(addr, end);
751
752 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
753 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
754
755 /*
756 * update BD's status now
757 * This block:
758 * - is always the last in a chain (means no chain)
759 * - should transmitt the CRC
760 * - might be the last BD in the list, so the address counter should
761 * wrap (-> keep the WRAP flag)
762 */
763 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
764 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
765 writew(status, &fec->tbd_base[fec->tbd_index].status);
766
767 /*
768 * Flush data cache. This code flushes both TX descriptors to RAM.
769 * After this code, the descriptors will be safely in RAM and we
770 * can start DMA.
771 */
772 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
773 addr = (ulong)fec->tbd_base;
774 flush_dcache_range(addr, addr + size);
775
776 /*
777 * Below we read the DMA descriptor's last four bytes back from the
778 * DRAM. This is important in order to make sure that all WRITE
779 * operations on the bus that were triggered by previous cache FLUSH
780 * have completed.
781 *
782 * Otherwise, on MX28, it is possible to observe a corruption of the
783 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
784 * for the bus structure of MX28. The scenario is as follows:
785 *
786 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
787 * to DRAM due to flush_dcache_range()
788 * 2) ARM core writes the FEC registers via AHB_ARB2
789 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
790 *
791 * Note that 2) does sometimes finish before 1) due to reordering of
792 * WRITE accesses on the AHB bus, therefore triggering 3) before the
793 * DMA descriptor is fully written into DRAM. This results in occasional
794 * corruption of the DMA descriptor.
795 */
796 readl(addr + size - 4);
797
798 /* Enable SmartDMA transmit task */
799 fec_tx_task_enable(fec);
800
801 /*
802 * Wait until frame is sent. On each turn of the wait cycle, we must
803 * invalidate data cache to see what's really in RAM. Also, we need
804 * barrier here.
805 */
806 while (--timeout) {
807 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
808 break;
809 }
810
811 if (!timeout) {
812 ret = -EINVAL;
813 goto out;
814 }
815
816 /*
817 * The TDAR bit is cleared when the descriptors are all out from TX
818 * but on mx6solox we noticed that the READY bit is still not cleared
819 * right after TDAR.
820 * These are two distinct signals, and in IC simulation, we found that
821 * TDAR always gets cleared prior than the READY bit of last BD becomes
822 * cleared.
823 * In mx6solox, we use a later version of FEC IP. It looks like that
824 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
825 * version.
826 *
827 * Fix this by polling the READY bit of BD after the TDAR polling,
828 * which covers the mx6solox case and does not harm the other SoCs.
829 */
830 timeout = FEC_XFER_TIMEOUT;
831 while (--timeout) {
832 invalidate_dcache_range(addr, addr + size);
833 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
834 FEC_TBD_READY))
835 break;
836 }
837
838 if (!timeout)
839 ret = -EINVAL;
840
841 out:
842 debug("fec_send: status 0x%x index %d ret %i\n",
843 readw(&fec->tbd_base[fec->tbd_index].status),
844 fec->tbd_index, ret);
845 /* for next transmission use the other buffer */
846 if (fec->tbd_index)
847 fec->tbd_index = 0;
848 else
849 fec->tbd_index = 1;
850
851 return ret;
852 }
853
854 /**
855 * Pull one frame from the card
856 * @param[in] dev Our ethernet device to handle
857 * @return Length of packet read
858 */
859 #ifdef CONFIG_DM_ETH
fecmxc_recv(struct udevice * dev,int flags,uchar ** packetp)860 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
861 #else
862 static int fec_recv(struct eth_device *dev)
863 #endif
864 {
865 #ifdef CONFIG_DM_ETH
866 struct fec_priv *fec = dev_get_priv(dev);
867 #else
868 struct fec_priv *fec = (struct fec_priv *)dev->priv;
869 #endif
870 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
871 unsigned long ievent;
872 int frame_length, len = 0;
873 uint16_t bd_status;
874 ulong addr, size, end;
875 int i;
876
877 #ifdef CONFIG_DM_ETH
878 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
879 if (*packetp == 0) {
880 printf("%s: error allocating packetp\n", __func__);
881 return -ENOMEM;
882 }
883 #else
884 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
885 #endif
886
887 /* Check if any critical events have happened */
888 ievent = readl(&fec->eth->ievent);
889 writel(ievent, &fec->eth->ievent);
890 debug("fec_recv: ievent 0x%lx\n", ievent);
891 if (ievent & FEC_IEVENT_BABR) {
892 #ifdef CONFIG_DM_ETH
893 fecmxc_halt(dev);
894 fecmxc_init(dev);
895 #else
896 fec_halt(dev);
897 fec_init(dev, fec->bd);
898 #endif
899 printf("some error: 0x%08lx\n", ievent);
900 return 0;
901 }
902 if (ievent & FEC_IEVENT_HBERR) {
903 /* Heartbeat error */
904 writel(0x00000001 | readl(&fec->eth->x_cntrl),
905 &fec->eth->x_cntrl);
906 }
907 if (ievent & FEC_IEVENT_GRA) {
908 /* Graceful stop complete */
909 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
910 #ifdef CONFIG_DM_ETH
911 fecmxc_halt(dev);
912 #else
913 fec_halt(dev);
914 #endif
915 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
916 &fec->eth->x_cntrl);
917 #ifdef CONFIG_DM_ETH
918 fecmxc_init(dev);
919 #else
920 fec_init(dev, fec->bd);
921 #endif
922 }
923 }
924
925 /*
926 * Read the buffer status. Before the status can be read, the data cache
927 * must be invalidated, because the data in RAM might have been changed
928 * by DMA. The descriptors are properly aligned to cachelines so there's
929 * no need to worry they'd overlap.
930 *
931 * WARNING: By invalidating the descriptor here, we also invalidate
932 * the descriptors surrounding this one. Therefore we can NOT change the
933 * contents of this descriptor nor the surrounding ones. The problem is
934 * that in order to mark the descriptor as processed, we need to change
935 * the descriptor. The solution is to mark the whole cache line when all
936 * descriptors in the cache line are processed.
937 */
938 addr = (ulong)rbd;
939 addr &= ~(ARCH_DMA_MINALIGN - 1);
940 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
941 invalidate_dcache_range(addr, addr + size);
942
943 bd_status = readw(&rbd->status);
944 debug("fec_recv: status 0x%x\n", bd_status);
945
946 if (!(bd_status & FEC_RBD_EMPTY)) {
947 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
948 ((readw(&rbd->data_length) - 4) > 14)) {
949 /* Get buffer address and size */
950 addr = readl(&rbd->data_pointer);
951 frame_length = readw(&rbd->data_length) - 4;
952 /* Invalidate data cache over the buffer */
953 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
954 addr &= ~(ARCH_DMA_MINALIGN - 1);
955 invalidate_dcache_range(addr, end);
956
957 /* Fill the buffer and pass it to upper layers */
958 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
959 swap_packet((uint32_t *)addr, frame_length);
960 #endif
961
962 #ifdef CONFIG_DM_ETH
963 memcpy(*packetp, (char *)addr, frame_length);
964 #else
965 memcpy(buff, (char *)addr, frame_length);
966 net_process_received_packet(buff, frame_length);
967 #endif
968 len = frame_length;
969 } else {
970 if (bd_status & FEC_RBD_ERR)
971 debug("error frame: 0x%08lx 0x%08x\n",
972 addr, bd_status);
973 }
974
975 /*
976 * Free the current buffer, restart the engine and move forward
977 * to the next buffer. Here we check if the whole cacheline of
978 * descriptors was already processed and if so, we mark it free
979 * as whole.
980 */
981 size = RXDESC_PER_CACHELINE - 1;
982 if ((fec->rbd_index & size) == size) {
983 i = fec->rbd_index - size;
984 addr = (ulong)&fec->rbd_base[i];
985 for (; i <= fec->rbd_index ; i++) {
986 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
987 &fec->rbd_base[i]);
988 }
989 flush_dcache_range(addr,
990 addr + ARCH_DMA_MINALIGN);
991 }
992
993 fec_rx_task_enable(fec);
994 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
995 }
996 debug("fec_recv: stop\n");
997
998 return len;
999 }
1000
fec_set_dev_name(char * dest,int dev_id)1001 static void fec_set_dev_name(char *dest, int dev_id)
1002 {
1003 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
1004 }
1005
fec_alloc_descs(struct fec_priv * fec)1006 static int fec_alloc_descs(struct fec_priv *fec)
1007 {
1008 unsigned int size;
1009 int i;
1010 uint8_t *data;
1011 ulong addr;
1012
1013 /* Allocate TX descriptors. */
1014 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1015 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
1016 if (!fec->tbd_base)
1017 goto err_tx;
1018
1019 /* Allocate RX descriptors. */
1020 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1021 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1022 if (!fec->rbd_base)
1023 goto err_rx;
1024
1025 memset(fec->rbd_base, 0, size);
1026
1027 /* Allocate RX buffers. */
1028
1029 /* Maximum RX buffer size. */
1030 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
1031 for (i = 0; i < FEC_RBD_NUM; i++) {
1032 data = memalign(FEC_DMA_RX_MINALIGN, size);
1033 if (!data) {
1034 printf("%s: error allocating rxbuf %d\n", __func__, i);
1035 goto err_ring;
1036 }
1037
1038 memset(data, 0, size);
1039
1040 addr = (ulong)data;
1041 fec->rbd_base[i].data_pointer = (uint32_t)addr;
1042 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1043 fec->rbd_base[i].data_length = 0;
1044 /* Flush the buffer to memory. */
1045 flush_dcache_range(addr, addr + size);
1046 }
1047
1048 /* Mark the last RBD to close the ring. */
1049 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1050
1051 fec->rbd_index = 0;
1052 fec->tbd_index = 0;
1053
1054 return 0;
1055
1056 err_ring:
1057 for (; i >= 0; i--) {
1058 addr = fec->rbd_base[i].data_pointer;
1059 free((void *)addr);
1060 }
1061 free(fec->rbd_base);
1062 err_rx:
1063 free(fec->tbd_base);
1064 err_tx:
1065 return -ENOMEM;
1066 }
1067
fec_free_descs(struct fec_priv * fec)1068 static void fec_free_descs(struct fec_priv *fec)
1069 {
1070 int i;
1071 ulong addr;
1072
1073 for (i = 0; i < FEC_RBD_NUM; i++) {
1074 addr = fec->rbd_base[i].data_pointer;
1075 free((void *)addr);
1076 }
1077 free(fec->rbd_base);
1078 free(fec->tbd_base);
1079 }
1080
fec_get_miibus(ulong base_addr,int dev_id)1081 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1082 {
1083 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1084 struct mii_dev *bus;
1085 int ret;
1086
1087 bus = mdio_alloc();
1088 if (!bus) {
1089 printf("mdio_alloc failed\n");
1090 return NULL;
1091 }
1092 bus->read = fec_phy_read;
1093 bus->write = fec_phy_write;
1094 bus->priv = eth;
1095 fec_set_dev_name(bus->name, dev_id);
1096
1097 ret = mdio_register(bus);
1098 if (ret) {
1099 printf("mdio_register failed\n");
1100 free(bus);
1101 return NULL;
1102 }
1103 fec_mii_setspeed(eth);
1104 return bus;
1105 }
1106
1107 #ifndef CONFIG_DM_ETH
1108 #ifdef CONFIG_PHYLIB
fec_probe(struct bd_info * bd,int dev_id,uint32_t base_addr,struct mii_dev * bus,struct phy_device * phydev)1109 int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
1110 struct mii_dev *bus, struct phy_device *phydev)
1111 #else
1112 static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
1113 struct mii_dev *bus, int phy_id)
1114 #endif
1115 {
1116 struct eth_device *edev;
1117 struct fec_priv *fec;
1118 unsigned char ethaddr[6];
1119 char mac[16];
1120 uint32_t start;
1121 int ret = 0;
1122
1123 /* create and fill edev struct */
1124 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1125 if (!edev) {
1126 puts("fec_mxc: not enough malloc memory for eth_device\n");
1127 ret = -ENOMEM;
1128 goto err1;
1129 }
1130
1131 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1132 if (!fec) {
1133 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1134 ret = -ENOMEM;
1135 goto err2;
1136 }
1137
1138 memset(edev, 0, sizeof(*edev));
1139 memset(fec, 0, sizeof(*fec));
1140
1141 ret = fec_alloc_descs(fec);
1142 if (ret)
1143 goto err3;
1144
1145 edev->priv = fec;
1146 edev->init = fec_init;
1147 edev->send = fec_send;
1148 edev->recv = fec_recv;
1149 edev->halt = fec_halt;
1150 edev->write_hwaddr = fec_set_hwaddr;
1151
1152 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1153 fec->bd = bd;
1154
1155 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1156
1157 /* Reset chip. */
1158 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1159 start = get_timer(0);
1160 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1161 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1162 printf("FEC MXC: Timeout resetting chip\n");
1163 goto err4;
1164 }
1165 udelay(10);
1166 }
1167
1168 fec_reg_setup(fec);
1169 fec_set_dev_name(edev->name, dev_id);
1170 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1171 fec->bus = bus;
1172 fec_mii_setspeed(bus->priv);
1173 #ifdef CONFIG_PHYLIB
1174 fec->phydev = phydev;
1175 phy_connect_dev(phydev, edev);
1176 /* Configure phy */
1177 phy_config(phydev);
1178 #else
1179 fec->phy_id = phy_id;
1180 #endif
1181 eth_register(edev);
1182 /* only support one eth device, the index number pointed by dev_id */
1183 edev->index = fec->dev_id;
1184
1185 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1186 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1187 memcpy(edev->enetaddr, ethaddr, 6);
1188 if (fec->dev_id)
1189 sprintf(mac, "eth%daddr", fec->dev_id);
1190 else
1191 strcpy(mac, "ethaddr");
1192 if (!env_get(mac))
1193 eth_env_set_enetaddr(mac, ethaddr);
1194 }
1195 return ret;
1196 err4:
1197 fec_free_descs(fec);
1198 err3:
1199 free(fec);
1200 err2:
1201 free(edev);
1202 err1:
1203 return ret;
1204 }
1205
fecmxc_initialize_multi(struct bd_info * bd,int dev_id,int phy_id,uint32_t addr)1206 int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id,
1207 uint32_t addr)
1208 {
1209 uint32_t base_mii;
1210 struct mii_dev *bus = NULL;
1211 #ifdef CONFIG_PHYLIB
1212 struct phy_device *phydev = NULL;
1213 #endif
1214 int ret;
1215
1216 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1217 if (enet_fused((ulong)addr)) {
1218 printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
1219 return -ENODEV;
1220 }
1221 }
1222
1223 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1224 /*
1225 * The i.MX28 has two ethernet interfaces, but they are not equal.
1226 * Only the first one can access the MDIO bus.
1227 */
1228 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1229 #else
1230 base_mii = addr;
1231 #endif
1232 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1233 bus = fec_get_miibus(base_mii, dev_id);
1234 if (!bus)
1235 return -ENOMEM;
1236 #ifdef CONFIG_PHYLIB
1237 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1238 if (!phydev) {
1239 mdio_unregister(bus);
1240 free(bus);
1241 return -ENOMEM;
1242 }
1243 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1244 #else
1245 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1246 #endif
1247 if (ret) {
1248 #ifdef CONFIG_PHYLIB
1249 free(phydev);
1250 #endif
1251 mdio_unregister(bus);
1252 free(bus);
1253 }
1254 return ret;
1255 }
1256
1257 #ifdef CONFIG_FEC_MXC_PHYADDR
fecmxc_initialize(struct bd_info * bd)1258 int fecmxc_initialize(struct bd_info *bd)
1259 {
1260 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1261 IMX_FEC_BASE);
1262 }
1263 #endif
1264
1265 #ifndef CONFIG_PHYLIB
fecmxc_register_mii_postcall(struct eth_device * dev,int (* cb)(int))1266 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1267 {
1268 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1269 fec->mii_postcall = cb;
1270 return 0;
1271 }
1272 #endif
1273
1274 #else
1275
fecmxc_read_rom_hwaddr(struct udevice * dev)1276 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1277 {
1278 struct fec_priv *priv = dev_get_priv(dev);
1279 struct eth_pdata *pdata = dev_get_plat(dev);
1280
1281 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1282 }
1283
fecmxc_set_promisc(struct udevice * dev,bool enable)1284 static int fecmxc_set_promisc(struct udevice *dev, bool enable)
1285 {
1286 struct fec_priv *priv = dev_get_priv(dev);
1287
1288 priv->promisc = enable;
1289
1290 return 0;
1291 }
1292
fecmxc_free_pkt(struct udevice * dev,uchar * packet,int length)1293 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1294 {
1295 if (packet)
1296 free(packet);
1297
1298 return 0;
1299 }
1300
1301 static const struct eth_ops fecmxc_ops = {
1302 .start = fecmxc_init,
1303 .send = fecmxc_send,
1304 .recv = fecmxc_recv,
1305 .free_pkt = fecmxc_free_pkt,
1306 .stop = fecmxc_halt,
1307 .write_hwaddr = fecmxc_set_hwaddr,
1308 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1309 .set_promisc = fecmxc_set_promisc,
1310 };
1311
device_get_phy_addr(struct fec_priv * priv,struct udevice * dev)1312 static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
1313 {
1314 struct ofnode_phandle_args phandle_args;
1315 int reg, ret;
1316
1317 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1318 &phandle_args);
1319 if (ret) {
1320 priv->phy_of_node = ofnode_find_subnode(dev_ofnode(dev),
1321 "fixed-link");
1322 if (ofnode_valid(priv->phy_of_node))
1323 return 0;
1324 debug("Failed to find phy-handle (err = %d)\n", ret);
1325 return ret;
1326 }
1327
1328 if (!ofnode_is_available(phandle_args.node))
1329 return -ENOENT;
1330
1331 priv->phy_of_node = phandle_args.node;
1332 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1333
1334 return reg;
1335 }
1336
fec_phy_init(struct fec_priv * priv,struct udevice * dev)1337 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1338 {
1339 struct phy_device *phydev;
1340 int addr;
1341
1342 addr = device_get_phy_addr(priv, dev);
1343 #ifdef CONFIG_FEC_MXC_PHYADDR
1344 addr = CONFIG_FEC_MXC_PHYADDR;
1345 #endif
1346
1347 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1348 if (!phydev)
1349 return -ENODEV;
1350
1351 priv->phydev = phydev;
1352 priv->phydev->node = priv->phy_of_node;
1353 phy_config(phydev);
1354
1355 return 0;
1356 }
1357
1358 #if CONFIG_IS_ENABLED(DM_GPIO)
1359 /* FEC GPIO reset */
fec_gpio_reset(struct fec_priv * priv)1360 static void fec_gpio_reset(struct fec_priv *priv)
1361 {
1362 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1363 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1364 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1365 mdelay(priv->reset_delay);
1366 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1367 if (priv->reset_post_delay)
1368 mdelay(priv->reset_post_delay);
1369 }
1370 }
1371 #endif
1372
fecmxc_probe(struct udevice * dev)1373 static int fecmxc_probe(struct udevice *dev)
1374 {
1375 bool dm_mii_bus = true;
1376 struct eth_pdata *pdata = dev_get_plat(dev);
1377 struct fec_priv *priv = dev_get_priv(dev);
1378 struct mii_dev *bus = NULL;
1379 uint32_t start;
1380 int ret;
1381
1382 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1383 if (enet_fused((ulong)priv->eth)) {
1384 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1385 return -ENODEV;
1386 }
1387 }
1388
1389 if (IS_ENABLED(CONFIG_IMX8)) {
1390 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1391 if (ret < 0) {
1392 debug("Can't get FEC ipg clk: %d\n", ret);
1393 return ret;
1394 }
1395 ret = clk_enable(&priv->ipg_clk);
1396 if (ret < 0) {
1397 debug("Can't enable FEC ipg clk: %d\n", ret);
1398 return ret;
1399 }
1400
1401 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1402 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1403 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1404 if (ret < 0) {
1405 debug("Can't get FEC ipg clk: %d\n", ret);
1406 return ret;
1407 }
1408 ret = clk_enable(&priv->ipg_clk);
1409 if(ret)
1410 return ret;
1411
1412 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1413 if (ret < 0) {
1414 debug("Can't get FEC ahb clk: %d\n", ret);
1415 return ret;
1416 }
1417 ret = clk_enable(&priv->ahb_clk);
1418 if (ret)
1419 return ret;
1420
1421 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1422 if (!ret) {
1423 ret = clk_enable(&priv->clk_enet_out);
1424 if (ret)
1425 return ret;
1426 }
1427
1428 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1429 if (!ret) {
1430 ret = clk_enable(&priv->clk_ref);
1431 if (ret)
1432 return ret;
1433 }
1434
1435 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1436 if (!ret) {
1437 ret = clk_enable(&priv->clk_ptp);
1438 if (ret)
1439 return ret;
1440 }
1441
1442 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1443 }
1444
1445 ret = fec_alloc_descs(priv);
1446 if (ret)
1447 return ret;
1448
1449 #ifdef CONFIG_DM_REGULATOR
1450 if (priv->phy_supply) {
1451 ret = regulator_set_enable(priv->phy_supply, true);
1452 if (ret) {
1453 printf("%s: Error enabling phy supply\n", dev->name);
1454 return ret;
1455 }
1456 }
1457 #endif
1458
1459 #if CONFIG_IS_ENABLED(DM_GPIO)
1460 fec_gpio_reset(priv);
1461 #endif
1462 /* Reset chip. */
1463 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1464 &priv->eth->ecntrl);
1465 start = get_timer(0);
1466 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1467 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1468 printf("FEC MXC: Timeout reseting chip\n");
1469 goto err_timeout;
1470 }
1471 udelay(10);
1472 }
1473
1474 fec_reg_setup(priv);
1475
1476 priv->dev_id = dev_seq(dev);
1477
1478 #ifdef CONFIG_DM_ETH_PHY
1479 bus = eth_phy_get_mdio_bus(dev);
1480 #endif
1481
1482 if (!bus) {
1483 dm_mii_bus = false;
1484 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1485 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
1486 dev_seq(dev));
1487 #else
1488 bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
1489 #endif
1490 }
1491 if (!bus) {
1492 ret = -ENOMEM;
1493 goto err_mii;
1494 }
1495
1496 #ifdef CONFIG_DM_ETH_PHY
1497 eth_phy_set_mdio_bus(dev, bus);
1498 #endif
1499
1500 priv->bus = bus;
1501 priv->interface = pdata->phy_interface;
1502 switch (priv->interface) {
1503 case PHY_INTERFACE_MODE_MII:
1504 priv->xcv_type = MII100;
1505 break;
1506 case PHY_INTERFACE_MODE_RMII:
1507 priv->xcv_type = RMII;
1508 break;
1509 case PHY_INTERFACE_MODE_RGMII:
1510 case PHY_INTERFACE_MODE_RGMII_ID:
1511 case PHY_INTERFACE_MODE_RGMII_RXID:
1512 case PHY_INTERFACE_MODE_RGMII_TXID:
1513 priv->xcv_type = RGMII;
1514 break;
1515 default:
1516 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1517 printf("Unsupported interface type %d defaulting to %d\n",
1518 priv->interface, priv->xcv_type);
1519 break;
1520 }
1521
1522 ret = fec_phy_init(priv, dev);
1523 if (ret)
1524 goto err_phy;
1525
1526 return 0;
1527
1528 err_phy:
1529 if (!dm_mii_bus) {
1530 mdio_unregister(bus);
1531 free(bus);
1532 }
1533 err_mii:
1534 err_timeout:
1535 fec_free_descs(priv);
1536 return ret;
1537 }
1538
fecmxc_remove(struct udevice * dev)1539 static int fecmxc_remove(struct udevice *dev)
1540 {
1541 struct fec_priv *priv = dev_get_priv(dev);
1542
1543 free(priv->phydev);
1544 fec_free_descs(priv);
1545 mdio_unregister(priv->bus);
1546 mdio_free(priv->bus);
1547
1548 #ifdef CONFIG_DM_REGULATOR
1549 if (priv->phy_supply)
1550 regulator_set_enable(priv->phy_supply, false);
1551 #endif
1552
1553 return 0;
1554 }
1555
fecmxc_of_to_plat(struct udevice * dev)1556 static int fecmxc_of_to_plat(struct udevice *dev)
1557 {
1558 int ret = 0;
1559 struct eth_pdata *pdata = dev_get_plat(dev);
1560 struct fec_priv *priv = dev_get_priv(dev);
1561 const char *phy_mode;
1562
1563 pdata->iobase = dev_read_addr(dev);
1564 priv->eth = (struct ethernet_regs *)pdata->iobase;
1565
1566 pdata->phy_interface = -1;
1567 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1568 NULL);
1569 if (phy_mode)
1570 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1571 if (pdata->phy_interface == -1) {
1572 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1573 return -EINVAL;
1574 }
1575
1576 #ifdef CONFIG_DM_REGULATOR
1577 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1578 #endif
1579
1580 #if CONFIG_IS_ENABLED(DM_GPIO)
1581 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1582 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1583 if (ret < 0)
1584 return 0; /* property is optional, don't return error! */
1585
1586 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1587 if (priv->reset_delay > 1000) {
1588 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1589 /* property value wrong, use default value */
1590 priv->reset_delay = 1;
1591 }
1592
1593 priv->reset_post_delay = dev_read_u32_default(dev,
1594 "phy-reset-post-delay",
1595 0);
1596 if (priv->reset_post_delay > 1000) {
1597 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1598 /* property value wrong, use default value */
1599 priv->reset_post_delay = 0;
1600 }
1601 #endif
1602
1603 return 0;
1604 }
1605
1606 static const struct udevice_id fecmxc_ids[] = {
1607 { .compatible = "fsl,imx28-fec" },
1608 { .compatible = "fsl,imx6q-fec" },
1609 { .compatible = "fsl,imx6sl-fec" },
1610 { .compatible = "fsl,imx6sx-fec" },
1611 { .compatible = "fsl,imx6ul-fec" },
1612 { .compatible = "fsl,imx53-fec" },
1613 { .compatible = "fsl,imx7d-fec" },
1614 { .compatible = "fsl,mvf600-fec" },
1615 { }
1616 };
1617
1618 U_BOOT_DRIVER(fecmxc_gem) = {
1619 .name = "fecmxc",
1620 .id = UCLASS_ETH,
1621 .of_match = fecmxc_ids,
1622 .of_to_plat = fecmxc_of_to_plat,
1623 .probe = fecmxc_probe,
1624 .remove = fecmxc_remove,
1625 .ops = &fecmxc_ops,
1626 .priv_auto = sizeof(struct fec_priv),
1627 .plat_auto = sizeof(struct eth_pdata),
1628 };
1629 #endif
1630