1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2014-2015 Freescale Semiconductor
4 * Copyright 2019-2021 NXP
5 */
6
7 #include <common.h>
8 #include <clock_legacy.h>
9 #include <cpu_func.h>
10 #include <env.h>
11 #include <fsl_immap.h>
12 #include <fsl_ifc.h>
13 #include <init.h>
14 #include <linux/sizes.h>
15 #include <log.h>
16 #include <asm/arch/fsl_serdes.h>
17 #include <asm/arch/soc.h>
18 #include <asm/cache.h>
19 #include <asm/io.h>
20 #include <asm/global_data.h>
21 #include <asm/arch-fsl-layerscape/config.h>
22 #include <asm/arch-fsl-layerscape/ns_access.h>
23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
24 #include <asm/gic-v3.h>
25 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
26 #include <fsl_csu.h>
27 #endif
28 #ifdef CONFIG_SYS_FSL_DDR
29 #include <fsl_ddr_sdram.h>
30 #include <fsl_ddr.h>
31 #endif
32 #ifdef CONFIG_CHAIN_OF_TRUST
33 #include <fsl_validate.h>
34 #endif
35 #include <fsl_immap.h>
36 #include <dm.h>
37 #include <dm/device_compat.h>
38 #include <linux/err.h>
39 #ifdef CONFIG_GIC_V3_ITS
40 DECLARE_GLOBAL_DATA_PTR;
41 #endif
42
43 #ifdef CONFIG_GIC_V3_ITS
44 #define PENDTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS), SZ_64K)
45 #define PROPTABLE_MAX_SZ ALIGN(BIT(ITS_MAX_LPI_NRBITS) / 8, SZ_64K)
46 #define GIC_LPI_SIZE ALIGN(cpu_numcores() * PENDTABLE_MAX_SZ + \
47 PROPTABLE_MAX_SZ, SZ_1M)
fdt_add_resv_mem_gic_rd_tables(void * blob,u64 base,size_t size)48 static int fdt_add_resv_mem_gic_rd_tables(void *blob, u64 base, size_t size)
49 {
50 int err;
51 struct fdt_memory gic_rd_tables;
52
53 gic_rd_tables.start = base;
54 gic_rd_tables.end = base + size - 1;
55 err = fdtdec_add_reserved_memory(blob, "gic-rd-tables", &gic_rd_tables,
56 NULL, 0, NULL, 0);
57 if (err < 0)
58 debug("%s: failed to add reserved memory: %d\n", __func__, err);
59
60 return err;
61 }
62
ls_gic_rd_tables_init(void * blob)63 int ls_gic_rd_tables_init(void *blob)
64 {
65 u64 gic_lpi_base;
66 int ret;
67
68 gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
69 ret = fdt_add_resv_mem_gic_rd_tables(blob, gic_lpi_base, GIC_LPI_SIZE);
70 if (ret)
71 return ret;
72
73 ret = gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
74 if (ret)
75 debug("%s: failed to init gic-lpi-tables\n", __func__);
76
77 return ret;
78 }
79 #endif
80
soc_has_dp_ddr(void)81 bool soc_has_dp_ddr(void)
82 {
83 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
84 u32 svr = gur_in32(&gur->svr);
85
86 /* LS2085A, LS2088A, LS2048A has DP_DDR */
87 if ((SVR_SOC_VER(svr) == SVR_LS2085A) ||
88 (SVR_SOC_VER(svr) == SVR_LS2088A) ||
89 (SVR_SOC_VER(svr) == SVR_LS2048A))
90 return true;
91
92 return false;
93 }
94
soc_has_aiop(void)95 bool soc_has_aiop(void)
96 {
97 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
98 u32 svr = gur_in32(&gur->svr);
99
100 /* LS2085A has AIOP */
101 if (SVR_SOC_VER(svr) == SVR_LS2085A)
102 return true;
103
104 return false;
105 }
106
set_usb_txvreftune(u32 __iomem * scfg,u32 offset)107 static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)
108 {
109 scfg_clrsetbits32(scfg + offset / 4,
110 0xF << 6,
111 SCFG_USB_TXVREFTUNE << 6);
112 }
113
erratum_a009008(void)114 static void erratum_a009008(void)
115 {
116 #ifdef CONFIG_SYS_FSL_ERRATUM_A009008
117 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
118
119 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
120 defined(CONFIG_ARCH_LS1012A)
121 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);
122 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
123 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);
124 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);
125 #endif
126 #elif defined(CONFIG_ARCH_LS2080A)
127 set_usb_txvreftune(scfg, SCFG_USB3PRM1CR);
128 #endif
129 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
130 }
131
set_usb_sqrxtune(u32 __iomem * scfg,u32 offset)132 static inline void set_usb_sqrxtune(u32 __iomem *scfg, u32 offset)
133 {
134 scfg_clrbits32(scfg + offset / 4,
135 SCFG_USB_SQRXTUNE_MASK << 23);
136 }
137
erratum_a009798(void)138 static void erratum_a009798(void)
139 {
140 #ifdef CONFIG_SYS_FSL_ERRATUM_A009798
141 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
142
143 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
144 defined(CONFIG_ARCH_LS1012A)
145 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1);
146 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
147 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2);
148 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3);
149 #endif
150 #elif defined(CONFIG_ARCH_LS2080A)
151 set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR);
152 #endif
153 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
154 }
155
156 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
157 defined(CONFIG_ARCH_LS1012A)
set_usb_pcstxswingfull(u32 __iomem * scfg,u32 offset)158 static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset)
159 {
160 scfg_clrsetbits32(scfg + offset / 4,
161 0x7F << 9,
162 SCFG_USB_PCSTXSWINGFULL << 9);
163 }
164 #endif
165
erratum_a008997(void)166 static void erratum_a008997(void)
167 {
168 #ifdef CONFIG_SYS_FSL_ERRATUM_A008997
169 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
170 defined(CONFIG_ARCH_LS1012A)
171 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
172
173 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1);
174 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
175 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2);
176 set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3);
177 #endif
178 #elif defined(CONFIG_ARCH_LS1028A)
179 clrsetbits_le32(DCSR_BASE + DCSR_USB_IOCR1,
180 0x7F << 11,
181 DCSR_USB_PCSTXSWINGFULL << 11);
182 #endif
183 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
184 }
185
186 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
187 defined(CONFIG_ARCH_LS1012A)
188
189 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
190 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
191 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
192 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
193 out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
194
195 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
196 defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) || \
197 defined(CONFIG_ARCH_LX2162A)
198
199 #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \
200 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \
201 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2); \
202 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \
203 out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4)
204
205 #endif
206
erratum_a009007(void)207 static void erratum_a009007(void)
208 {
209 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \
210 defined(CONFIG_ARCH_LS1012A)
211 void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1;
212
213 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
214 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
215 usb_phy = (void __iomem *)SCFG_USB_PHY2;
216 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
217
218 usb_phy = (void __iomem *)SCFG_USB_PHY3;
219 PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy);
220 #endif
221 #elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
222 defined(CONFIG_ARCH_LS1028A)
223 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
224
225 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
226 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
227 #endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
228 }
229
230 #if defined(CONFIG_FSL_LSCH3)
erratum_a050204(void)231 static void erratum_a050204(void)
232 {
233 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
234 void __iomem *dcsr = (void __iomem *)DCSR_BASE;
235
236 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1);
237 PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY2);
238 #endif
239 }
240 /*
241 * This erratum requires setting a value to eddrtqcr1 to
242 * optimal the DDR performance.
243 */
erratum_a008336(void)244 static void erratum_a008336(void)
245 {
246 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
247 u32 *eddrtqcr1;
248
249 #ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
250 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
251 if (fsl_ddr_get_version(0) == 0x50200)
252 out_le32(eddrtqcr1, 0x63b30002);
253 #endif
254 #ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
255 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
256 if (fsl_ddr_get_version(0) == 0x50200)
257 out_le32(eddrtqcr1, 0x63b30002);
258 #endif
259 #endif
260 }
261
262 /*
263 * This erratum requires a register write before being Memory
264 * controller 3 being enabled.
265 */
erratum_a008514(void)266 static void erratum_a008514(void)
267 {
268 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
269 u32 *eddrtqcr1;
270
271 #ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
272 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
273 out_le32(eddrtqcr1, 0x63b20002);
274 #endif
275 #endif
276 }
277 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
278 #define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
279
get_internval_val_mhz(void)280 static unsigned long get_internval_val_mhz(void)
281 {
282 char *interval = env_get(PLATFORM_CYCLE_ENV_VAR);
283 /*
284 * interval is the number of platform cycles(MHz) between
285 * wake up events generated by EPU.
286 */
287 ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
288
289 if (interval)
290 interval_mhz = dectoul(interval, NULL);
291
292 return interval_mhz;
293 }
294
erratum_a009635(void)295 void erratum_a009635(void)
296 {
297 u32 val;
298 unsigned long interval_mhz = get_internval_val_mhz();
299
300 if (!interval_mhz)
301 return;
302
303 val = in_le32(DCSR_CGACRE5);
304 writel(val | 0x00000200, DCSR_CGACRE5);
305
306 val = in_le32(EPU_EPCMPR5);
307 writel(interval_mhz, EPU_EPCMPR5);
308 val = in_le32(EPU_EPCCR5);
309 writel(val | 0x82820000, EPU_EPCCR5);
310 val = in_le32(EPU_EPSMCR5);
311 writel(val | 0x002f0000, EPU_EPSMCR5);
312 val = in_le32(EPU_EPECR5);
313 writel(val | 0x20000000, EPU_EPECR5);
314 val = in_le32(EPU_EPGCR);
315 writel(val | 0x80000000, EPU_EPGCR);
316 }
317 #endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
318
erratum_rcw_src(void)319 static void erratum_rcw_src(void)
320 {
321 #if defined(CONFIG_SPL) && defined(CONFIG_NAND_BOOT)
322 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
323 u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
324 u32 val;
325
326 val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
327 val &= ~DCFG_PORSR1_RCW_SRC;
328 val |= DCFG_PORSR1_RCW_SRC_NOR;
329 out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
330 #endif
331 }
332
333 #define I2C_DEBUG_REG 0x6
334 #define I2C_GLITCH_EN 0x8
335 /*
336 * This erratum requires setting glitch_en bit to enable
337 * digital glitch filter to improve clock stability.
338 */
339 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
erratum_a009203(void)340 static void erratum_a009203(void)
341 {
342 #if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
343 u8 __iomem *ptr;
344 #ifdef I2C1_BASE_ADDR
345 ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
346
347 writeb(I2C_GLITCH_EN, ptr);
348 #endif
349 #ifdef I2C2_BASE_ADDR
350 ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
351
352 writeb(I2C_GLITCH_EN, ptr);
353 #endif
354 #ifdef I2C3_BASE_ADDR
355 ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
356
357 writeb(I2C_GLITCH_EN, ptr);
358 #endif
359 #ifdef I2C4_BASE_ADDR
360 ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
361
362 writeb(I2C_GLITCH_EN, ptr);
363 #endif
364 #endif
365 }
366 #endif
367
bypass_smmu(void)368 void bypass_smmu(void)
369 {
370 u32 val;
371 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
372 out_le32(SMMU_SCR0, val);
373 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
374 out_le32(SMMU_NSCR0, val);
375 }
fsl_lsch3_early_init_f(void)376 void fsl_lsch3_early_init_f(void)
377 {
378 erratum_rcw_src();
379 #ifdef CONFIG_FSL_IFC
380 init_early_memctl_regs(); /* tighten IFC timing */
381 #endif
382 #ifdef CONFIG_SYS_FSL_ERRATUM_A009203
383 erratum_a009203();
384 #endif
385 erratum_a008514();
386 erratum_a008336();
387 erratum_a009008();
388 erratum_a009798();
389 erratum_a008997();
390 erratum_a009007();
391 erratum_a050204();
392 #ifdef CONFIG_CHAIN_OF_TRUST
393 /* In case of Secure Boot, the IBR configures the SMMU
394 * to allow only Secure transactions.
395 * SMMU must be reset in bypass mode.
396 * Set the ClientPD bit and Clear the USFCFG Bit
397 */
398 if (fsl_check_boot_mode_secure() == 1)
399 bypass_smmu();
400 #endif
401
402 #if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) || \
403 defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) || \
404 defined(CONFIG_ARCH_LX2162A)
405 set_icids();
406 #endif
407 }
408
409 /* Get VDD in the unit mV from voltage ID */
get_core_volt_from_fuse(void)410 int get_core_volt_from_fuse(void)
411 {
412 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
413 int vdd;
414 u32 fusesr;
415 u8 vid;
416
417 /* get the voltage ID from fuse status register */
418 fusesr = in_le32(&gur->dcfg_fusesr);
419 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
420 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) &
421 FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK;
422 if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) {
423 vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) &
424 FSL_CHASSIS3_DCFG_FUSESR_VID_MASK;
425 }
426 debug("%s: VID = 0x%x\n", __func__, vid);
427 switch (vid) {
428 case 0x00: /* VID isn't supported */
429 vdd = -EINVAL;
430 debug("%s: The VID feature is not supported\n", __func__);
431 break;
432 case 0x08: /* 0.9V silicon */
433 vdd = 900;
434 break;
435 case 0x10: /* 1.0V silicon */
436 vdd = 1000;
437 break;
438 default: /* Other core voltage */
439 vdd = -EINVAL;
440 debug("%s: The VID(%x) isn't supported\n", __func__, vid);
441 break;
442 }
443 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
444
445 return vdd;
446 }
447
448 #elif defined(CONFIG_FSL_LSCH2)
449 /*
450 * This erratum requires setting a value to eddrtqcr1 to optimal
451 * the DDR performance. The eddrtqcr1 register is in SCFG space
452 * of LS1043A and the offset is 0x157_020c.
453 */
454 #if defined(CONFIG_SYS_FSL_ERRATUM_A009660) \
455 && defined(CONFIG_SYS_FSL_ERRATUM_A008514)
456 #error A009660 and A008514 can not be both enabled.
457 #endif
458
erratum_a009660(void)459 static void erratum_a009660(void)
460 {
461 #ifdef CONFIG_SYS_FSL_ERRATUM_A009660
462 u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
463 out_be32(eddrtqcr1, 0x63b20042);
464 #endif
465 }
466
erratum_a008850_early(void)467 static void erratum_a008850_early(void)
468 {
469 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
470 /* part 1 of 2 */
471 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
472 CONFIG_SYS_CCI400_OFFSET);
473 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
474
475 /* Skip if running at lower exception level */
476 if (current_el() < 3)
477 return;
478
479 /* disables propagation of barrier transactions to DDRC from CCI400 */
480 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
481
482 /* disable the re-ordering in DDRC */
483 ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
484 #endif
485 }
486
erratum_a008850_post(void)487 void erratum_a008850_post(void)
488 {
489 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
490 /* part 2 of 2 */
491 struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
492 CONFIG_SYS_CCI400_OFFSET);
493 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
494 u32 tmp;
495
496 /* Skip if running at lower exception level */
497 if (current_el() < 3)
498 return;
499
500 /* enable propagation of barrier transactions to DDRC from CCI400 */
501 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
502
503 /* enable the re-ordering in DDRC */
504 tmp = ddr_in32(&ddr->eor);
505 tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
506 ddr_out32(&ddr->eor, tmp);
507 #endif
508 }
509
510 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315(void)511 void erratum_a010315(void)
512 {
513 int i;
514
515 for (i = PCIE1; i <= PCIE4; i++)
516 if (!is_serdes_configured(i)) {
517 debug("PCIe%d: disabled all R/W permission!\n", i);
518 set_pcie_ns_access(i, 0);
519 }
520 }
521 #endif
522
erratum_a010539(void)523 static void erratum_a010539(void)
524 {
525 #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
526 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
527 u32 porsr1;
528
529 porsr1 = in_be32(&gur->porsr1);
530 porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
531 out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
532 porsr1);
533 out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
534 #endif
535 }
536
537 /* Get VDD in the unit mV from voltage ID */
get_core_volt_from_fuse(void)538 int get_core_volt_from_fuse(void)
539 {
540 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
541 int vdd;
542 u32 fusesr;
543 u8 vid;
544
545 fusesr = in_be32(&gur->dcfg_fusesr);
546 debug("%s: fusesr = 0x%x\n", __func__, fusesr);
547 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
548 FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
549 if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
550 vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
551 FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
552 }
553 debug("%s: VID = 0x%x\n", __func__, vid);
554 switch (vid) {
555 case 0x00: /* VID isn't supported */
556 vdd = -EINVAL;
557 debug("%s: The VID feature is not supported\n", __func__);
558 break;
559 case 0x08: /* 0.9V silicon */
560 vdd = 900;
561 break;
562 case 0x10: /* 1.0V silicon */
563 vdd = 1000;
564 break;
565 default: /* Other core voltage */
566 vdd = -EINVAL;
567 printf("%s: The VID(%x) isn't supported\n", __func__, vid);
568 break;
569 }
570 debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd);
571
572 return vdd;
573 }
574
board_switch_core_volt(u32 vdd)575 __weak int board_switch_core_volt(u32 vdd)
576 {
577 return 0;
578 }
579
setup_core_volt(u32 vdd)580 static int setup_core_volt(u32 vdd)
581 {
582 return board_setup_core_volt(vdd);
583 }
584
585 #ifdef CONFIG_SYS_FSL_DDR
ddr_enable_0v9_volt(bool en)586 static void ddr_enable_0v9_volt(bool en)
587 {
588 struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
589 u32 tmp;
590
591 tmp = ddr_in32(&ddr->ddr_cdr1);
592
593 if (en)
594 tmp |= DDR_CDR1_V0PT9_EN;
595 else
596 tmp &= ~DDR_CDR1_V0PT9_EN;
597
598 ddr_out32(&ddr->ddr_cdr1, tmp);
599 }
600 #endif
601
setup_chip_volt(void)602 int setup_chip_volt(void)
603 {
604 int vdd;
605
606 vdd = get_core_volt_from_fuse();
607 /* Nothing to do for silicons doesn't support VID */
608 if (vdd < 0)
609 return vdd;
610
611 if (setup_core_volt(vdd))
612 printf("%s: Switch core VDD to %dmV failed\n", __func__, vdd);
613 #ifdef CONFIG_SYS_HAS_SERDES
614 if (setup_serdes_volt(vdd))
615 printf("%s: Switch SVDD to %dmV failed\n", __func__, vdd);
616 #endif
617
618 #ifdef CONFIG_SYS_FSL_DDR
619 if (vdd == 900)
620 ddr_enable_0v9_volt(true);
621 #endif
622
623 return 0;
624 }
625
626 #ifdef CONFIG_FSL_PFE
init_pfe_scfg_dcfg_regs(void)627 void init_pfe_scfg_dcfg_regs(void)
628 {
629 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
630 u32 ecccr2;
631
632 out_be32(&scfg->pfeasbcr,
633 in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0);
634 out_be32(&scfg->pfebsbcr,
635 in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0);
636
637 /* CCI-400 QoS settings for PFE */
638 out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS
639 | SCFG_WR_QOS1_PFE2_QOS));
640 out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS
641 | SCFG_RD_QOS1_PFE2_QOS));
642
643 ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2);
644 out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2,
645 ecccr2 | (unsigned int)DISABLE_PFE_ECC);
646 }
647 #endif
648
fsl_lsch2_early_init_f(void)649 void fsl_lsch2_early_init_f(void)
650 {
651 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
652 CONFIG_SYS_CCI400_OFFSET);
653 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
654 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
655 enum boot_src src;
656 #endif
657
658 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
659 enable_layerscape_ns_access();
660 #endif
661
662 #ifdef CONFIG_FSL_IFC
663 init_early_memctl_regs(); /* tighten IFC timing */
664 #endif
665
666 #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
667 src = get_boot_src();
668 if (src != BOOT_SOURCE_QSPI_NOR)
669 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
670 #else
671 #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT)
672 out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
673 #endif
674 #endif
675 /* Make SEC reads and writes snoopable */
676 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
677 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
678 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
679 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_USB2RDSNP |
680 SCFG_SNPCNFGCR_USB2WRSNP | SCFG_SNPCNFGCR_USB3RDSNP |
681 SCFG_SNPCNFGCR_USB3WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
682 SCFG_SNPCNFGCR_SATAWRSNP);
683 #elif defined(CONFIG_ARCH_LS1012A)
684 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
685 SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_USB1RDSNP |
686 SCFG_SNPCNFGCR_USB1WRSNP | SCFG_SNPCNFGCR_SATARDSNP |
687 SCFG_SNPCNFGCR_SATAWRSNP);
688 #else
689 setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP |
690 SCFG_SNPCNFGCR_SECWRSNP |
691 SCFG_SNPCNFGCR_SATARDSNP |
692 SCFG_SNPCNFGCR_SATAWRSNP);
693 #endif
694
695 /*
696 * Enable snoop requests and DVM message requests for
697 * Slave insterface S4 (A53 core cluster)
698 */
699 if (current_el() == 3) {
700 out_le32(&cci->slave[4].snoop_ctrl,
701 CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
702 }
703
704 /*
705 * Program Central Security Unit (CSU) to grant access
706 * permission for USB 2.0 controller
707 */
708 #if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL)
709 if (current_el() == 3)
710 set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW);
711 #endif
712 /* Erratum */
713 erratum_a008850_early(); /* part 1 of 2 */
714 erratum_a009660();
715 erratum_a010539();
716 erratum_a009008();
717 erratum_a009798();
718 erratum_a008997();
719 erratum_a009007();
720
721 #if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
722 set_icids();
723 #endif
724 }
725 #endif
726
727 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
fspi_ahb_init(void)728 int fspi_ahb_init(void)
729 {
730 /* Enable 4bytes address support and fast read */
731 u32 *fspi_lut, lut_key, *fspi_key;
732
733 fspi_key = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUTKEY_BASE_ADDR;
734 fspi_lut = (void *)SYS_NXP_FSPI_ADDR + SYS_NXP_FSPI_LUT_BASE_ADDR;
735
736 lut_key = in_be32(fspi_key);
737
738 if (lut_key == SYS_NXP_FSPI_LUTKEY) {
739 /* That means the register is BE */
740 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
741 /* Unlock the lut table */
742 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
743 /* Create READ LUT */
744 out_be32(fspi_lut, 0x0820040c);
745 out_be32(fspi_lut + 1, 0x24003008);
746 out_be32(fspi_lut + 2, 0x00000000);
747 /* Lock the lut table */
748 out_be32(fspi_key, SYS_NXP_FSPI_LUTKEY);
749 out_be32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
750 } else {
751 /* That means the register is LE */
752 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
753 /* Unlock the lut table */
754 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_UNLOCK);
755 /* Create READ LUT */
756 out_le32(fspi_lut, 0x0820040c);
757 out_le32(fspi_lut + 1, 0x24003008);
758 out_le32(fspi_lut + 2, 0x00000000);
759 /* Lock the lut table */
760 out_le32(fspi_key, SYS_NXP_FSPI_LUTKEY);
761 out_le32(fspi_key + 1, SYS_NXP_FSPI_LUTCR_LOCK);
762 }
763
764 return 0;
765 }
766 #endif
767
768 #ifdef CONFIG_QSPI_AHB_INIT
769 /* Enable 4bytes address support and fast read */
qspi_ahb_init(void)770 int qspi_ahb_init(void)
771 {
772 u32 *qspi_lut, lut_key, *qspi_key;
773
774 qspi_key = (void *)SYS_FSL_QSPI_ADDR + 0x300;
775 qspi_lut = (void *)SYS_FSL_QSPI_ADDR + 0x310;
776
777 lut_key = in_be32(qspi_key);
778
779 if (lut_key == 0x5af05af0) {
780 /* That means the register is BE */
781 out_be32(qspi_key, 0x5af05af0);
782 /* Unlock the lut table */
783 out_be32(qspi_key + 1, 0x00000002);
784 out_be32(qspi_lut, 0x0820040c);
785 out_be32(qspi_lut + 1, 0x1c080c08);
786 out_be32(qspi_lut + 2, 0x00002400);
787 /* Lock the lut table */
788 out_be32(qspi_key, 0x5af05af0);
789 out_be32(qspi_key + 1, 0x00000001);
790 } else {
791 /* That means the register is LE */
792 out_le32(qspi_key, 0x5af05af0);
793 /* Unlock the lut table */
794 out_le32(qspi_key + 1, 0x00000002);
795 out_le32(qspi_lut, 0x0820040c);
796 out_le32(qspi_lut + 1, 0x1c080c08);
797 out_le32(qspi_lut + 2, 0x00002400);
798 /* Lock the lut table */
799 out_le32(qspi_key, 0x5af05af0);
800 out_le32(qspi_key + 1, 0x00000001);
801 }
802
803 return 0;
804 }
805 #endif
806
807 #ifdef CONFIG_TFABOOT
808 #define MAX_BOOTCMD_SIZE 512
809
fsl_setenv_bootcmd(void)810 int fsl_setenv_bootcmd(void)
811 {
812 int ret;
813 enum boot_src src = get_boot_src();
814 char bootcmd_str[MAX_BOOTCMD_SIZE];
815
816 switch (src) {
817 #ifdef IFC_NOR_BOOTCOMMAND
818 case BOOT_SOURCE_IFC_NOR:
819 sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND);
820 break;
821 #endif
822 #ifdef QSPI_NOR_BOOTCOMMAND
823 case BOOT_SOURCE_QSPI_NOR:
824 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
825 break;
826 #endif
827 #ifdef XSPI_NOR_BOOTCOMMAND
828 case BOOT_SOURCE_XSPI_NOR:
829 sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND);
830 break;
831 #endif
832 #ifdef IFC_NAND_BOOTCOMMAND
833 case BOOT_SOURCE_IFC_NAND:
834 sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND);
835 break;
836 #endif
837 #ifdef QSPI_NAND_BOOTCOMMAND
838 case BOOT_SOURCE_QSPI_NAND:
839 sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND);
840 break;
841 #endif
842 #ifdef XSPI_NAND_BOOTCOMMAND
843 case BOOT_SOURCE_XSPI_NAND:
844 sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND);
845 break;
846 #endif
847 #ifdef SD_BOOTCOMMAND
848 case BOOT_SOURCE_SD_MMC:
849 sprintf(bootcmd_str, SD_BOOTCOMMAND);
850 break;
851 #endif
852 #ifdef SD2_BOOTCOMMAND
853 case BOOT_SOURCE_SD_MMC2:
854 sprintf(bootcmd_str, SD2_BOOTCOMMAND);
855 break;
856 #endif
857 default:
858 #ifdef QSPI_NOR_BOOTCOMMAND
859 sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND);
860 #endif
861 break;
862 }
863
864 ret = env_set("bootcmd", bootcmd_str);
865 if (ret) {
866 printf("Failed to set bootcmd: ret = %d\n", ret);
867 return ret;
868 }
869 return 0;
870 }
871
fsl_setenv_mcinitcmd(void)872 int fsl_setenv_mcinitcmd(void)
873 {
874 int ret = 0;
875 enum boot_src src = get_boot_src();
876
877 switch (src) {
878 #ifdef IFC_MC_INIT_CMD
879 case BOOT_SOURCE_IFC_NAND:
880 case BOOT_SOURCE_IFC_NOR:
881 ret = env_set("mcinitcmd", IFC_MC_INIT_CMD);
882 break;
883 #endif
884 #ifdef QSPI_MC_INIT_CMD
885 case BOOT_SOURCE_QSPI_NAND:
886 case BOOT_SOURCE_QSPI_NOR:
887 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
888 break;
889 #endif
890 #ifdef XSPI_MC_INIT_CMD
891 case BOOT_SOURCE_XSPI_NAND:
892 case BOOT_SOURCE_XSPI_NOR:
893 ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD);
894 break;
895 #endif
896 #ifdef SD_MC_INIT_CMD
897 case BOOT_SOURCE_SD_MMC:
898 ret = env_set("mcinitcmd", SD_MC_INIT_CMD);
899 break;
900 #endif
901 #ifdef SD2_MC_INIT_CMD
902 case BOOT_SOURCE_SD_MMC2:
903 ret = env_set("mcinitcmd", SD2_MC_INIT_CMD);
904 break;
905 #endif
906 default:
907 #ifdef QSPI_MC_INIT_CMD
908 ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD);
909 #endif
910 break;
911 }
912
913 if (ret) {
914 printf("Failed to set mcinitcmd: ret = %d\n", ret);
915 return ret;
916 }
917 return 0;
918 }
919 #endif
920
921 #ifdef CONFIG_BOARD_LATE_INIT
fsl_board_late_init(void)922 __weak int fsl_board_late_init(void)
923 {
924 return 0;
925 }
926
927 #define DWC3_GSBUSCFG0 0xc100
928 #define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
929 #define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
930 << DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
931
enable_dwc3_snooping(void)932 void enable_dwc3_snooping(void)
933 {
934 int ret;
935 u32 val;
936 struct udevice *bus;
937 struct uclass *uc;
938 fdt_addr_t dwc3_base;
939
940 ret = uclass_get(UCLASS_USB, &uc);
941 if (ret)
942 return;
943
944 uclass_foreach_dev(bus, uc) {
945 if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
946 dwc3_base = devfdt_get_addr(bus);
947 if (dwc3_base == FDT_ADDR_T_NONE) {
948 dev_err(bus, "dwc3 regs missing\n");
949 continue;
950 }
951 val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
952 val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
953 val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
954 writel(val, dwc3_base + DWC3_GSBUSCFG0);
955 }
956 }
957 }
958
board_late_init(void)959 int board_late_init(void)
960 {
961 #ifdef CONFIG_CHAIN_OF_TRUST
962 fsl_setenv_chain_of_trust();
963 #endif
964 #ifdef CONFIG_TFABOOT
965 /*
966 * Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
967 * not exists in env
968 */
969 if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
970 // Set bootcmd and mcinitcmd as per boot source
971 fsl_setenv_bootcmd();
972 fsl_setenv_mcinitcmd();
973 env_set("fsl_bootcmd_mcinitcmd_set", "y");
974 }
975 #endif
976 #ifdef CONFIG_QSPI_AHB_INIT
977 qspi_ahb_init();
978 #endif
979 #ifdef CONFIG_FSPI_AHB_EN_4BYTE
980 fspi_ahb_init();
981 #endif
982
983 if (IS_ENABLED(CONFIG_DM))
984 enable_dwc3_snooping();
985
986 return fsl_board_late_init();
987 }
988 #endif
989