1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 4 * Altera Corporation <www.altera.com> 5 */ 6 7 #ifndef __CADENCE_QSPI_H__ 8 #define __CADENCE_QSPI_H__ 9 10 #include <reset.h> 11 12 #define CQSPI_IS_ADDR(cmd_len) (cmd_len > 1 ? 1 : 0) 13 14 #define CQSPI_NO_DECODER_MAX_CS 4 15 #define CQSPI_DECODER_MAX_CS 16 16 #define CQSPI_READ_CAPTURE_MAX_DELAY 16 17 18 struct cadence_spi_plat { 19 unsigned int ref_clk_hz; 20 unsigned int max_hz; 21 void *regbase; 22 void *ahbbase; 23 bool is_decoded_cs; 24 u32 fifo_depth; 25 u32 fifo_width; 26 u32 trigger_address; 27 fdt_addr_t ahbsize; 28 bool use_dac_mode; 29 int read_delay; 30 u32 wr_delay; 31 32 /* Flash parameters */ 33 u32 page_size; 34 u32 block_size; 35 u32 tshsl_ns; 36 u32 tsd2d_ns; 37 u32 tchsh_ns; 38 u32 tslch_ns; 39 40 /* Transaction protocol parameters. */ 41 u8 inst_width; 42 u8 addr_width; 43 u8 data_width; 44 bool dtr; 45 }; 46 47 struct cadence_spi_priv { 48 void *regbase; 49 void *ahbbase; 50 size_t cmd_len; 51 u8 cmd_buf[32]; 52 size_t data_len; 53 54 int qspi_is_init; 55 unsigned int qspi_calibrated_hz; 56 unsigned int qspi_calibrated_cs; 57 unsigned int previous_hz; 58 59 struct reset_ctl_bulk resets; 60 }; 61 62 /* Functions call declaration */ 63 void cadence_qspi_apb_controller_init(struct cadence_spi_plat *plat); 64 void cadence_qspi_apb_controller_enable(void *reg_base_addr); 65 void cadence_qspi_apb_controller_disable(void *reg_base_addr); 66 void cadence_qspi_apb_dac_mode_enable(void *reg_base); 67 68 int cadence_qspi_apb_command_read_setup(struct cadence_spi_plat *plat, 69 const struct spi_mem_op *op); 70 int cadence_qspi_apb_command_read(struct cadence_spi_plat *plat, 71 const struct spi_mem_op *op); 72 int cadence_qspi_apb_command_write_setup(struct cadence_spi_plat *plat, 73 const struct spi_mem_op *op); 74 int cadence_qspi_apb_command_write(struct cadence_spi_plat *plat, 75 const struct spi_mem_op *op); 76 77 int cadence_qspi_apb_read_setup(struct cadence_spi_plat *plat, 78 const struct spi_mem_op *op); 79 int cadence_qspi_apb_read_execute(struct cadence_spi_plat *plat, 80 const struct spi_mem_op *op); 81 int cadence_qspi_apb_write_setup(struct cadence_spi_plat *plat, 82 const struct spi_mem_op *op); 83 int cadence_qspi_apb_write_execute(struct cadence_spi_plat *plat, 84 const struct spi_mem_op *op); 85 86 void cadence_qspi_apb_chipselect(void *reg_base, 87 unsigned int chip_select, unsigned int decoder_enable); 88 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode); 89 void cadence_qspi_apb_config_baudrate_div(void *reg_base, 90 unsigned int ref_clk_hz, unsigned int sclk_hz); 91 void cadence_qspi_apb_delay(void *reg_base, 92 unsigned int ref_clk, unsigned int sclk_hz, 93 unsigned int tshsl_ns, unsigned int tsd2d_ns, 94 unsigned int tchsh_ns, unsigned int tslch_ns); 95 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy); 96 void cadence_qspi_apb_readdata_capture(void *reg_base, 97 unsigned int bypass, unsigned int delay); 98 99 #endif /* __CADENCE_QSPI_H__ */ 100