1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Microchip Image Sensor Controller (ISC) common driver base
4 *
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
6 *
7 * Author: Songjun Wu
8 * Author: Eugen Hristev <eugen.hristev@microchip.com>
9 *
10 */
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/math64.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/videodev2.h>
21 #include <linux/atmel-isc-media.h>
22
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-event.h>
26 #include <media/v4l2-image-sizes.h>
27 #include <media/v4l2-ioctl.h>
28 #include <media/v4l2-fwnode.h>
29 #include <media/v4l2-subdev.h>
30 #include <media/videobuf2-dma-contig.h>
31
32 #include "microchip-isc-regs.h"
33 #include "microchip-isc.h"
34
35 #define ISC_IS_FORMAT_RAW(mbus_code) \
36 (((mbus_code) & 0xf000) == 0x3000)
37
38 #define ISC_IS_FORMAT_GREY(mbus_code) \
39 (((mbus_code) == MEDIA_BUS_FMT_Y10_1X10) | \
40 (((mbus_code) == MEDIA_BUS_FMT_Y8_1X8)))
41
isc_update_v4l2_ctrls(struct isc_device * isc)42 static inline void isc_update_v4l2_ctrls(struct isc_device *isc)
43 {
44 struct isc_ctrls *ctrls = &isc->ctrls;
45
46 /* In here we set the v4l2 controls w.r.t. our pipeline config */
47 v4l2_ctrl_s_ctrl(isc->r_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_R]);
48 v4l2_ctrl_s_ctrl(isc->b_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_B]);
49 v4l2_ctrl_s_ctrl(isc->gr_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GR]);
50 v4l2_ctrl_s_ctrl(isc->gb_gain_ctrl, ctrls->gain[ISC_HIS_CFG_MODE_GB]);
51
52 v4l2_ctrl_s_ctrl(isc->r_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_R]);
53 v4l2_ctrl_s_ctrl(isc->b_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_B]);
54 v4l2_ctrl_s_ctrl(isc->gr_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GR]);
55 v4l2_ctrl_s_ctrl(isc->gb_off_ctrl, ctrls->offset[ISC_HIS_CFG_MODE_GB]);
56 }
57
isc_update_awb_ctrls(struct isc_device * isc)58 static inline void isc_update_awb_ctrls(struct isc_device *isc)
59 {
60 struct isc_ctrls *ctrls = &isc->ctrls;
61
62 /* In here we set our actual hw pipeline config */
63
64 regmap_write(isc->regmap, ISC_WB_O_RGR,
65 ((ctrls->offset[ISC_HIS_CFG_MODE_R])) |
66 ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16));
67 regmap_write(isc->regmap, ISC_WB_O_BGB,
68 ((ctrls->offset[ISC_HIS_CFG_MODE_B])) |
69 ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16));
70 regmap_write(isc->regmap, ISC_WB_G_RGR,
71 ctrls->gain[ISC_HIS_CFG_MODE_R] |
72 (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16));
73 regmap_write(isc->regmap, ISC_WB_G_BGB,
74 ctrls->gain[ISC_HIS_CFG_MODE_B] |
75 (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16));
76 }
77
isc_reset_awb_ctrls(struct isc_device * isc)78 static inline void isc_reset_awb_ctrls(struct isc_device *isc)
79 {
80 unsigned int c;
81
82 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
83 /* gains have a fixed point at 9 decimals */
84 isc->ctrls.gain[c] = 1 << 9;
85 /* offsets are in 2's complements */
86 isc->ctrls.offset[c] = 0;
87 }
88 }
89
isc_queue_setup(struct vb2_queue * vq,unsigned int * nbuffers,unsigned int * nplanes,unsigned int sizes[],struct device * alloc_devs[])90 static int isc_queue_setup(struct vb2_queue *vq,
91 unsigned int *nbuffers, unsigned int *nplanes,
92 unsigned int sizes[], struct device *alloc_devs[])
93 {
94 struct isc_device *isc = vb2_get_drv_priv(vq);
95 unsigned int size = isc->fmt.fmt.pix.sizeimage;
96
97 if (*nplanes)
98 return sizes[0] < size ? -EINVAL : 0;
99
100 *nplanes = 1;
101 sizes[0] = size;
102
103 return 0;
104 }
105
isc_buffer_prepare(struct vb2_buffer * vb)106 static int isc_buffer_prepare(struct vb2_buffer *vb)
107 {
108 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
109 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
110 unsigned long size = isc->fmt.fmt.pix.sizeimage;
111
112 if (vb2_plane_size(vb, 0) < size) {
113 dev_err(isc->dev, "buffer too small (%lu < %lu)\n",
114 vb2_plane_size(vb, 0), size);
115 return -EINVAL;
116 }
117
118 vb2_set_plane_payload(vb, 0, size);
119
120 vbuf->field = isc->fmt.fmt.pix.field;
121
122 return 0;
123 }
124
isc_crop_pfe(struct isc_device * isc)125 static void isc_crop_pfe(struct isc_device *isc)
126 {
127 struct regmap *regmap = isc->regmap;
128 u32 h, w;
129
130 h = isc->fmt.fmt.pix.height;
131 w = isc->fmt.fmt.pix.width;
132
133 /*
134 * In case the sensor is not RAW, it will output a pixel (12-16 bits)
135 * with two samples on the ISC Data bus (which is 8-12)
136 * ISC will count each sample, so, we need to multiply these values
137 * by two, to get the real number of samples for the required pixels.
138 */
139 if (!ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code)) {
140 h <<= 1;
141 w <<= 1;
142 }
143
144 /*
145 * We limit the column/row count that the ISC will output according
146 * to the configured resolution that we want.
147 * This will avoid the situation where the sensor is misconfigured,
148 * sending more data, and the ISC will just take it and DMA to memory,
149 * causing corruption.
150 */
151 regmap_write(regmap, ISC_PFE_CFG1,
152 (ISC_PFE_CFG1_COLMIN(0) & ISC_PFE_CFG1_COLMIN_MASK) |
153 (ISC_PFE_CFG1_COLMAX(w - 1) & ISC_PFE_CFG1_COLMAX_MASK));
154
155 regmap_write(regmap, ISC_PFE_CFG2,
156 (ISC_PFE_CFG2_ROWMIN(0) & ISC_PFE_CFG2_ROWMIN_MASK) |
157 (ISC_PFE_CFG2_ROWMAX(h - 1) & ISC_PFE_CFG2_ROWMAX_MASK));
158
159 regmap_update_bits(regmap, ISC_PFE_CFG0,
160 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN,
161 ISC_PFE_CFG0_COLEN | ISC_PFE_CFG0_ROWEN);
162 }
163
isc_start_dma(struct isc_device * isc)164 static void isc_start_dma(struct isc_device *isc)
165 {
166 struct regmap *regmap = isc->regmap;
167 u32 sizeimage = isc->fmt.fmt.pix.sizeimage;
168 u32 dctrl_dview;
169 dma_addr_t addr0;
170
171 addr0 = vb2_dma_contig_plane_dma_addr(&isc->cur_frm->vb.vb2_buf, 0);
172 regmap_write(regmap, ISC_DAD0 + isc->offsets.dma, addr0);
173
174 switch (isc->config.fourcc) {
175 case V4L2_PIX_FMT_YUV420:
176 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
177 addr0 + (sizeimage * 2) / 3);
178 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
179 addr0 + (sizeimage * 5) / 6);
180 break;
181 case V4L2_PIX_FMT_YUV422P:
182 regmap_write(regmap, ISC_DAD1 + isc->offsets.dma,
183 addr0 + sizeimage / 2);
184 regmap_write(regmap, ISC_DAD2 + isc->offsets.dma,
185 addr0 + (sizeimage * 3) / 4);
186 break;
187 default:
188 break;
189 }
190
191 dctrl_dview = isc->config.dctrl_dview;
192
193 regmap_write(regmap, ISC_DCTRL + isc->offsets.dma,
194 dctrl_dview | ISC_DCTRL_IE_IS);
195 spin_lock(&isc->awb_lock);
196 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);
197 spin_unlock(&isc->awb_lock);
198 }
199
isc_set_pipeline(struct isc_device * isc,u32 pipeline)200 static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)
201 {
202 struct regmap *regmap = isc->regmap;
203 struct isc_ctrls *ctrls = &isc->ctrls;
204 u32 val, bay_cfg;
205 const u32 *gamma;
206 unsigned int i;
207
208 /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
209 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
210 val = pipeline & BIT(i) ? 1 : 0;
211 regmap_field_write(isc->pipeline[i], val);
212 }
213
214 if (!pipeline)
215 return;
216
217 bay_cfg = isc->config.sd_format->cfa_baycfg;
218
219 regmap_write(regmap, ISC_WB_CFG, bay_cfg);
220 isc_update_awb_ctrls(isc);
221 isc_update_v4l2_ctrls(isc);
222
223 regmap_write(regmap, ISC_CFA_CFG, bay_cfg | ISC_CFA_CFG_EITPOL);
224
225 gamma = &isc->gamma_table[ctrls->gamma_index][0];
226 regmap_bulk_write(regmap, ISC_GAM_BENTRY, gamma, GAMMA_ENTRIES);
227 regmap_bulk_write(regmap, ISC_GAM_GENTRY, gamma, GAMMA_ENTRIES);
228 regmap_bulk_write(regmap, ISC_GAM_RENTRY, gamma, GAMMA_ENTRIES);
229
230 isc->config_dpc(isc);
231 isc->config_csc(isc);
232 isc->config_cbc(isc);
233 isc->config_cc(isc);
234 isc->config_gam(isc);
235 }
236
isc_update_profile(struct isc_device * isc)237 static int isc_update_profile(struct isc_device *isc)
238 {
239 struct regmap *regmap = isc->regmap;
240 u32 sr;
241 int counter = 100;
242
243 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_UPPRO);
244
245 regmap_read(regmap, ISC_CTRLSR, &sr);
246 while ((sr & ISC_CTRL_UPPRO) && counter--) {
247 usleep_range(1000, 2000);
248 regmap_read(regmap, ISC_CTRLSR, &sr);
249 }
250
251 if (counter < 0) {
252 v4l2_warn(&isc->v4l2_dev, "Time out to update profile\n");
253 return -ETIMEDOUT;
254 }
255
256 return 0;
257 }
258
isc_set_histogram(struct isc_device * isc,bool enable)259 static void isc_set_histogram(struct isc_device *isc, bool enable)
260 {
261 struct regmap *regmap = isc->regmap;
262 struct isc_ctrls *ctrls = &isc->ctrls;
263
264 if (enable) {
265 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
266 ISC_HIS_CFG_MODE_GR |
267 (isc->config.sd_format->cfa_baycfg
268 << ISC_HIS_CFG_BAYSEL_SHIFT) |
269 ISC_HIS_CFG_RAR);
270 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
271 ISC_HIS_CTRL_EN);
272 regmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);
273 ctrls->hist_id = ISC_HIS_CFG_MODE_GR;
274 isc_update_profile(isc);
275 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
276
277 ctrls->hist_stat = HIST_ENABLED;
278 } else {
279 regmap_write(regmap, ISC_INTDIS, ISC_INT_HISDONE);
280 regmap_write(regmap, ISC_HIS_CTRL + isc->offsets.his,
281 ISC_HIS_CTRL_DIS);
282
283 ctrls->hist_stat = HIST_DISABLED;
284 }
285 }
286
isc_configure(struct isc_device * isc)287 static int isc_configure(struct isc_device *isc)
288 {
289 struct regmap *regmap = isc->regmap;
290 u32 pfe_cfg0, dcfg, mask, pipeline;
291 struct isc_subdev_entity *subdev = isc->current_subdev;
292
293 pfe_cfg0 = isc->config.sd_format->pfe_cfg0_bps;
294 pipeline = isc->config.bits_pipeline;
295
296 dcfg = isc->config.dcfg_imode | isc->dcfg;
297
298 pfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;
299 mask = ISC_PFE_CFG0_BPS_MASK | ISC_PFE_CFG0_HPOL_LOW |
300 ISC_PFE_CFG0_VPOL_LOW | ISC_PFE_CFG0_PPOL_LOW |
301 ISC_PFE_CFG0_MODE_MASK | ISC_PFE_CFG0_CCIR_CRC |
302 ISC_PFE_CFG0_CCIR656 | ISC_PFE_CFG0_MIPI;
303
304 regmap_update_bits(regmap, ISC_PFE_CFG0, mask, pfe_cfg0);
305
306 isc->config_rlp(isc);
307
308 regmap_write(regmap, ISC_DCFG + isc->offsets.dma, dcfg);
309
310 /* Set the pipeline */
311 isc_set_pipeline(isc, pipeline);
312
313 /*
314 * The current implemented histogram is available for RAW R, B, GB, GR
315 * channels. We need to check if sensor is outputting RAW BAYER
316 */
317 if (isc->ctrls.awb &&
318 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
319 isc_set_histogram(isc, true);
320 else
321 isc_set_histogram(isc, false);
322
323 /* Update profile */
324 return isc_update_profile(isc);
325 }
326
isc_prepare_streaming(struct vb2_queue * vq)327 static int isc_prepare_streaming(struct vb2_queue *vq)
328 {
329 struct isc_device *isc = vb2_get_drv_priv(vq);
330
331 return media_pipeline_start(isc->video_dev.entity.pads, &isc->mpipe);
332 }
333
isc_start_streaming(struct vb2_queue * vq,unsigned int count)334 static int isc_start_streaming(struct vb2_queue *vq, unsigned int count)
335 {
336 struct isc_device *isc = vb2_get_drv_priv(vq);
337 struct regmap *regmap = isc->regmap;
338 struct isc_buffer *buf;
339 unsigned long flags;
340 int ret;
341
342 /* Enable stream on the sub device */
343 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 1);
344 if (ret && ret != -ENOIOCTLCMD) {
345 dev_err(isc->dev, "stream on failed in subdev %d\n", ret);
346 goto err_start_stream;
347 }
348
349 ret = pm_runtime_resume_and_get(isc->dev);
350 if (ret < 0) {
351 dev_err(isc->dev, "RPM resume failed in subdev %d\n",
352 ret);
353 goto err_pm_get;
354 }
355
356 ret = isc_configure(isc);
357 if (unlikely(ret))
358 goto err_configure;
359
360 /* Enable DMA interrupt */
361 regmap_write(regmap, ISC_INTEN, ISC_INT_DDONE);
362
363 spin_lock_irqsave(&isc->dma_queue_lock, flags);
364
365 isc->sequence = 0;
366 isc->stop = false;
367 reinit_completion(&isc->comp);
368
369 isc->cur_frm = list_first_entry(&isc->dma_queue,
370 struct isc_buffer, list);
371 list_del(&isc->cur_frm->list);
372
373 isc_crop_pfe(isc);
374 isc_start_dma(isc);
375
376 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
377
378 /* if we streaming from RAW, we can do one-shot white balance adj */
379 if (ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
380 v4l2_ctrl_activate(isc->do_wb_ctrl, true);
381
382 return 0;
383
384 err_configure:
385 pm_runtime_put_sync(isc->dev);
386 err_pm_get:
387 v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
388
389 err_start_stream:
390 spin_lock_irqsave(&isc->dma_queue_lock, flags);
391 list_for_each_entry(buf, &isc->dma_queue, list)
392 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED);
393 INIT_LIST_HEAD(&isc->dma_queue);
394 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
395
396 return ret;
397 }
398
isc_unprepare_streaming(struct vb2_queue * vq)399 static void isc_unprepare_streaming(struct vb2_queue *vq)
400 {
401 struct isc_device *isc = vb2_get_drv_priv(vq);
402
403 /* Stop media pipeline */
404 media_pipeline_stop(isc->video_dev.entity.pads);
405 }
406
isc_stop_streaming(struct vb2_queue * vq)407 static void isc_stop_streaming(struct vb2_queue *vq)
408 {
409 struct isc_device *isc = vb2_get_drv_priv(vq);
410 unsigned long flags;
411 struct isc_buffer *buf;
412 int ret;
413
414 mutex_lock(&isc->awb_mutex);
415 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
416
417 isc->stop = true;
418
419 /* Wait until the end of the current frame */
420 if (isc->cur_frm && !wait_for_completion_timeout(&isc->comp, 5 * HZ))
421 dev_err(isc->dev, "Timeout waiting for end of the capture\n");
422
423 mutex_unlock(&isc->awb_mutex);
424
425 /* Disable DMA interrupt */
426 regmap_write(isc->regmap, ISC_INTDIS, ISC_INT_DDONE);
427
428 pm_runtime_put_sync(isc->dev);
429
430 /* Disable stream on the sub device */
431 ret = v4l2_subdev_call(isc->current_subdev->sd, video, s_stream, 0);
432 if (ret && ret != -ENOIOCTLCMD)
433 dev_err(isc->dev, "stream off failed in subdev\n");
434
435 /* Release all active buffers */
436 spin_lock_irqsave(&isc->dma_queue_lock, flags);
437 if (unlikely(isc->cur_frm)) {
438 vb2_buffer_done(&isc->cur_frm->vb.vb2_buf,
439 VB2_BUF_STATE_ERROR);
440 isc->cur_frm = NULL;
441 }
442 list_for_each_entry(buf, &isc->dma_queue, list)
443 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
444 INIT_LIST_HEAD(&isc->dma_queue);
445 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
446 }
447
isc_buffer_queue(struct vb2_buffer * vb)448 static void isc_buffer_queue(struct vb2_buffer *vb)
449 {
450 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
451 struct isc_buffer *buf = container_of(vbuf, struct isc_buffer, vb);
452 struct isc_device *isc = vb2_get_drv_priv(vb->vb2_queue);
453 unsigned long flags;
454
455 spin_lock_irqsave(&isc->dma_queue_lock, flags);
456 if (!isc->cur_frm && list_empty(&isc->dma_queue) &&
457 vb2_start_streaming_called(vb->vb2_queue)) {
458 isc->cur_frm = buf;
459 isc_start_dma(isc);
460 } else {
461 list_add_tail(&buf->list, &isc->dma_queue);
462 }
463 spin_unlock_irqrestore(&isc->dma_queue_lock, flags);
464 }
465
466 static const struct vb2_ops isc_vb2_ops = {
467 .queue_setup = isc_queue_setup,
468 .wait_prepare = vb2_ops_wait_prepare,
469 .wait_finish = vb2_ops_wait_finish,
470 .buf_prepare = isc_buffer_prepare,
471 .start_streaming = isc_start_streaming,
472 .stop_streaming = isc_stop_streaming,
473 .buf_queue = isc_buffer_queue,
474 .prepare_streaming = isc_prepare_streaming,
475 .unprepare_streaming = isc_unprepare_streaming,
476 };
477
isc_querycap(struct file * file,void * priv,struct v4l2_capability * cap)478 static int isc_querycap(struct file *file, void *priv,
479 struct v4l2_capability *cap)
480 {
481 struct isc_device *isc = video_drvdata(file);
482
483 strscpy(cap->driver, "microchip-isc", sizeof(cap->driver));
484 strscpy(cap->card, "Microchip Image Sensor Controller", sizeof(cap->card));
485 snprintf(cap->bus_info, sizeof(cap->bus_info),
486 "platform:%s", isc->v4l2_dev.name);
487
488 return 0;
489 }
490
isc_enum_fmt_vid_cap(struct file * file,void * priv,struct v4l2_fmtdesc * f)491 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
492 struct v4l2_fmtdesc *f)
493 {
494 struct isc_device *isc = video_drvdata(file);
495 u32 index = f->index;
496 u32 i, supported_index = 0;
497 struct isc_format *fmt;
498
499 /*
500 * If we are not asked a specific mbus_code, we have to report all
501 * the formats that we can output.
502 */
503 if (!f->mbus_code) {
504 if (index >= isc->controller_formats_size)
505 return -EINVAL;
506
507 f->pixelformat = isc->controller_formats[index].fourcc;
508
509 return 0;
510 }
511
512 /*
513 * If a specific mbus_code is requested, check if we support
514 * this mbus_code as input for the ISC.
515 * If it's supported, then we report the corresponding pixelformat
516 * as first possible option for the ISC.
517 * E.g. mbus MEDIA_BUS_FMT_YUYV8_2X8 and report
518 * 'YUYV' (YUYV 4:2:2)
519 */
520 fmt = isc_find_format_by_code(isc, f->mbus_code, &i);
521 if (!fmt)
522 return -EINVAL;
523
524 if (!index) {
525 f->pixelformat = fmt->fourcc;
526
527 return 0;
528 }
529
530 supported_index++;
531
532 /* If the index is not raw, we don't have anymore formats to report */
533 if (!ISC_IS_FORMAT_RAW(f->mbus_code))
534 return -EINVAL;
535
536 /*
537 * We are asked for a specific mbus code, which is raw.
538 * We have to search through the formats we can convert to.
539 * We have to skip the raw formats, we cannot convert to raw.
540 * E.g. 'AR12' (16-bit ARGB 4-4-4-4), 'AR15' (16-bit ARGB 1-5-5-5), etc.
541 */
542 for (i = 0; i < isc->controller_formats_size; i++) {
543 if (isc->controller_formats[i].raw)
544 continue;
545 if (index == supported_index) {
546 f->pixelformat = isc->controller_formats[i].fourcc;
547 return 0;
548 }
549 supported_index++;
550 }
551
552 return -EINVAL;
553 }
554
isc_g_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * fmt)555 static int isc_g_fmt_vid_cap(struct file *file, void *priv,
556 struct v4l2_format *fmt)
557 {
558 struct isc_device *isc = video_drvdata(file);
559
560 *fmt = isc->fmt;
561
562 return 0;
563 }
564
565 /*
566 * Checks the current configured format, if ISC can output it,
567 * considering which type of format the ISC receives from the sensor
568 */
isc_try_validate_formats(struct isc_device * isc)569 static int isc_try_validate_formats(struct isc_device *isc)
570 {
571 int ret;
572 bool bayer = false, yuv = false, rgb = false, grey = false;
573
574 /* all formats supported by the RLP module are OK */
575 switch (isc->try_config.fourcc) {
576 case V4L2_PIX_FMT_SBGGR8:
577 case V4L2_PIX_FMT_SGBRG8:
578 case V4L2_PIX_FMT_SGRBG8:
579 case V4L2_PIX_FMT_SRGGB8:
580 case V4L2_PIX_FMT_SBGGR10:
581 case V4L2_PIX_FMT_SGBRG10:
582 case V4L2_PIX_FMT_SGRBG10:
583 case V4L2_PIX_FMT_SRGGB10:
584 case V4L2_PIX_FMT_SBGGR12:
585 case V4L2_PIX_FMT_SGBRG12:
586 case V4L2_PIX_FMT_SGRBG12:
587 case V4L2_PIX_FMT_SRGGB12:
588 ret = 0;
589 bayer = true;
590 break;
591
592 case V4L2_PIX_FMT_YUV420:
593 case V4L2_PIX_FMT_YUV422P:
594 case V4L2_PIX_FMT_YUYV:
595 case V4L2_PIX_FMT_UYVY:
596 case V4L2_PIX_FMT_VYUY:
597 ret = 0;
598 yuv = true;
599 break;
600
601 case V4L2_PIX_FMT_RGB565:
602 case V4L2_PIX_FMT_ABGR32:
603 case V4L2_PIX_FMT_XBGR32:
604 case V4L2_PIX_FMT_ARGB444:
605 case V4L2_PIX_FMT_ARGB555:
606 ret = 0;
607 rgb = true;
608 break;
609 case V4L2_PIX_FMT_GREY:
610 case V4L2_PIX_FMT_Y10:
611 case V4L2_PIX_FMT_Y16:
612 ret = 0;
613 grey = true;
614 break;
615 default:
616 /* any other different formats are not supported */
617 dev_err(isc->dev, "Requested unsupported format.\n");
618 ret = -EINVAL;
619 }
620 dev_dbg(isc->dev,
621 "Format validation, requested rgb=%u, yuv=%u, grey=%u, bayer=%u\n",
622 rgb, yuv, grey, bayer);
623
624 if (bayer &&
625 !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
626 dev_err(isc->dev, "Cannot output RAW if we do not receive RAW.\n");
627 return -EINVAL;
628 }
629
630 if (grey && !ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code) &&
631 !ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) {
632 dev_err(isc->dev, "Cannot output GREY if we do not receive RAW/GREY.\n");
633 return -EINVAL;
634 }
635
636 if ((rgb || bayer || yuv) &&
637 ISC_IS_FORMAT_GREY(isc->try_config.sd_format->mbus_code)) {
638 dev_err(isc->dev, "Cannot convert GREY to another format.\n");
639 return -EINVAL;
640 }
641
642 return ret;
643 }
644
645 /*
646 * Configures the RLP and DMA modules, depending on the output format
647 * configured for the ISC.
648 * If direct_dump == true, just dump raw data 8/16 bits depending on format.
649 */
isc_try_configure_rlp_dma(struct isc_device * isc,bool direct_dump)650 static int isc_try_configure_rlp_dma(struct isc_device *isc, bool direct_dump)
651 {
652 isc->try_config.rlp_cfg_mode = 0;
653
654 switch (isc->try_config.fourcc) {
655 case V4L2_PIX_FMT_SBGGR8:
656 case V4L2_PIX_FMT_SGBRG8:
657 case V4L2_PIX_FMT_SGRBG8:
658 case V4L2_PIX_FMT_SRGGB8:
659 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
660 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
661 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
662 isc->try_config.bpp = 8;
663 isc->try_config.bpp_v4l2 = 8;
664 break;
665 case V4L2_PIX_FMT_SBGGR10:
666 case V4L2_PIX_FMT_SGBRG10:
667 case V4L2_PIX_FMT_SGRBG10:
668 case V4L2_PIX_FMT_SRGGB10:
669 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT10;
670 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
671 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
672 isc->try_config.bpp = 16;
673 isc->try_config.bpp_v4l2 = 16;
674 break;
675 case V4L2_PIX_FMT_SBGGR12:
676 case V4L2_PIX_FMT_SGBRG12:
677 case V4L2_PIX_FMT_SGRBG12:
678 case V4L2_PIX_FMT_SRGGB12:
679 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT12;
680 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
681 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
682 isc->try_config.bpp = 16;
683 isc->try_config.bpp_v4l2 = 16;
684 break;
685 case V4L2_PIX_FMT_RGB565:
686 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_RGB565;
687 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
688 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
689 isc->try_config.bpp = 16;
690 isc->try_config.bpp_v4l2 = 16;
691 break;
692 case V4L2_PIX_FMT_ARGB444:
693 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB444;
694 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
695 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
696 isc->try_config.bpp = 16;
697 isc->try_config.bpp_v4l2 = 16;
698 break;
699 case V4L2_PIX_FMT_ARGB555:
700 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB555;
701 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
702 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
703 isc->try_config.bpp = 16;
704 isc->try_config.bpp_v4l2 = 16;
705 break;
706 case V4L2_PIX_FMT_ABGR32:
707 case V4L2_PIX_FMT_XBGR32:
708 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_ARGB32;
709 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
710 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
711 isc->try_config.bpp = 32;
712 isc->try_config.bpp_v4l2 = 32;
713 break;
714 case V4L2_PIX_FMT_YUV420:
715 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
716 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC420P;
717 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
718 isc->try_config.bpp = 12;
719 isc->try_config.bpp_v4l2 = 8; /* only first plane */
720 break;
721 case V4L2_PIX_FMT_YUV422P:
722 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YYCC;
723 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_YC422P;
724 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PLANAR;
725 isc->try_config.bpp = 16;
726 isc->try_config.bpp_v4l2 = 8; /* only first plane */
727 break;
728 case V4L2_PIX_FMT_YUYV:
729 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_YUYV;
730 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
731 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
732 isc->try_config.bpp = 16;
733 isc->try_config.bpp_v4l2 = 16;
734 break;
735 case V4L2_PIX_FMT_UYVY:
736 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_UYVY;
737 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
738 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
739 isc->try_config.bpp = 16;
740 isc->try_config.bpp_v4l2 = 16;
741 break;
742 case V4L2_PIX_FMT_VYUY:
743 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_YCYC | ISC_RLP_CFG_YMODE_VYUY;
744 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED32;
745 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
746 isc->try_config.bpp = 16;
747 isc->try_config.bpp_v4l2 = 16;
748 break;
749 case V4L2_PIX_FMT_GREY:
750 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY8;
751 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
752 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
753 isc->try_config.bpp = 8;
754 isc->try_config.bpp_v4l2 = 8;
755 break;
756 case V4L2_PIX_FMT_Y16:
757 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DATY10 | ISC_RLP_CFG_LSH;
758 fallthrough;
759 case V4L2_PIX_FMT_Y10:
760 isc->try_config.rlp_cfg_mode |= ISC_RLP_CFG_MODE_DATY10;
761 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED16;
762 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
763 isc->try_config.bpp = 16;
764 isc->try_config.bpp_v4l2 = 16;
765 break;
766 default:
767 return -EINVAL;
768 }
769
770 if (direct_dump) {
771 isc->try_config.rlp_cfg_mode = ISC_RLP_CFG_MODE_DAT8;
772 isc->try_config.dcfg_imode = ISC_DCFG_IMODE_PACKED8;
773 isc->try_config.dctrl_dview = ISC_DCTRL_DVIEW_PACKED;
774 return 0;
775 }
776
777 return 0;
778 }
779
780 /*
781 * Configuring pipeline modules, depending on which format the ISC outputs
782 * and considering which format it has as input from the sensor.
783 */
isc_try_configure_pipeline(struct isc_device * isc)784 static int isc_try_configure_pipeline(struct isc_device *isc)
785 {
786 switch (isc->try_config.fourcc) {
787 case V4L2_PIX_FMT_RGB565:
788 case V4L2_PIX_FMT_ARGB555:
789 case V4L2_PIX_FMT_ARGB444:
790 case V4L2_PIX_FMT_ABGR32:
791 case V4L2_PIX_FMT_XBGR32:
792 /* if sensor format is RAW, we convert inside ISC */
793 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
794 isc->try_config.bits_pipeline = CFA_ENABLE |
795 WB_ENABLE | GAM_ENABLES | DPC_BLCENABLE |
796 CC_ENABLE;
797 } else {
798 isc->try_config.bits_pipeline = 0x0;
799 }
800 break;
801 case V4L2_PIX_FMT_YUV420:
802 /* if sensor format is RAW, we convert inside ISC */
803 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
804 isc->try_config.bits_pipeline = CFA_ENABLE |
805 CSC_ENABLE | GAM_ENABLES | WB_ENABLE |
806 SUB420_ENABLE | SUB422_ENABLE | CBC_ENABLE |
807 DPC_BLCENABLE;
808 } else {
809 isc->try_config.bits_pipeline = 0x0;
810 }
811 break;
812 case V4L2_PIX_FMT_YUV422P:
813 /* if sensor format is RAW, we convert inside ISC */
814 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
815 isc->try_config.bits_pipeline = CFA_ENABLE |
816 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
817 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
818 } else {
819 isc->try_config.bits_pipeline = 0x0;
820 }
821 break;
822 case V4L2_PIX_FMT_YUYV:
823 case V4L2_PIX_FMT_UYVY:
824 case V4L2_PIX_FMT_VYUY:
825 /* if sensor format is RAW, we convert inside ISC */
826 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
827 isc->try_config.bits_pipeline = CFA_ENABLE |
828 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
829 SUB422_ENABLE | CBC_ENABLE | DPC_BLCENABLE;
830 } else {
831 isc->try_config.bits_pipeline = 0x0;
832 }
833 break;
834 case V4L2_PIX_FMT_GREY:
835 case V4L2_PIX_FMT_Y16:
836 /* if sensor format is RAW, we convert inside ISC */
837 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code)) {
838 isc->try_config.bits_pipeline = CFA_ENABLE |
839 CSC_ENABLE | WB_ENABLE | GAM_ENABLES |
840 CBC_ENABLE | DPC_BLCENABLE;
841 } else {
842 isc->try_config.bits_pipeline = 0x0;
843 }
844 break;
845 default:
846 if (ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
847 isc->try_config.bits_pipeline = WB_ENABLE | DPC_BLCENABLE;
848 else
849 isc->try_config.bits_pipeline = 0x0;
850 }
851
852 /* Tune the pipeline to product specific */
853 isc->adapt_pipeline(isc);
854
855 return 0;
856 }
857
isc_try_fse(struct isc_device * isc,struct v4l2_subdev_state * sd_state)858 static void isc_try_fse(struct isc_device *isc,
859 struct v4l2_subdev_state *sd_state)
860 {
861 int ret;
862 struct v4l2_subdev_frame_size_enum fse = {};
863
864 /*
865 * If we do not know yet which format the subdev is using, we cannot
866 * do anything.
867 */
868 if (!isc->config.sd_format)
869 return;
870
871 fse.code = isc->try_config.sd_format->mbus_code;
872 fse.which = V4L2_SUBDEV_FORMAT_TRY;
873
874 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, enum_frame_size,
875 sd_state, &fse);
876 /*
877 * Attempt to obtain format size from subdev. If not available,
878 * just use the maximum ISC can receive.
879 */
880 if (ret) {
881 sd_state->pads->try_crop.width = isc->max_width;
882 sd_state->pads->try_crop.height = isc->max_height;
883 } else {
884 sd_state->pads->try_crop.width = fse.max_width;
885 sd_state->pads->try_crop.height = fse.max_height;
886 }
887 }
888
isc_try_fmt(struct isc_device * isc,struct v4l2_format * f)889 static int isc_try_fmt(struct isc_device *isc, struct v4l2_format *f)
890 {
891 struct v4l2_pix_format *pixfmt = &f->fmt.pix;
892 unsigned int i;
893
894 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
895 return -EINVAL;
896
897 isc->try_config.fourcc = isc->controller_formats[0].fourcc;
898
899 /* find if the format requested is supported */
900 for (i = 0; i < isc->controller_formats_size; i++)
901 if (isc->controller_formats[i].fourcc == pixfmt->pixelformat) {
902 isc->try_config.fourcc = pixfmt->pixelformat;
903 break;
904 }
905
906 isc_try_configure_rlp_dma(isc, false);
907
908 /* Limit to Microchip ISC hardware capabilities */
909 v4l_bound_align_image(&pixfmt->width, 16, isc->max_width, 0,
910 &pixfmt->height, 16, isc->max_height, 0, 0);
911 /* If we did not find the requested format, we will fallback here */
912 pixfmt->pixelformat = isc->try_config.fourcc;
913 pixfmt->colorspace = V4L2_COLORSPACE_SRGB;
914 pixfmt->field = V4L2_FIELD_NONE;
915
916 pixfmt->bytesperline = (pixfmt->width * isc->try_config.bpp_v4l2) >> 3;
917 pixfmt->sizeimage = ((pixfmt->width * isc->try_config.bpp) >> 3) *
918 pixfmt->height;
919
920 isc->try_fmt = *f;
921
922 return 0;
923 }
924
isc_set_fmt(struct isc_device * isc,struct v4l2_format * f)925 static int isc_set_fmt(struct isc_device *isc, struct v4l2_format *f)
926 {
927 isc_try_fmt(isc, f);
928
929 /* make the try configuration active */
930 isc->config = isc->try_config;
931 isc->fmt = isc->try_fmt;
932
933 dev_dbg(isc->dev, "ISC set_fmt to %.4s @%dx%d\n",
934 (char *)&f->fmt.pix.pixelformat,
935 f->fmt.pix.width, f->fmt.pix.height);
936
937 return 0;
938 }
939
isc_validate(struct isc_device * isc)940 static int isc_validate(struct isc_device *isc)
941 {
942 int ret;
943 int i;
944 struct isc_format *sd_fmt = NULL;
945 struct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix;
946 struct v4l2_subdev_format format = {
947 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
948 .pad = isc->remote_pad,
949 };
950 struct v4l2_subdev_pad_config pad_cfg = {};
951 struct v4l2_subdev_state pad_state = {
952 .pads = &pad_cfg,
953 };
954
955 /* Get current format from subdev */
956 ret = v4l2_subdev_call(isc->current_subdev->sd, pad, get_fmt, NULL,
957 &format);
958 if (ret)
959 return ret;
960
961 /* Identify the subdev's format configuration */
962 for (i = 0; i < isc->formats_list_size; i++)
963 if (isc->formats_list[i].mbus_code == format.format.code) {
964 sd_fmt = &isc->formats_list[i];
965 break;
966 }
967
968 /* Check if the format is not supported */
969 if (!sd_fmt) {
970 dev_err(isc->dev,
971 "Current subdevice is streaming a media bus code that is not supported 0x%x\n",
972 format.format.code);
973 return -EPIPE;
974 }
975
976 /* At this moment we know which format the subdev will use */
977 isc->try_config.sd_format = sd_fmt;
978
979 /* If the sensor is not RAW, we can only do a direct dump */
980 if (!ISC_IS_FORMAT_RAW(isc->try_config.sd_format->mbus_code))
981 isc_try_configure_rlp_dma(isc, true);
982
983 /* Limit to Microchip ISC hardware capabilities */
984 v4l_bound_align_image(&format.format.width, 16, isc->max_width, 0,
985 &format.format.height, 16, isc->max_height, 0, 0);
986
987 /* Check if the frame size is the same. Otherwise we may overflow */
988 if (pixfmt->height != format.format.height ||
989 pixfmt->width != format.format.width) {
990 dev_err(isc->dev,
991 "ISC not configured with the proper frame size: %dx%d\n",
992 format.format.width, format.format.height);
993 return -EPIPE;
994 }
995
996 dev_dbg(isc->dev,
997 "Identified subdev using format %.4s with %dx%d %d bpp\n",
998 (char *)&sd_fmt->fourcc, pixfmt->width, pixfmt->height,
999 isc->try_config.bpp);
1000
1001 /* Reset and restart AWB if the subdevice changed the format */
1002 if (isc->try_config.sd_format && isc->config.sd_format &&
1003 isc->try_config.sd_format != isc->config.sd_format) {
1004 isc->ctrls.hist_stat = HIST_INIT;
1005 isc_reset_awb_ctrls(isc);
1006 isc_update_v4l2_ctrls(isc);
1007 }
1008
1009 /* Validate formats */
1010 ret = isc_try_validate_formats(isc);
1011 if (ret)
1012 return ret;
1013
1014 /* Obtain frame sizes if possible to have crop requirements ready */
1015 isc_try_fse(isc, &pad_state);
1016
1017 /* Configure ISC pipeline for the config */
1018 ret = isc_try_configure_pipeline(isc);
1019 if (ret)
1020 return ret;
1021
1022 isc->config = isc->try_config;
1023
1024 dev_dbg(isc->dev, "New ISC configuration in place\n");
1025
1026 return 0;
1027 }
1028
isc_s_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1029 static int isc_s_fmt_vid_cap(struct file *file, void *priv,
1030 struct v4l2_format *f)
1031 {
1032 struct isc_device *isc = video_drvdata(file);
1033
1034 if (vb2_is_busy(&isc->vb2_vidq))
1035 return -EBUSY;
1036
1037 return isc_set_fmt(isc, f);
1038 }
1039
isc_try_fmt_vid_cap(struct file * file,void * priv,struct v4l2_format * f)1040 static int isc_try_fmt_vid_cap(struct file *file, void *priv,
1041 struct v4l2_format *f)
1042 {
1043 struct isc_device *isc = video_drvdata(file);
1044
1045 return isc_try_fmt(isc, f);
1046 }
1047
isc_enum_input(struct file * file,void * priv,struct v4l2_input * inp)1048 static int isc_enum_input(struct file *file, void *priv,
1049 struct v4l2_input *inp)
1050 {
1051 if (inp->index != 0)
1052 return -EINVAL;
1053
1054 inp->type = V4L2_INPUT_TYPE_CAMERA;
1055 inp->std = 0;
1056 strscpy(inp->name, "Camera", sizeof(inp->name));
1057
1058 return 0;
1059 }
1060
isc_g_input(struct file * file,void * priv,unsigned int * i)1061 static int isc_g_input(struct file *file, void *priv, unsigned int *i)
1062 {
1063 *i = 0;
1064
1065 return 0;
1066 }
1067
isc_s_input(struct file * file,void * priv,unsigned int i)1068 static int isc_s_input(struct file *file, void *priv, unsigned int i)
1069 {
1070 if (i > 0)
1071 return -EINVAL;
1072
1073 return 0;
1074 }
1075
isc_g_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1076 static int isc_g_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1077 {
1078 struct isc_device *isc = video_drvdata(file);
1079
1080 return v4l2_g_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1081 }
1082
isc_s_parm(struct file * file,void * fh,struct v4l2_streamparm * a)1083 static int isc_s_parm(struct file *file, void *fh, struct v4l2_streamparm *a)
1084 {
1085 struct isc_device *isc = video_drvdata(file);
1086
1087 return v4l2_s_parm_cap(video_devdata(file), isc->current_subdev->sd, a);
1088 }
1089
isc_enum_framesizes(struct file * file,void * fh,struct v4l2_frmsizeenum * fsize)1090 static int isc_enum_framesizes(struct file *file, void *fh,
1091 struct v4l2_frmsizeenum *fsize)
1092 {
1093 struct isc_device *isc = video_drvdata(file);
1094 int ret = -EINVAL;
1095 int i;
1096
1097 if (fsize->index)
1098 return -EINVAL;
1099
1100 for (i = 0; i < isc->controller_formats_size; i++)
1101 if (isc->controller_formats[i].fourcc == fsize->pixel_format)
1102 ret = 0;
1103
1104 if (ret)
1105 return ret;
1106
1107 fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1108
1109 fsize->stepwise.min_width = 16;
1110 fsize->stepwise.max_width = isc->max_width;
1111 fsize->stepwise.min_height = 16;
1112 fsize->stepwise.max_height = isc->max_height;
1113 fsize->stepwise.step_width = 1;
1114 fsize->stepwise.step_height = 1;
1115
1116 return 0;
1117 }
1118
1119 static const struct v4l2_ioctl_ops isc_ioctl_ops = {
1120 .vidioc_querycap = isc_querycap,
1121 .vidioc_enum_fmt_vid_cap = isc_enum_fmt_vid_cap,
1122 .vidioc_g_fmt_vid_cap = isc_g_fmt_vid_cap,
1123 .vidioc_s_fmt_vid_cap = isc_s_fmt_vid_cap,
1124 .vidioc_try_fmt_vid_cap = isc_try_fmt_vid_cap,
1125
1126 .vidioc_enum_input = isc_enum_input,
1127 .vidioc_g_input = isc_g_input,
1128 .vidioc_s_input = isc_s_input,
1129
1130 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1131 .vidioc_querybuf = vb2_ioctl_querybuf,
1132 .vidioc_qbuf = vb2_ioctl_qbuf,
1133 .vidioc_expbuf = vb2_ioctl_expbuf,
1134 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1135 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1136 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1137 .vidioc_streamon = vb2_ioctl_streamon,
1138 .vidioc_streamoff = vb2_ioctl_streamoff,
1139
1140 .vidioc_g_parm = isc_g_parm,
1141 .vidioc_s_parm = isc_s_parm,
1142 .vidioc_enum_framesizes = isc_enum_framesizes,
1143
1144 .vidioc_log_status = v4l2_ctrl_log_status,
1145 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1146 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1147 };
1148
isc_open(struct file * file)1149 static int isc_open(struct file *file)
1150 {
1151 struct isc_device *isc = video_drvdata(file);
1152 struct v4l2_subdev *sd = isc->current_subdev->sd;
1153 int ret;
1154
1155 if (mutex_lock_interruptible(&isc->lock))
1156 return -ERESTARTSYS;
1157
1158 ret = v4l2_fh_open(file);
1159 if (ret < 0)
1160 goto unlock;
1161
1162 if (!v4l2_fh_is_singular_file(file))
1163 goto unlock;
1164
1165 ret = v4l2_subdev_call(sd, core, s_power, 1);
1166 if (ret < 0 && ret != -ENOIOCTLCMD) {
1167 v4l2_fh_release(file);
1168 goto unlock;
1169 }
1170
1171 ret = isc_set_fmt(isc, &isc->fmt);
1172 if (ret) {
1173 v4l2_subdev_call(sd, core, s_power, 0);
1174 v4l2_fh_release(file);
1175 }
1176
1177 unlock:
1178 mutex_unlock(&isc->lock);
1179 return ret;
1180 }
1181
isc_release(struct file * file)1182 static int isc_release(struct file *file)
1183 {
1184 struct isc_device *isc = video_drvdata(file);
1185 struct v4l2_subdev *sd = isc->current_subdev->sd;
1186 bool fh_singular;
1187 int ret;
1188
1189 mutex_lock(&isc->lock);
1190
1191 fh_singular = v4l2_fh_is_singular_file(file);
1192
1193 ret = _vb2_fop_release(file, NULL);
1194
1195 if (fh_singular)
1196 v4l2_subdev_call(sd, core, s_power, 0);
1197
1198 mutex_unlock(&isc->lock);
1199
1200 return ret;
1201 }
1202
1203 static const struct v4l2_file_operations isc_fops = {
1204 .owner = THIS_MODULE,
1205 .open = isc_open,
1206 .release = isc_release,
1207 .unlocked_ioctl = video_ioctl2,
1208 .read = vb2_fop_read,
1209 .mmap = vb2_fop_mmap,
1210 .poll = vb2_fop_poll,
1211 };
1212
microchip_isc_interrupt(int irq,void * dev_id)1213 irqreturn_t microchip_isc_interrupt(int irq, void *dev_id)
1214 {
1215 struct isc_device *isc = (struct isc_device *)dev_id;
1216 struct regmap *regmap = isc->regmap;
1217 u32 isc_intsr, isc_intmask, pending;
1218 irqreturn_t ret = IRQ_NONE;
1219
1220 regmap_read(regmap, ISC_INTSR, &isc_intsr);
1221 regmap_read(regmap, ISC_INTMASK, &isc_intmask);
1222
1223 pending = isc_intsr & isc_intmask;
1224
1225 if (likely(pending & ISC_INT_DDONE)) {
1226 spin_lock(&isc->dma_queue_lock);
1227 if (isc->cur_frm) {
1228 struct vb2_v4l2_buffer *vbuf = &isc->cur_frm->vb;
1229 struct vb2_buffer *vb = &vbuf->vb2_buf;
1230
1231 vb->timestamp = ktime_get_ns();
1232 vbuf->sequence = isc->sequence++;
1233 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1234 isc->cur_frm = NULL;
1235 }
1236
1237 if (!list_empty(&isc->dma_queue) && !isc->stop) {
1238 isc->cur_frm = list_first_entry(&isc->dma_queue,
1239 struct isc_buffer, list);
1240 list_del(&isc->cur_frm->list);
1241
1242 isc_start_dma(isc);
1243 }
1244
1245 if (isc->stop)
1246 complete(&isc->comp);
1247
1248 ret = IRQ_HANDLED;
1249 spin_unlock(&isc->dma_queue_lock);
1250 }
1251
1252 if (pending & ISC_INT_HISDONE) {
1253 schedule_work(&isc->awb_work);
1254 ret = IRQ_HANDLED;
1255 }
1256
1257 return ret;
1258 }
1259 EXPORT_SYMBOL_GPL(microchip_isc_interrupt);
1260
isc_hist_count(struct isc_device * isc,u32 * min,u32 * max)1261 static void isc_hist_count(struct isc_device *isc, u32 *min, u32 *max)
1262 {
1263 struct regmap *regmap = isc->regmap;
1264 struct isc_ctrls *ctrls = &isc->ctrls;
1265 u32 *hist_count = &ctrls->hist_count[ctrls->hist_id];
1266 u32 *hist_entry = &ctrls->hist_entry[0];
1267 u32 i;
1268
1269 *min = 0;
1270 *max = HIST_ENTRIES;
1271
1272 regmap_bulk_read(regmap, ISC_HIS_ENTRY + isc->offsets.his_entry,
1273 hist_entry, HIST_ENTRIES);
1274
1275 *hist_count = 0;
1276 /*
1277 * we deliberately ignore the end of the histogram,
1278 * the most white pixels
1279 */
1280 for (i = 1; i < HIST_ENTRIES; i++) {
1281 if (*hist_entry && !*min)
1282 *min = i;
1283 if (*hist_entry)
1284 *max = i;
1285 *hist_count += i * (*hist_entry++);
1286 }
1287
1288 if (!*min)
1289 *min = 1;
1290
1291 dev_dbg(isc->dev, "isc wb: hist_id %u, hist_count %u",
1292 ctrls->hist_id, *hist_count);
1293 }
1294
isc_wb_update(struct isc_ctrls * ctrls)1295 static void isc_wb_update(struct isc_ctrls *ctrls)
1296 {
1297 struct isc_device *isc = container_of(ctrls, struct isc_device, ctrls);
1298 u32 *hist_count = &ctrls->hist_count[0];
1299 u32 c, offset[4];
1300 u64 avg = 0;
1301 /* We compute two gains, stretch gain and grey world gain */
1302 u32 s_gain[4], gw_gain[4];
1303
1304 /*
1305 * According to Grey World, we need to set gains for R/B to normalize
1306 * them towards the green channel.
1307 * Thus we want to keep Green as fixed and adjust only Red/Blue
1308 * Compute the average of the both green channels first
1309 */
1310 avg = (u64)hist_count[ISC_HIS_CFG_MODE_GR] +
1311 (u64)hist_count[ISC_HIS_CFG_MODE_GB];
1312 avg >>= 1;
1313
1314 dev_dbg(isc->dev, "isc wb: green components average %llu\n", avg);
1315
1316 /* Green histogram is null, nothing to do */
1317 if (!avg)
1318 return;
1319
1320 for (c = ISC_HIS_CFG_MODE_GR; c <= ISC_HIS_CFG_MODE_B; c++) {
1321 /*
1322 * the color offset is the minimum value of the histogram.
1323 * we stretch this color to the full range by substracting
1324 * this value from the color component.
1325 */
1326 offset[c] = ctrls->hist_minmax[c][HIST_MIN_INDEX];
1327 /*
1328 * The offset is always at least 1. If the offset is 1, we do
1329 * not need to adjust it, so our result must be zero.
1330 * the offset is computed in a histogram on 9 bits (0..512)
1331 * but the offset in register is based on
1332 * 12 bits pipeline (0..4096).
1333 * we need to shift with the 3 bits that the histogram is
1334 * ignoring
1335 */
1336 ctrls->offset[c] = (offset[c] - 1) << 3;
1337
1338 /*
1339 * the offset is then taken and converted to 2's complements,
1340 * and must be negative, as we subtract this value from the
1341 * color components
1342 */
1343 ctrls->offset[c] = -ctrls->offset[c];
1344
1345 /*
1346 * the stretch gain is the total number of histogram bins
1347 * divided by the actual range of color component (Max - Min)
1348 * If we compute gain like this, the actual color component
1349 * will be stretched to the full histogram.
1350 * We need to shift 9 bits for precision, we have 9 bits for
1351 * decimals
1352 */
1353 s_gain[c] = (HIST_ENTRIES << 9) /
1354 (ctrls->hist_minmax[c][HIST_MAX_INDEX] -
1355 ctrls->hist_minmax[c][HIST_MIN_INDEX] + 1);
1356
1357 /*
1358 * Now we have to compute the gain w.r.t. the average.
1359 * Add/lose gain to the component towards the average.
1360 * If it happens that the component is zero, use the
1361 * fixed point value : 1.0 gain.
1362 */
1363 if (hist_count[c])
1364 gw_gain[c] = div_u64(avg << 9, hist_count[c]);
1365 else
1366 gw_gain[c] = 1 << 9;
1367
1368 dev_dbg(isc->dev,
1369 "isc wb: component %d, s_gain %u, gw_gain %u\n",
1370 c, s_gain[c], gw_gain[c]);
1371 /* multiply both gains and adjust for decimals */
1372 ctrls->gain[c] = s_gain[c] * gw_gain[c];
1373 ctrls->gain[c] >>= 9;
1374
1375 /* make sure we are not out of range */
1376 ctrls->gain[c] = clamp_val(ctrls->gain[c], 0, GENMASK(12, 0));
1377
1378 dev_dbg(isc->dev, "isc wb: component %d, final gain %u\n",
1379 c, ctrls->gain[c]);
1380 }
1381 }
1382
isc_awb_work(struct work_struct * w)1383 static void isc_awb_work(struct work_struct *w)
1384 {
1385 struct isc_device *isc =
1386 container_of(w, struct isc_device, awb_work);
1387 struct regmap *regmap = isc->regmap;
1388 struct isc_ctrls *ctrls = &isc->ctrls;
1389 u32 hist_id = ctrls->hist_id;
1390 u32 baysel;
1391 unsigned long flags;
1392 u32 min, max;
1393 int ret;
1394
1395 if (ctrls->hist_stat != HIST_ENABLED)
1396 return;
1397
1398 isc_hist_count(isc, &min, &max);
1399
1400 dev_dbg(isc->dev,
1401 "isc wb mode %d: hist min %u , max %u\n", hist_id, min, max);
1402
1403 ctrls->hist_minmax[hist_id][HIST_MIN_INDEX] = min;
1404 ctrls->hist_minmax[hist_id][HIST_MAX_INDEX] = max;
1405
1406 if (hist_id != ISC_HIS_CFG_MODE_B) {
1407 hist_id++;
1408 } else {
1409 isc_wb_update(ctrls);
1410 hist_id = ISC_HIS_CFG_MODE_GR;
1411 }
1412
1413 ctrls->hist_id = hist_id;
1414 baysel = isc->config.sd_format->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;
1415
1416 ret = pm_runtime_resume_and_get(isc->dev);
1417 if (ret < 0)
1418 return;
1419
1420 /*
1421 * only update if we have all the required histograms and controls
1422 * if awb has been disabled, we need to reset registers as well.
1423 */
1424 if (hist_id == ISC_HIS_CFG_MODE_GR || ctrls->awb == ISC_WB_NONE) {
1425 /*
1426 * It may happen that DMA Done IRQ will trigger while we are
1427 * updating white balance registers here.
1428 * In that case, only parts of the controls have been updated.
1429 * We can avoid that by locking the section.
1430 */
1431 spin_lock_irqsave(&isc->awb_lock, flags);
1432 isc_update_awb_ctrls(isc);
1433 spin_unlock_irqrestore(&isc->awb_lock, flags);
1434
1435 /*
1436 * if we are doing just the one time white balance adjustment,
1437 * we are basically done.
1438 */
1439 if (ctrls->awb == ISC_WB_ONETIME) {
1440 dev_info(isc->dev,
1441 "Completed one time white-balance adjustment.\n");
1442 /* update the v4l2 controls values */
1443 isc_update_v4l2_ctrls(isc);
1444 ctrls->awb = ISC_WB_NONE;
1445 }
1446 }
1447 regmap_write(regmap, ISC_HIS_CFG + isc->offsets.his,
1448 hist_id | baysel | ISC_HIS_CFG_RAR);
1449
1450 /*
1451 * We have to make sure the streaming has not stopped meanwhile.
1452 * ISC requires a frame to clock the internal profile update.
1453 * To avoid issues, lock the sequence with a mutex
1454 */
1455 mutex_lock(&isc->awb_mutex);
1456
1457 /* streaming is not active anymore */
1458 if (isc->stop) {
1459 mutex_unlock(&isc->awb_mutex);
1460 return;
1461 }
1462
1463 isc_update_profile(isc);
1464
1465 mutex_unlock(&isc->awb_mutex);
1466
1467 /* if awb has been disabled, we don't need to start another histogram */
1468 if (ctrls->awb)
1469 regmap_write(regmap, ISC_CTRLEN, ISC_CTRL_HISREQ);
1470
1471 pm_runtime_put_sync(isc->dev);
1472 }
1473
isc_s_ctrl(struct v4l2_ctrl * ctrl)1474 static int isc_s_ctrl(struct v4l2_ctrl *ctrl)
1475 {
1476 struct isc_device *isc = container_of(ctrl->handler,
1477 struct isc_device, ctrls.handler);
1478 struct isc_ctrls *ctrls = &isc->ctrls;
1479
1480 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1481 return 0;
1482
1483 switch (ctrl->id) {
1484 case V4L2_CID_BRIGHTNESS:
1485 ctrls->brightness = ctrl->val & ISC_CBC_BRIGHT_MASK;
1486 break;
1487 case V4L2_CID_CONTRAST:
1488 ctrls->contrast = ctrl->val & ISC_CBC_CONTRAST_MASK;
1489 break;
1490 case V4L2_CID_GAMMA:
1491 ctrls->gamma_index = ctrl->val;
1492 break;
1493 default:
1494 return -EINVAL;
1495 }
1496
1497 return 0;
1498 }
1499
1500 static const struct v4l2_ctrl_ops isc_ctrl_ops = {
1501 .s_ctrl = isc_s_ctrl,
1502 };
1503
isc_s_awb_ctrl(struct v4l2_ctrl * ctrl)1504 static int isc_s_awb_ctrl(struct v4l2_ctrl *ctrl)
1505 {
1506 struct isc_device *isc = container_of(ctrl->handler,
1507 struct isc_device, ctrls.handler);
1508 struct isc_ctrls *ctrls = &isc->ctrls;
1509
1510 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
1511 return 0;
1512
1513 switch (ctrl->id) {
1514 case V4L2_CID_AUTO_WHITE_BALANCE:
1515 if (ctrl->val == 1)
1516 ctrls->awb = ISC_WB_AUTO;
1517 else
1518 ctrls->awb = ISC_WB_NONE;
1519
1520 /* configure the controls with new values from v4l2 */
1521 if (ctrl->cluster[ISC_CTRL_R_GAIN]->is_new)
1522 ctrls->gain[ISC_HIS_CFG_MODE_R] = isc->r_gain_ctrl->val;
1523 if (ctrl->cluster[ISC_CTRL_B_GAIN]->is_new)
1524 ctrls->gain[ISC_HIS_CFG_MODE_B] = isc->b_gain_ctrl->val;
1525 if (ctrl->cluster[ISC_CTRL_GR_GAIN]->is_new)
1526 ctrls->gain[ISC_HIS_CFG_MODE_GR] = isc->gr_gain_ctrl->val;
1527 if (ctrl->cluster[ISC_CTRL_GB_GAIN]->is_new)
1528 ctrls->gain[ISC_HIS_CFG_MODE_GB] = isc->gb_gain_ctrl->val;
1529
1530 if (ctrl->cluster[ISC_CTRL_R_OFF]->is_new)
1531 ctrls->offset[ISC_HIS_CFG_MODE_R] = isc->r_off_ctrl->val;
1532 if (ctrl->cluster[ISC_CTRL_B_OFF]->is_new)
1533 ctrls->offset[ISC_HIS_CFG_MODE_B] = isc->b_off_ctrl->val;
1534 if (ctrl->cluster[ISC_CTRL_GR_OFF]->is_new)
1535 ctrls->offset[ISC_HIS_CFG_MODE_GR] = isc->gr_off_ctrl->val;
1536 if (ctrl->cluster[ISC_CTRL_GB_OFF]->is_new)
1537 ctrls->offset[ISC_HIS_CFG_MODE_GB] = isc->gb_off_ctrl->val;
1538
1539 isc_update_awb_ctrls(isc);
1540
1541 mutex_lock(&isc->awb_mutex);
1542 if (vb2_is_streaming(&isc->vb2_vidq)) {
1543 /*
1544 * If we are streaming, we can update profile to
1545 * have the new settings in place.
1546 */
1547 isc_update_profile(isc);
1548 } else {
1549 /*
1550 * The auto cluster will activate automatically this
1551 * control. This has to be deactivated when not
1552 * streaming.
1553 */
1554 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1555 }
1556 mutex_unlock(&isc->awb_mutex);
1557
1558 /* if we have autowhitebalance on, start histogram procedure */
1559 if (ctrls->awb == ISC_WB_AUTO &&
1560 vb2_is_streaming(&isc->vb2_vidq) &&
1561 ISC_IS_FORMAT_RAW(isc->config.sd_format->mbus_code))
1562 isc_set_histogram(isc, true);
1563
1564 /*
1565 * for one time whitebalance adjustment, check the button,
1566 * if it's pressed, perform the one time operation.
1567 */
1568 if (ctrls->awb == ISC_WB_NONE &&
1569 ctrl->cluster[ISC_CTRL_DO_WB]->is_new &&
1570 !(ctrl->cluster[ISC_CTRL_DO_WB]->flags &
1571 V4L2_CTRL_FLAG_INACTIVE)) {
1572 ctrls->awb = ISC_WB_ONETIME;
1573 isc_set_histogram(isc, true);
1574 dev_dbg(isc->dev, "One time white-balance started.\n");
1575 }
1576 return 0;
1577 }
1578 return 0;
1579 }
1580
isc_g_volatile_awb_ctrl(struct v4l2_ctrl * ctrl)1581 static int isc_g_volatile_awb_ctrl(struct v4l2_ctrl *ctrl)
1582 {
1583 struct isc_device *isc = container_of(ctrl->handler,
1584 struct isc_device, ctrls.handler);
1585 struct isc_ctrls *ctrls = &isc->ctrls;
1586
1587 switch (ctrl->id) {
1588 /* being a cluster, this id will be called for every control */
1589 case V4L2_CID_AUTO_WHITE_BALANCE:
1590 ctrl->cluster[ISC_CTRL_R_GAIN]->val =
1591 ctrls->gain[ISC_HIS_CFG_MODE_R];
1592 ctrl->cluster[ISC_CTRL_B_GAIN]->val =
1593 ctrls->gain[ISC_HIS_CFG_MODE_B];
1594 ctrl->cluster[ISC_CTRL_GR_GAIN]->val =
1595 ctrls->gain[ISC_HIS_CFG_MODE_GR];
1596 ctrl->cluster[ISC_CTRL_GB_GAIN]->val =
1597 ctrls->gain[ISC_HIS_CFG_MODE_GB];
1598
1599 ctrl->cluster[ISC_CTRL_R_OFF]->val =
1600 ctrls->offset[ISC_HIS_CFG_MODE_R];
1601 ctrl->cluster[ISC_CTRL_B_OFF]->val =
1602 ctrls->offset[ISC_HIS_CFG_MODE_B];
1603 ctrl->cluster[ISC_CTRL_GR_OFF]->val =
1604 ctrls->offset[ISC_HIS_CFG_MODE_GR];
1605 ctrl->cluster[ISC_CTRL_GB_OFF]->val =
1606 ctrls->offset[ISC_HIS_CFG_MODE_GB];
1607 break;
1608 }
1609 return 0;
1610 }
1611
1612 static const struct v4l2_ctrl_ops isc_awb_ops = {
1613 .s_ctrl = isc_s_awb_ctrl,
1614 .g_volatile_ctrl = isc_g_volatile_awb_ctrl,
1615 };
1616
1617 #define ISC_CTRL_OFF(_name, _id, _name_str) \
1618 static const struct v4l2_ctrl_config _name = { \
1619 .ops = &isc_awb_ops, \
1620 .id = _id, \
1621 .name = _name_str, \
1622 .type = V4L2_CTRL_TYPE_INTEGER, \
1623 .flags = V4L2_CTRL_FLAG_SLIDER, \
1624 .min = -4095, \
1625 .max = 4095, \
1626 .step = 1, \
1627 .def = 0, \
1628 }
1629
1630 ISC_CTRL_OFF(isc_r_off_ctrl, ISC_CID_R_OFFSET, "Red Component Offset");
1631 ISC_CTRL_OFF(isc_b_off_ctrl, ISC_CID_B_OFFSET, "Blue Component Offset");
1632 ISC_CTRL_OFF(isc_gr_off_ctrl, ISC_CID_GR_OFFSET, "Green Red Component Offset");
1633 ISC_CTRL_OFF(isc_gb_off_ctrl, ISC_CID_GB_OFFSET, "Green Blue Component Offset");
1634
1635 #define ISC_CTRL_GAIN(_name, _id, _name_str) \
1636 static const struct v4l2_ctrl_config _name = { \
1637 .ops = &isc_awb_ops, \
1638 .id = _id, \
1639 .name = _name_str, \
1640 .type = V4L2_CTRL_TYPE_INTEGER, \
1641 .flags = V4L2_CTRL_FLAG_SLIDER, \
1642 .min = 0, \
1643 .max = 8191, \
1644 .step = 1, \
1645 .def = 512, \
1646 }
1647
1648 ISC_CTRL_GAIN(isc_r_gain_ctrl, ISC_CID_R_GAIN, "Red Component Gain");
1649 ISC_CTRL_GAIN(isc_b_gain_ctrl, ISC_CID_B_GAIN, "Blue Component Gain");
1650 ISC_CTRL_GAIN(isc_gr_gain_ctrl, ISC_CID_GR_GAIN, "Green Red Component Gain");
1651 ISC_CTRL_GAIN(isc_gb_gain_ctrl, ISC_CID_GB_GAIN, "Green Blue Component Gain");
1652
isc_ctrl_init(struct isc_device * isc)1653 static int isc_ctrl_init(struct isc_device *isc)
1654 {
1655 const struct v4l2_ctrl_ops *ops = &isc_ctrl_ops;
1656 struct isc_ctrls *ctrls = &isc->ctrls;
1657 struct v4l2_ctrl_handler *hdl = &ctrls->handler;
1658 int ret;
1659
1660 ctrls->hist_stat = HIST_INIT;
1661 isc_reset_awb_ctrls(isc);
1662
1663 ret = v4l2_ctrl_handler_init(hdl, 13);
1664 if (ret < 0)
1665 return ret;
1666
1667 /* Initialize product specific controls. For example, contrast */
1668 isc->config_ctrls(isc, ops);
1669
1670 ctrls->brightness = 0;
1671
1672 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -1024, 1023, 1, 0);
1673 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA, 0, isc->gamma_max, 1,
1674 isc->gamma_max);
1675 isc->awb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1676 V4L2_CID_AUTO_WHITE_BALANCE,
1677 0, 1, 1, 1);
1678
1679 /* do_white_balance is a button, so min,max,step,default are ignored */
1680 isc->do_wb_ctrl = v4l2_ctrl_new_std(hdl, &isc_awb_ops,
1681 V4L2_CID_DO_WHITE_BALANCE,
1682 0, 0, 0, 0);
1683
1684 if (!isc->do_wb_ctrl) {
1685 ret = hdl->error;
1686 v4l2_ctrl_handler_free(hdl);
1687 return ret;
1688 }
1689
1690 v4l2_ctrl_activate(isc->do_wb_ctrl, false);
1691
1692 isc->r_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_gain_ctrl, NULL);
1693 isc->b_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_gain_ctrl, NULL);
1694 isc->gr_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_gain_ctrl, NULL);
1695 isc->gb_gain_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_gain_ctrl, NULL);
1696 isc->r_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_r_off_ctrl, NULL);
1697 isc->b_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_b_off_ctrl, NULL);
1698 isc->gr_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gr_off_ctrl, NULL);
1699 isc->gb_off_ctrl = v4l2_ctrl_new_custom(hdl, &isc_gb_off_ctrl, NULL);
1700
1701 /*
1702 * The cluster is in auto mode with autowhitebalance enabled
1703 * and manual mode otherwise.
1704 */
1705 v4l2_ctrl_auto_cluster(10, &isc->awb_ctrl, 0, true);
1706
1707 v4l2_ctrl_handler_setup(hdl);
1708
1709 return 0;
1710 }
1711
isc_async_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1712 static int isc_async_bound(struct v4l2_async_notifier *notifier,
1713 struct v4l2_subdev *subdev,
1714 struct v4l2_async_subdev *asd)
1715 {
1716 struct isc_device *isc = container_of(notifier->v4l2_dev,
1717 struct isc_device, v4l2_dev);
1718 struct isc_subdev_entity *subdev_entity =
1719 container_of(notifier, struct isc_subdev_entity, notifier);
1720 int pad;
1721
1722 if (video_is_registered(&isc->video_dev)) {
1723 dev_err(isc->dev, "only supports one sub-device.\n");
1724 return -EBUSY;
1725 }
1726
1727 subdev_entity->sd = subdev;
1728
1729 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode,
1730 MEDIA_PAD_FL_SOURCE);
1731 if (pad < 0) {
1732 dev_err(isc->dev, "failed to find pad for %s\n", subdev->name);
1733 return pad;
1734 }
1735
1736 isc->remote_pad = pad;
1737
1738 return 0;
1739 }
1740
isc_async_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * subdev,struct v4l2_async_subdev * asd)1741 static void isc_async_unbind(struct v4l2_async_notifier *notifier,
1742 struct v4l2_subdev *subdev,
1743 struct v4l2_async_subdev *asd)
1744 {
1745 struct isc_device *isc = container_of(notifier->v4l2_dev,
1746 struct isc_device, v4l2_dev);
1747 mutex_destroy(&isc->awb_mutex);
1748 cancel_work_sync(&isc->awb_work);
1749 video_unregister_device(&isc->video_dev);
1750 v4l2_ctrl_handler_free(&isc->ctrls.handler);
1751 }
1752
isc_find_format_by_code(struct isc_device * isc,unsigned int code,int * index)1753 struct isc_format *isc_find_format_by_code(struct isc_device *isc,
1754 unsigned int code, int *index)
1755 {
1756 struct isc_format *fmt = &isc->formats_list[0];
1757 unsigned int i;
1758
1759 for (i = 0; i < isc->formats_list_size; i++) {
1760 if (fmt->mbus_code == code) {
1761 *index = i;
1762 return fmt;
1763 }
1764
1765 fmt++;
1766 }
1767
1768 return NULL;
1769 }
1770 EXPORT_SYMBOL_GPL(isc_find_format_by_code);
1771
isc_set_default_fmt(struct isc_device * isc)1772 static int isc_set_default_fmt(struct isc_device *isc)
1773 {
1774 struct v4l2_format f = {
1775 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
1776 .fmt.pix = {
1777 .width = VGA_WIDTH,
1778 .height = VGA_HEIGHT,
1779 .field = V4L2_FIELD_NONE,
1780 .pixelformat = isc->controller_formats[0].fourcc,
1781 },
1782 };
1783 int ret;
1784
1785 ret = isc_try_fmt(isc, &f);
1786 if (ret)
1787 return ret;
1788
1789 isc->fmt = f;
1790 return 0;
1791 }
1792
isc_async_complete(struct v4l2_async_notifier * notifier)1793 static int isc_async_complete(struct v4l2_async_notifier *notifier)
1794 {
1795 struct isc_device *isc = container_of(notifier->v4l2_dev,
1796 struct isc_device, v4l2_dev);
1797 struct video_device *vdev = &isc->video_dev;
1798 struct vb2_queue *q = &isc->vb2_vidq;
1799 int ret = 0;
1800
1801 INIT_WORK(&isc->awb_work, isc_awb_work);
1802
1803 ret = v4l2_device_register_subdev_nodes(&isc->v4l2_dev);
1804 if (ret < 0) {
1805 dev_err(isc->dev, "Failed to register subdev nodes\n");
1806 return ret;
1807 }
1808
1809 isc->current_subdev = container_of(notifier,
1810 struct isc_subdev_entity, notifier);
1811 mutex_init(&isc->lock);
1812 mutex_init(&isc->awb_mutex);
1813
1814 init_completion(&isc->comp);
1815
1816 /* Initialize videobuf2 queue */
1817 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1818 q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
1819 q->drv_priv = isc;
1820 q->buf_struct_size = sizeof(struct isc_buffer);
1821 q->ops = &isc_vb2_ops;
1822 q->mem_ops = &vb2_dma_contig_memops;
1823 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1824 q->lock = &isc->lock;
1825 q->min_buffers_needed = 1;
1826 q->dev = isc->dev;
1827
1828 ret = vb2_queue_init(q);
1829 if (ret < 0) {
1830 dev_err(isc->dev, "vb2_queue_init() failed: %d\n", ret);
1831 goto isc_async_complete_err;
1832 }
1833
1834 /* Init video dma queues */
1835 INIT_LIST_HEAD(&isc->dma_queue);
1836 spin_lock_init(&isc->dma_queue_lock);
1837 spin_lock_init(&isc->awb_lock);
1838
1839 ret = isc_set_default_fmt(isc);
1840 if (ret) {
1841 dev_err(isc->dev, "Could not set default format\n");
1842 goto isc_async_complete_err;
1843 }
1844
1845 ret = isc_ctrl_init(isc);
1846 if (ret) {
1847 dev_err(isc->dev, "Init isc ctrols failed: %d\n", ret);
1848 goto isc_async_complete_err;
1849 }
1850
1851 /* Register video device */
1852 strscpy(vdev->name, KBUILD_MODNAME, sizeof(vdev->name));
1853 vdev->release = video_device_release_empty;
1854 vdev->fops = &isc_fops;
1855 vdev->ioctl_ops = &isc_ioctl_ops;
1856 vdev->v4l2_dev = &isc->v4l2_dev;
1857 vdev->vfl_dir = VFL_DIR_RX;
1858 vdev->queue = q;
1859 vdev->lock = &isc->lock;
1860 vdev->ctrl_handler = &isc->ctrls.handler;
1861 vdev->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE |
1862 V4L2_CAP_IO_MC;
1863 video_set_drvdata(vdev, isc);
1864
1865 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1866 if (ret < 0) {
1867 dev_err(isc->dev, "video_register_device failed: %d\n", ret);
1868 goto isc_async_complete_err;
1869 }
1870
1871 ret = isc_scaler_link(isc);
1872 if (ret < 0)
1873 goto isc_async_complete_unregister_device;
1874
1875 ret = media_device_register(&isc->mdev);
1876 if (ret < 0)
1877 goto isc_async_complete_unregister_device;
1878
1879 return 0;
1880
1881 isc_async_complete_unregister_device:
1882 video_unregister_device(vdev);
1883
1884 isc_async_complete_err:
1885 mutex_destroy(&isc->awb_mutex);
1886 mutex_destroy(&isc->lock);
1887 return ret;
1888 }
1889
1890 const struct v4l2_async_notifier_operations microchip_isc_async_ops = {
1891 .bound = isc_async_bound,
1892 .unbind = isc_async_unbind,
1893 .complete = isc_async_complete,
1894 };
1895 EXPORT_SYMBOL_GPL(microchip_isc_async_ops);
1896
microchip_isc_subdev_cleanup(struct isc_device * isc)1897 void microchip_isc_subdev_cleanup(struct isc_device *isc)
1898 {
1899 struct isc_subdev_entity *subdev_entity;
1900
1901 list_for_each_entry(subdev_entity, &isc->subdev_entities, list) {
1902 v4l2_async_nf_unregister(&subdev_entity->notifier);
1903 v4l2_async_nf_cleanup(&subdev_entity->notifier);
1904 }
1905
1906 INIT_LIST_HEAD(&isc->subdev_entities);
1907 }
1908 EXPORT_SYMBOL_GPL(microchip_isc_subdev_cleanup);
1909
microchip_isc_pipeline_init(struct isc_device * isc)1910 int microchip_isc_pipeline_init(struct isc_device *isc)
1911 {
1912 struct device *dev = isc->dev;
1913 struct regmap *regmap = isc->regmap;
1914 struct regmap_field *regs;
1915 unsigned int i;
1916
1917 /*
1918 * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
1919 * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
1920 */
1921 const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
1922 REG_FIELD(ISC_DPC_CTRL, 0, 0),
1923 REG_FIELD(ISC_DPC_CTRL, 1, 1),
1924 REG_FIELD(ISC_DPC_CTRL, 2, 2),
1925 REG_FIELD(ISC_WB_CTRL, 0, 0),
1926 REG_FIELD(ISC_CFA_CTRL, 0, 0),
1927 REG_FIELD(ISC_CC_CTRL, 0, 0),
1928 REG_FIELD(ISC_GAM_CTRL, 0, 0),
1929 REG_FIELD(ISC_GAM_CTRL, 1, 1),
1930 REG_FIELD(ISC_GAM_CTRL, 2, 2),
1931 REG_FIELD(ISC_GAM_CTRL, 3, 3),
1932 REG_FIELD(ISC_VHXS_CTRL, 0, 0),
1933 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
1934 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
1935 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
1936 REG_FIELD(ISC_SUB420_CTRL + isc->offsets.sub420, 0, 0),
1937 };
1938
1939 for (i = 0; i < ISC_PIPE_LINE_NODE_NUM; i++) {
1940 regs = devm_regmap_field_alloc(dev, regmap, regfields[i]);
1941 if (IS_ERR(regs))
1942 return PTR_ERR(regs);
1943
1944 isc->pipeline[i] = regs;
1945 }
1946
1947 return 0;
1948 }
1949 EXPORT_SYMBOL_GPL(microchip_isc_pipeline_init);
1950
isc_link_validate(struct media_link * link)1951 static int isc_link_validate(struct media_link *link)
1952 {
1953 struct video_device *vdev =
1954 media_entity_to_video_device(link->sink->entity);
1955 struct isc_device *isc = video_get_drvdata(vdev);
1956 int ret;
1957
1958 ret = v4l2_subdev_link_validate(link);
1959 if (ret)
1960 return ret;
1961
1962 return isc_validate(isc);
1963 }
1964
1965 static const struct media_entity_operations isc_entity_operations = {
1966 .link_validate = isc_link_validate,
1967 };
1968
isc_mc_init(struct isc_device * isc,u32 ver)1969 int isc_mc_init(struct isc_device *isc, u32 ver)
1970 {
1971 const struct of_device_id *match;
1972 int ret;
1973
1974 isc->video_dev.entity.function = MEDIA_ENT_F_IO_V4L;
1975 isc->video_dev.entity.flags = MEDIA_ENT_FL_DEFAULT;
1976 isc->video_dev.entity.ops = &isc_entity_operations;
1977
1978 isc->pads[ISC_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1979
1980 ret = media_entity_pads_init(&isc->video_dev.entity, ISC_PADS_NUM,
1981 isc->pads);
1982 if (ret < 0) {
1983 dev_err(isc->dev, "media entity init failed\n");
1984 return ret;
1985 }
1986
1987 isc->mdev.dev = isc->dev;
1988
1989 match = of_match_node(isc->dev->driver->of_match_table,
1990 isc->dev->of_node);
1991
1992 strscpy(isc->mdev.driver_name, KBUILD_MODNAME,
1993 sizeof(isc->mdev.driver_name));
1994 strscpy(isc->mdev.model, match->compatible, sizeof(isc->mdev.model));
1995 snprintf(isc->mdev.bus_info, sizeof(isc->mdev.bus_info), "platform:%s",
1996 isc->v4l2_dev.name);
1997 isc->mdev.hw_revision = ver;
1998
1999 media_device_init(&isc->mdev);
2000
2001 isc->v4l2_dev.mdev = &isc->mdev;
2002
2003 return isc_scaler_init(isc);
2004 }
2005 EXPORT_SYMBOL_GPL(isc_mc_init);
2006
isc_mc_cleanup(struct isc_device * isc)2007 void isc_mc_cleanup(struct isc_device *isc)
2008 {
2009 media_entity_cleanup(&isc->video_dev.entity);
2010 media_device_cleanup(&isc->mdev);
2011 }
2012 EXPORT_SYMBOL_GPL(isc_mc_cleanup);
2013
2014 /* regmap configuration */
2015 #define MICROCHIP_ISC_REG_MAX 0xd5c
2016 const struct regmap_config microchip_isc_regmap_config = {
2017 .reg_bits = 32,
2018 .reg_stride = 4,
2019 .val_bits = 32,
2020 .max_register = MICROCHIP_ISC_REG_MAX,
2021 };
2022 EXPORT_SYMBOL_GPL(microchip_isc_regmap_config);
2023
2024 MODULE_AUTHOR("Songjun Wu");
2025 MODULE_AUTHOR("Eugen Hristev");
2026 MODULE_DESCRIPTION("Microchip ISC common code base");
2027 MODULE_LICENSE("GPL v2");
2028