1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  */
5 
6 #include <drm/drm_blend.h>
7 #include <drm/drm_fourcc.h>
8 #include <drm/drm_framebuffer.h>
9 
10 #include <linux/clk.h>
11 #include <linux/component.h>
12 #include <linux/module.h>
13 #include <linux/of_device.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/soc/mediatek/mtk-cmdq.h>
18 
19 #include "mtk_disp_drv.h"
20 #include "mtk_drm_crtc.h"
21 #include "mtk_drm_ddp_comp.h"
22 #include "mtk_drm_drv.h"
23 
24 #define DISP_REG_OVL_INTEN			0x0004
25 #define OVL_FME_CPL_INT					BIT(1)
26 #define DISP_REG_OVL_INTSTA			0x0008
27 #define DISP_REG_OVL_EN				0x000c
28 #define DISP_REG_OVL_RST			0x0014
29 #define DISP_REG_OVL_ROI_SIZE			0x0020
30 #define DISP_REG_OVL_DATAPATH_CON		0x0024
31 #define OVL_LAYER_SMI_ID_EN				BIT(0)
32 #define OVL_BGCLR_SEL_IN				BIT(2)
33 #define OVL_LAYER_AFBC_EN(n)				BIT(4+n)
34 #define DISP_REG_OVL_ROI_BGCLR			0x0028
35 #define DISP_REG_OVL_SRC_CON			0x002c
36 #define DISP_REG_OVL_CON(n)			(0x0030 + 0x20 * (n))
37 #define DISP_REG_OVL_SRC_SIZE(n)		(0x0038 + 0x20 * (n))
38 #define DISP_REG_OVL_OFFSET(n)			(0x003c + 0x20 * (n))
39 #define DISP_REG_OVL_PITCH_MSB(n)		(0x0040 + 0x20 * (n))
40 #define OVL_PITCH_MSB_2ND_SUBBUF			BIT(16)
41 #define DISP_REG_OVL_PITCH(n)			(0x0044 + 0x20 * (n))
42 #define DISP_REG_OVL_RDMA_CTRL(n)		(0x00c0 + 0x20 * (n))
43 #define DISP_REG_OVL_RDMA_GMC(n)		(0x00c8 + 0x20 * (n))
44 #define DISP_REG_OVL_ADDR_MT2701		0x0040
45 #define DISP_REG_OVL_ADDR_MT8173		0x0f40
46 #define DISP_REG_OVL_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n))
47 #define DISP_REG_OVL_HDR_ADDR(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x04)
48 #define DISP_REG_OVL_HDR_PITCH(ovl, n)		((ovl)->data->addr + 0x20 * (n) + 0x08)
49 
50 #define GMC_THRESHOLD_BITS	16
51 #define GMC_THRESHOLD_HIGH	((1 << GMC_THRESHOLD_BITS) / 4)
52 #define GMC_THRESHOLD_LOW	((1 << GMC_THRESHOLD_BITS) / 8)
53 
54 #define OVL_CON_BYTE_SWAP	BIT(24)
55 #define OVL_CON_MTX_YUV_TO_RGB	(6 << 16)
56 #define OVL_CON_CLRFMT_RGB	(1 << 12)
57 #define OVL_CON_CLRFMT_RGBA8888	(2 << 12)
58 #define OVL_CON_CLRFMT_ARGB8888	(3 << 12)
59 #define OVL_CON_CLRFMT_UYVY	(4 << 12)
60 #define OVL_CON_CLRFMT_YUYV	(5 << 12)
61 #define OVL_CON_CLRFMT_RGB565(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
62 					0 : OVL_CON_CLRFMT_RGB)
63 #define OVL_CON_CLRFMT_RGB888(ovl)	((ovl)->data->fmt_rgb565_is_0 ? \
64 					OVL_CON_CLRFMT_RGB : 0)
65 #define	OVL_CON_AEN		BIT(8)
66 #define	OVL_CON_ALPHA		0xff
67 #define	OVL_CON_VIRT_FLIP	BIT(9)
68 #define	OVL_CON_HORZ_FLIP	BIT(10)
69 
70 struct mtk_disp_ovl_data {
71 	unsigned int addr;
72 	unsigned int gmc_bits;
73 	unsigned int layer_nr;
74 	bool fmt_rgb565_is_0;
75 	bool smi_id_en;
76 	bool supports_afbc;
77 };
78 
79 /*
80  * struct mtk_disp_ovl - DISP_OVL driver structure
81  * @crtc: associated crtc to report vblank events to
82  * @data: platform data
83  */
84 struct mtk_disp_ovl {
85 	struct drm_crtc			*crtc;
86 	struct clk			*clk;
87 	void __iomem			*regs;
88 	struct cmdq_client_reg		cmdq_reg;
89 	const struct mtk_disp_ovl_data	*data;
90 	void				(*vblank_cb)(void *data);
91 	void				*vblank_cb_data;
92 };
93 
mtk_disp_ovl_irq_handler(int irq,void * dev_id)94 static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
95 {
96 	struct mtk_disp_ovl *priv = dev_id;
97 
98 	/* Clear frame completion interrupt */
99 	writel(0x0, priv->regs + DISP_REG_OVL_INTSTA);
100 
101 	if (!priv->vblank_cb)
102 		return IRQ_NONE;
103 
104 	priv->vblank_cb(priv->vblank_cb_data);
105 
106 	return IRQ_HANDLED;
107 }
108 
mtk_ovl_register_vblank_cb(struct device * dev,void (* vblank_cb)(void *),void * vblank_cb_data)109 void mtk_ovl_register_vblank_cb(struct device *dev,
110 				void (*vblank_cb)(void *),
111 				void *vblank_cb_data)
112 {
113 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
114 
115 	ovl->vblank_cb = vblank_cb;
116 	ovl->vblank_cb_data = vblank_cb_data;
117 }
118 
mtk_ovl_unregister_vblank_cb(struct device * dev)119 void mtk_ovl_unregister_vblank_cb(struct device *dev)
120 {
121 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
122 
123 	ovl->vblank_cb = NULL;
124 	ovl->vblank_cb_data = NULL;
125 }
126 
mtk_ovl_enable_vblank(struct device * dev)127 void mtk_ovl_enable_vblank(struct device *dev)
128 {
129 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
130 
131 	writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
132 	writel_relaxed(OVL_FME_CPL_INT, ovl->regs + DISP_REG_OVL_INTEN);
133 }
134 
mtk_ovl_disable_vblank(struct device * dev)135 void mtk_ovl_disable_vblank(struct device *dev)
136 {
137 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
138 
139 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
140 }
141 
mtk_ovl_clk_enable(struct device * dev)142 int mtk_ovl_clk_enable(struct device *dev)
143 {
144 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
145 
146 	return clk_prepare_enable(ovl->clk);
147 }
148 
mtk_ovl_clk_disable(struct device * dev)149 void mtk_ovl_clk_disable(struct device *dev)
150 {
151 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
152 
153 	clk_disable_unprepare(ovl->clk);
154 }
155 
mtk_ovl_start(struct device * dev)156 void mtk_ovl_start(struct device *dev)
157 {
158 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
159 
160 	if (ovl->data->smi_id_en) {
161 		unsigned int reg;
162 
163 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
164 		reg = reg | OVL_LAYER_SMI_ID_EN;
165 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
166 	}
167 	writel_relaxed(0x1, ovl->regs + DISP_REG_OVL_EN);
168 }
169 
mtk_ovl_stop(struct device * dev)170 void mtk_ovl_stop(struct device *dev)
171 {
172 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
173 
174 	writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_EN);
175 	if (ovl->data->smi_id_en) {
176 		unsigned int reg;
177 
178 		reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
179 		reg = reg & ~OVL_LAYER_SMI_ID_EN;
180 		writel_relaxed(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
181 	}
182 }
183 
mtk_ovl_set_afbc(struct mtk_disp_ovl * ovl,struct cmdq_pkt * cmdq_pkt,int idx,bool enabled)184 static void mtk_ovl_set_afbc(struct mtk_disp_ovl *ovl, struct cmdq_pkt *cmdq_pkt,
185 			     int idx, bool enabled)
186 {
187 	mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0,
188 			   &ovl->cmdq_reg, ovl->regs,
189 			   DISP_REG_OVL_DATAPATH_CON, OVL_LAYER_AFBC_EN(idx));
190 }
191 
mtk_ovl_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)192 void mtk_ovl_config(struct device *dev, unsigned int w,
193 		    unsigned int h, unsigned int vrefresh,
194 		    unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
195 {
196 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
197 
198 	if (w != 0 && h != 0)
199 		mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl->cmdq_reg, ovl->regs,
200 				      DISP_REG_OVL_ROI_SIZE);
201 	mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_ROI_BGCLR);
202 
203 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
204 	mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST);
205 }
206 
mtk_ovl_layer_nr(struct device * dev)207 unsigned int mtk_ovl_layer_nr(struct device *dev)
208 {
209 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
210 
211 	return ovl->data->layer_nr;
212 }
213 
mtk_ovl_supported_rotations(struct device * dev)214 unsigned int mtk_ovl_supported_rotations(struct device *dev)
215 {
216 	return DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
217 	       DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
218 }
219 
mtk_ovl_layer_check(struct device * dev,unsigned int idx,struct mtk_plane_state * mtk_state)220 int mtk_ovl_layer_check(struct device *dev, unsigned int idx,
221 			struct mtk_plane_state *mtk_state)
222 {
223 	struct drm_plane_state *state = &mtk_state->base;
224 	unsigned int rotation = 0;
225 
226 	rotation = drm_rotation_simplify(state->rotation,
227 					 DRM_MODE_ROTATE_0 |
228 					 DRM_MODE_REFLECT_X |
229 					 DRM_MODE_REFLECT_Y);
230 	rotation &= ~DRM_MODE_ROTATE_0;
231 
232 	/* We can only do reflection, not rotation */
233 	if ((rotation & DRM_MODE_ROTATE_MASK) != 0)
234 		return -EINVAL;
235 
236 	/*
237 	 * TODO: Rotating/reflecting YUV buffers is not supported at this time.
238 	 *	 Only RGB[AX] variants are supported.
239 	 */
240 	if (state->fb->format->is_yuv && rotation != 0)
241 		return -EINVAL;
242 
243 	state->rotation = rotation;
244 
245 	return 0;
246 }
247 
mtk_ovl_layer_on(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)248 void mtk_ovl_layer_on(struct device *dev, unsigned int idx,
249 		      struct cmdq_pkt *cmdq_pkt)
250 {
251 	unsigned int gmc_thrshd_l;
252 	unsigned int gmc_thrshd_h;
253 	unsigned int gmc_value;
254 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
255 
256 	mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs,
257 		      DISP_REG_OVL_RDMA_CTRL(idx));
258 	gmc_thrshd_l = GMC_THRESHOLD_LOW >>
259 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
260 	gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
261 		      (GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
262 	if (ovl->data->gmc_bits == 10)
263 		gmc_value = gmc_thrshd_h | gmc_thrshd_h << 16;
264 	else
265 		gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
266 			    gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
267 	mtk_ddp_write(cmdq_pkt, gmc_value,
268 		      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RDMA_GMC(idx));
269 	mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs,
270 			   DISP_REG_OVL_SRC_CON, BIT(idx));
271 }
272 
mtk_ovl_layer_off(struct device * dev,unsigned int idx,struct cmdq_pkt * cmdq_pkt)273 void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
274 		       struct cmdq_pkt *cmdq_pkt)
275 {
276 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
277 
278 	mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
279 			   DISP_REG_OVL_SRC_CON, BIT(idx));
280 	mtk_ddp_write(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs,
281 		      DISP_REG_OVL_RDMA_CTRL(idx));
282 }
283 
ovl_fmt_convert(struct mtk_disp_ovl * ovl,unsigned int fmt)284 static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
285 {
286 	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
287 	 * is defined in mediatek HW data sheet.
288 	 * The alphabet order in XXX is no relation to data
289 	 * arrangement in memory.
290 	 */
291 	switch (fmt) {
292 	default:
293 	case DRM_FORMAT_RGB565:
294 		return OVL_CON_CLRFMT_RGB565(ovl);
295 	case DRM_FORMAT_BGR565:
296 		return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP;
297 	case DRM_FORMAT_RGB888:
298 		return OVL_CON_CLRFMT_RGB888(ovl);
299 	case DRM_FORMAT_BGR888:
300 		return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP;
301 	case DRM_FORMAT_RGBX8888:
302 	case DRM_FORMAT_RGBA8888:
303 		return OVL_CON_CLRFMT_ARGB8888;
304 	case DRM_FORMAT_BGRX8888:
305 	case DRM_FORMAT_BGRA8888:
306 		return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
307 	case DRM_FORMAT_XRGB8888:
308 	case DRM_FORMAT_ARGB8888:
309 		return OVL_CON_CLRFMT_RGBA8888;
310 	case DRM_FORMAT_XBGR8888:
311 	case DRM_FORMAT_ABGR8888:
312 		return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
313 	case DRM_FORMAT_UYVY:
314 		return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB;
315 	case DRM_FORMAT_YUYV:
316 		return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB;
317 	}
318 }
319 
mtk_ovl_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt)320 void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
321 			  struct mtk_plane_state *state,
322 			  struct cmdq_pkt *cmdq_pkt)
323 {
324 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
325 	struct mtk_plane_pending_state *pending = &state->pending;
326 	unsigned int addr = pending->addr;
327 	unsigned int hdr_addr = pending->hdr_addr;
328 	unsigned int pitch = pending->pitch;
329 	unsigned int hdr_pitch = pending->hdr_pitch;
330 	unsigned int fmt = pending->format;
331 	unsigned int offset = (pending->y << 16) | pending->x;
332 	unsigned int src_size = (pending->height << 16) | pending->width;
333 	unsigned int con;
334 	bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR;
335 	union overlay_pitch {
336 		struct split_pitch {
337 			u16 lsb;
338 			u16 msb;
339 		} split_pitch;
340 		u32 pitch;
341 	} overlay_pitch;
342 
343 	overlay_pitch.pitch = pitch;
344 
345 	if (!pending->enable) {
346 		mtk_ovl_layer_off(dev, idx, cmdq_pkt);
347 		return;
348 	}
349 
350 	con = ovl_fmt_convert(ovl, fmt);
351 	if (state->base.fb && state->base.fb->format->has_alpha)
352 		con |= OVL_CON_AEN | OVL_CON_ALPHA;
353 
354 	if (pending->rotation & DRM_MODE_REFLECT_Y) {
355 		con |= OVL_CON_VIRT_FLIP;
356 		addr += (pending->height - 1) * pending->pitch;
357 	}
358 
359 	if (pending->rotation & DRM_MODE_REFLECT_X) {
360 		con |= OVL_CON_HORZ_FLIP;
361 		addr += pending->pitch - 1;
362 	}
363 
364 	if (ovl->data->supports_afbc)
365 		mtk_ovl_set_afbc(ovl, cmdq_pkt, idx, is_afbc);
366 
367 	mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
368 			      DISP_REG_OVL_CON(idx));
369 	mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, &ovl->cmdq_reg, ovl->regs,
370 			      DISP_REG_OVL_PITCH(idx));
371 	mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
372 			      DISP_REG_OVL_SRC_SIZE(idx));
373 	mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl->regs,
374 			      DISP_REG_OVL_OFFSET(idx));
375 	mtk_ddp_write_relaxed(cmdq_pkt, addr, &ovl->cmdq_reg, ovl->regs,
376 			      DISP_REG_OVL_ADDR(ovl, idx));
377 
378 	if (is_afbc) {
379 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_addr, &ovl->cmdq_reg, ovl->regs,
380 				      DISP_REG_OVL_HDR_ADDR(ovl, idx));
381 		mtk_ddp_write_relaxed(cmdq_pkt,
382 				      OVL_PITCH_MSB_2ND_SUBBUF | overlay_pitch.split_pitch.msb,
383 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
384 		mtk_ddp_write_relaxed(cmdq_pkt, hdr_pitch, &ovl->cmdq_reg, ovl->regs,
385 				      DISP_REG_OVL_HDR_PITCH(ovl, idx));
386 	} else {
387 		mtk_ddp_write_relaxed(cmdq_pkt,
388 				      overlay_pitch.split_pitch.msb,
389 				      &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH_MSB(idx));
390 	}
391 
392 	mtk_ovl_layer_on(dev, idx, cmdq_pkt);
393 }
394 
mtk_ovl_bgclr_in_on(struct device * dev)395 void mtk_ovl_bgclr_in_on(struct device *dev)
396 {
397 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
398 	unsigned int reg;
399 
400 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
401 	reg = reg | OVL_BGCLR_SEL_IN;
402 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
403 }
404 
mtk_ovl_bgclr_in_off(struct device * dev)405 void mtk_ovl_bgclr_in_off(struct device *dev)
406 {
407 	struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
408 	unsigned int reg;
409 
410 	reg = readl(ovl->regs + DISP_REG_OVL_DATAPATH_CON);
411 	reg = reg & ~OVL_BGCLR_SEL_IN;
412 	writel(reg, ovl->regs + DISP_REG_OVL_DATAPATH_CON);
413 }
414 
mtk_disp_ovl_bind(struct device * dev,struct device * master,void * data)415 static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
416 			     void *data)
417 {
418 	return 0;
419 }
420 
mtk_disp_ovl_unbind(struct device * dev,struct device * master,void * data)421 static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
422 				void *data)
423 {
424 }
425 
426 static const struct component_ops mtk_disp_ovl_component_ops = {
427 	.bind	= mtk_disp_ovl_bind,
428 	.unbind = mtk_disp_ovl_unbind,
429 };
430 
mtk_disp_ovl_probe(struct platform_device * pdev)431 static int mtk_disp_ovl_probe(struct platform_device *pdev)
432 {
433 	struct device *dev = &pdev->dev;
434 	struct mtk_disp_ovl *priv;
435 	struct resource *res;
436 	int irq;
437 	int ret;
438 
439 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
440 	if (!priv)
441 		return -ENOMEM;
442 
443 	irq = platform_get_irq(pdev, 0);
444 	if (irq < 0)
445 		return irq;
446 
447 	priv->clk = devm_clk_get(dev, NULL);
448 	if (IS_ERR(priv->clk)) {
449 		dev_err(dev, "failed to get ovl clk\n");
450 		return PTR_ERR(priv->clk);
451 	}
452 
453 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
454 	priv->regs = devm_ioremap_resource(dev, res);
455 	if (IS_ERR(priv->regs)) {
456 		dev_err(dev, "failed to ioremap ovl\n");
457 		return PTR_ERR(priv->regs);
458 	}
459 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
460 	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
461 	if (ret)
462 		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
463 #endif
464 
465 	priv->data = of_device_get_match_data(dev);
466 	platform_set_drvdata(pdev, priv);
467 
468 	ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
469 			       IRQF_TRIGGER_NONE, dev_name(dev), priv);
470 	if (ret < 0) {
471 		dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
472 		return ret;
473 	}
474 
475 	pm_runtime_enable(dev);
476 
477 	ret = component_add(dev, &mtk_disp_ovl_component_ops);
478 	if (ret) {
479 		pm_runtime_disable(dev);
480 		dev_err(dev, "Failed to add component: %d\n", ret);
481 	}
482 
483 	return ret;
484 }
485 
mtk_disp_ovl_remove(struct platform_device * pdev)486 static int mtk_disp_ovl_remove(struct platform_device *pdev)
487 {
488 	component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
489 	pm_runtime_disable(&pdev->dev);
490 
491 	return 0;
492 }
493 
494 static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
495 	.addr = DISP_REG_OVL_ADDR_MT2701,
496 	.gmc_bits = 8,
497 	.layer_nr = 4,
498 	.fmt_rgb565_is_0 = false,
499 };
500 
501 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
502 	.addr = DISP_REG_OVL_ADDR_MT8173,
503 	.gmc_bits = 8,
504 	.layer_nr = 4,
505 	.fmt_rgb565_is_0 = true,
506 };
507 
508 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
509 	.addr = DISP_REG_OVL_ADDR_MT8173,
510 	.gmc_bits = 10,
511 	.layer_nr = 4,
512 	.fmt_rgb565_is_0 = true,
513 };
514 
515 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
516 	.addr = DISP_REG_OVL_ADDR_MT8173,
517 	.gmc_bits = 10,
518 	.layer_nr = 2,
519 	.fmt_rgb565_is_0 = true,
520 };
521 
522 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
523 	.addr = DISP_REG_OVL_ADDR_MT8173,
524 	.gmc_bits = 10,
525 	.layer_nr = 4,
526 	.fmt_rgb565_is_0 = true,
527 	.smi_id_en = true,
528 };
529 
530 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
531 	.addr = DISP_REG_OVL_ADDR_MT8173,
532 	.gmc_bits = 10,
533 	.layer_nr = 2,
534 	.fmt_rgb565_is_0 = true,
535 	.smi_id_en = true,
536 };
537 
538 static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
539 	.addr = DISP_REG_OVL_ADDR_MT8173,
540 	.gmc_bits = 10,
541 	.layer_nr = 4,
542 	.fmt_rgb565_is_0 = true,
543 	.smi_id_en = true,
544 	.supports_afbc = true,
545 };
546 
547 static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
548 	{ .compatible = "mediatek,mt2701-disp-ovl",
549 	  .data = &mt2701_ovl_driver_data},
550 	{ .compatible = "mediatek,mt8173-disp-ovl",
551 	  .data = &mt8173_ovl_driver_data},
552 	{ .compatible = "mediatek,mt8183-disp-ovl",
553 	  .data = &mt8183_ovl_driver_data},
554 	{ .compatible = "mediatek,mt8183-disp-ovl-2l",
555 	  .data = &mt8183_ovl_2l_driver_data},
556 	{ .compatible = "mediatek,mt8192-disp-ovl",
557 	  .data = &mt8192_ovl_driver_data},
558 	{ .compatible = "mediatek,mt8192-disp-ovl-2l",
559 	  .data = &mt8192_ovl_2l_driver_data},
560 	{ .compatible = "mediatek,mt8195-disp-ovl",
561 	  .data = &mt8195_ovl_driver_data},
562 	{},
563 };
564 MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
565 
566 struct platform_driver mtk_disp_ovl_driver = {
567 	.probe		= mtk_disp_ovl_probe,
568 	.remove		= mtk_disp_ovl_remove,
569 	.driver		= {
570 		.name	= "mediatek-disp-ovl",
571 		.owner	= THIS_MODULE,
572 		.of_match_table = mtk_disp_ovl_driver_dt_match,
573 	},
574 };
575