1 /*
2 * Copyright (c) 2015 - 2020, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the copyright holder nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef NRF_UARTE_H__
33 #define NRF_UARTE_H__
34
35 #include <nrfx.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 #define NRF_UARTE_PSEL_DISCONNECTED 0xFFFFFFFF
42
43 /**
44 * @defgroup nrf_uarte_hal UARTE HAL
45 * @{
46 * @ingroup nrf_uarte
47 * @brief Hardware access layer for managing the UARTE peripheral.
48 */
49
50 /** @brief UARTE tasks. */
51 typedef enum
52 {
53 NRF_UARTE_TASK_STARTRX = offsetof(NRF_UARTE_Type, TASKS_STARTRX), ///< Start UART receiver.
54 NRF_UARTE_TASK_STOPRX = offsetof(NRF_UARTE_Type, TASKS_STOPRX), ///< Stop UART receiver.
55 NRF_UARTE_TASK_STARTTX = offsetof(NRF_UARTE_Type, TASKS_STARTTX), ///< Start UART transmitter.
56 NRF_UARTE_TASK_STOPTX = offsetof(NRF_UARTE_Type, TASKS_STOPTX), ///< Stop UART transmitter.
57 NRF_UARTE_TASK_FLUSHRX = offsetof(NRF_UARTE_Type, TASKS_FLUSHRX) ///< Flush RX FIFO in RX buffer.
58 } nrf_uarte_task_t;
59
60 /** @brief UARTE events. */
61 typedef enum
62 {
63 NRF_UARTE_EVENT_CTS = offsetof(NRF_UARTE_Type, EVENTS_CTS), ///< CTS is activated.
64 NRF_UARTE_EVENT_NCTS = offsetof(NRF_UARTE_Type, EVENTS_NCTS), ///< CTS is deactivated.
65 NRF_UARTE_EVENT_RXDRDY = offsetof(NRF_UARTE_Type, EVENTS_RXDRDY), ///< Data received in RXD (but potentially not yet transferred to Data RAM).
66 NRF_UARTE_EVENT_ENDRX = offsetof(NRF_UARTE_Type, EVENTS_ENDRX), ///< Receive buffer is filled up.
67 NRF_UARTE_EVENT_TXDRDY = offsetof(NRF_UARTE_Type, EVENTS_TXDRDY), ///< Data sent from TXD.
68 NRF_UARTE_EVENT_ENDTX = offsetof(NRF_UARTE_Type, EVENTS_ENDTX), ///< Last TX byte transmitted.
69 NRF_UARTE_EVENT_ERROR = offsetof(NRF_UARTE_Type, EVENTS_ERROR), ///< Error detected.
70 NRF_UARTE_EVENT_RXTO = offsetof(NRF_UARTE_Type, EVENTS_RXTO), ///< Receiver timeout.
71 NRF_UARTE_EVENT_RXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_RXSTARTED), ///< Receiver has started.
72 NRF_UARTE_EVENT_TXSTARTED = offsetof(NRF_UARTE_Type, EVENTS_TXSTARTED), ///< Transmitter has started.
73 NRF_UARTE_EVENT_TXSTOPPED = offsetof(NRF_UARTE_Type, EVENTS_TXSTOPPED) ///< Transmitted stopped.
74 } nrf_uarte_event_t;
75
76 /** @brief Types of UARTE shortcuts. */
77 typedef enum
78 {
79 NRF_UARTE_SHORT_ENDRX_STARTRX = UARTE_SHORTS_ENDRX_STARTRX_Msk, ///< Shortcut between ENDRX event and STARTRX task.
80 NRF_UARTE_SHORT_ENDRX_STOPRX = UARTE_SHORTS_ENDRX_STOPRX_Msk ///< Shortcut between ENDRX event and STOPRX task.
81 } nrf_uarte_short_t;
82
83
84 /** @brief UARTE interrupts. */
85 typedef enum
86 {
87 NRF_UARTE_INT_CTS_MASK = UARTE_INTENSET_CTS_Msk, ///< Interrupt on CTS event.
88 NRF_UARTE_INT_NCTS_MASK = UARTE_INTENSET_NCTS_Msk, ///< Interrupt on NCTS event.
89 NRF_UARTE_INT_RXDRDY_MASK = UARTE_INTENSET_RXDRDY_Msk, ///< Interrupt on RXDRDY event.
90 NRF_UARTE_INT_ENDRX_MASK = UARTE_INTENSET_ENDRX_Msk, ///< Interrupt on ENDRX event.
91 NRF_UARTE_INT_TXDRDY_MASK = UARTE_INTENSET_TXDRDY_Msk, ///< Interrupt on TXDRDY event.
92 NRF_UARTE_INT_ENDTX_MASK = UARTE_INTENSET_ENDTX_Msk, ///< Interrupt on ENDTX event.
93 NRF_UARTE_INT_ERROR_MASK = UARTE_INTENSET_ERROR_Msk, ///< Interrupt on ERROR event.
94 NRF_UARTE_INT_RXTO_MASK = UARTE_INTENSET_RXTO_Msk, ///< Interrupt on RXTO event.
95 NRF_UARTE_INT_RXSTARTED_MASK = UARTE_INTENSET_RXSTARTED_Msk, ///< Interrupt on RXSTARTED event.
96 NRF_UARTE_INT_TXSTARTED_MASK = UARTE_INTENSET_TXSTARTED_Msk, ///< Interrupt on TXSTARTED event.
97 NRF_UARTE_INT_TXSTOPPED_MASK = UARTE_INTENSET_TXSTOPPED_Msk ///< Interrupt on TXSTOPPED event.
98 } nrf_uarte_int_mask_t;
99
100 /** @brief Baudrates supported by UARTE. */
101 typedef enum
102 {
103 NRF_UARTE_BAUDRATE_1200 = UARTE_BAUDRATE_BAUDRATE_Baud1200, ///< 1200 baud.
104 NRF_UARTE_BAUDRATE_2400 = UARTE_BAUDRATE_BAUDRATE_Baud2400, ///< 2400 baud.
105 NRF_UARTE_BAUDRATE_4800 = UARTE_BAUDRATE_BAUDRATE_Baud4800, ///< 4800 baud.
106 NRF_UARTE_BAUDRATE_9600 = UARTE_BAUDRATE_BAUDRATE_Baud9600, ///< 9600 baud.
107 NRF_UARTE_BAUDRATE_14400 = UARTE_BAUDRATE_BAUDRATE_Baud14400, ///< 14400 baud.
108 NRF_UARTE_BAUDRATE_19200 = UARTE_BAUDRATE_BAUDRATE_Baud19200, ///< 19200 baud.
109 NRF_UARTE_BAUDRATE_28800 = UARTE_BAUDRATE_BAUDRATE_Baud28800, ///< 28800 baud.
110 NRF_UARTE_BAUDRATE_31250 = UARTE_BAUDRATE_BAUDRATE_Baud31250, ///< 31250 baud.
111 NRF_UARTE_BAUDRATE_38400 = UARTE_BAUDRATE_BAUDRATE_Baud38400, ///< 38400 baud.
112 NRF_UARTE_BAUDRATE_56000 = UARTE_BAUDRATE_BAUDRATE_Baud56000, ///< 56000 baud.
113 NRF_UARTE_BAUDRATE_57600 = UARTE_BAUDRATE_BAUDRATE_Baud57600, ///< 57600 baud.
114 NRF_UARTE_BAUDRATE_76800 = UARTE_BAUDRATE_BAUDRATE_Baud76800, ///< 76800 baud.
115 NRF_UARTE_BAUDRATE_115200 = UARTE_BAUDRATE_BAUDRATE_Baud115200, ///< 115200 baud.
116 NRF_UARTE_BAUDRATE_230400 = UARTE_BAUDRATE_BAUDRATE_Baud230400, ///< 230400 baud.
117 NRF_UARTE_BAUDRATE_250000 = UARTE_BAUDRATE_BAUDRATE_Baud250000, ///< 250000 baud.
118 NRF_UARTE_BAUDRATE_460800 = UARTE_BAUDRATE_BAUDRATE_Baud460800, ///< 460800 baud.
119 NRF_UARTE_BAUDRATE_921600 = UARTE_BAUDRATE_BAUDRATE_Baud921600, ///< 921600 baud.
120 NRF_UARTE_BAUDRATE_1000000 = UARTE_BAUDRATE_BAUDRATE_Baud1M ///< 1000000 baud.
121 } nrf_uarte_baudrate_t;
122
123 /** @brief Types of UARTE error masks. */
124 typedef enum
125 {
126 NRF_UARTE_ERROR_OVERRUN_MASK = UARTE_ERRORSRC_OVERRUN_Msk, ///< Overrun error.
127 NRF_UARTE_ERROR_PARITY_MASK = UARTE_ERRORSRC_PARITY_Msk, ///< Parity error.
128 NRF_UARTE_ERROR_FRAMING_MASK = UARTE_ERRORSRC_FRAMING_Msk, ///< Framing error.
129 NRF_UARTE_ERROR_BREAK_MASK = UARTE_ERRORSRC_BREAK_Msk ///< Break error.
130 } nrf_uarte_error_mask_t;
131
132 /** @brief Types of UARTE parity modes. */
133 typedef enum
134 {
135 NRF_UARTE_PARITY_EXCLUDED = UARTE_CONFIG_PARITY_Excluded << UARTE_CONFIG_PARITY_Pos, ///< Parity excluded.
136 NRF_UARTE_PARITY_INCLUDED = UARTE_CONFIG_PARITY_Included << UARTE_CONFIG_PARITY_Pos ///< Parity included.
137 } nrf_uarte_parity_t;
138
139 /** @brief Types of UARTE flow control modes. */
140 typedef enum
141 {
142 NRF_UARTE_HWFC_DISABLED = UARTE_CONFIG_HWFC_Disabled << UARTE_CONFIG_HWFC_Pos, ///< Hardware flow control disabled.
143 NRF_UARTE_HWFC_ENABLED = UARTE_CONFIG_HWFC_Enabled << UARTE_CONFIG_HWFC_Pos ///< Hardware flow control enabled.
144 } nrf_uarte_hwfc_t;
145
146 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
147 /** @brief Types of UARTE stop bit modes. */
148 typedef enum
149 {
150 NRF_UARTE_STOP_ONE = UARTE_CONFIG_STOP_One << UARTE_CONFIG_STOP_Pos, ///< One stop bit.
151 NRF_UARTE_STOP_TWO = UARTE_CONFIG_STOP_Two << UARTE_CONFIG_STOP_Pos ///< Two stop bits.
152 } nrf_uarte_stop_t;
153 #endif
154
155 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
156 /** @brief Types of UARTE parity types. */
157 typedef enum
158 {
159 NRF_UARTE_PARITYTYPE_EVEN = UARTE_CONFIG_PARITYTYPE_Even << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity even.
160 NRF_UARTE_PARITYTYPE_ODD = UARTE_CONFIG_PARITYTYPE_Odd << UARTE_CONFIG_PARITYTYPE_Pos, ///< Parity odd.
161 } nrf_uarte_paritytype_t;
162 #endif
163
164 /** @brief Structure for UARTE transmission configuration. */
165 typedef struct
166 {
167 nrf_uarte_hwfc_t hwfc; ///< Flow control configuration.
168 nrf_uarte_parity_t parity; ///< Parity configuration.
169 #if defined(UARTE_CONFIG_STOP_Msk) || defined(__NRFX_DOXYGEN__)
170 nrf_uarte_stop_t stop; ///< Stop bits.
171 #endif
172 #if defined(UARTE_CONFIG_PARITYTYPE_Msk) || defined(__NRFX_DOXYGEN__)
173 nrf_uarte_paritytype_t paritytype; ///< Parity type.
174 #endif
175 } nrf_uarte_config_t;
176
177 /**
178 * @brief Function for clearing a specific UARTE event.
179 *
180 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
181 * @param[in] event Event to clear.
182 */
183 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event);
184
185 /**
186 * @brief Function for retrieving the state of the UARTE event.
187 *
188 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
189 * @param[in] event Event to be checked.
190 *
191 * @retval true The event has been generated.
192 * @retval false The event has not been generated.
193 */
194 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
195 nrf_uarte_event_t event);
196
197 /**
198 * @brief Function for returning the address of the specified UARTE event register.
199 *
200 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
201 * @param[in] event The specified event.
202 *
203 * @return Address of specified event register.
204 */
205 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
206 nrf_uarte_event_t event);
207
208 /**
209 * @brief Function for enabling UARTE shortcuts.
210 *
211 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
212 * @param[in] mask Shortcuts to be enabled.
213 */
214 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
215
216 /**
217 * @brief Function for disabling UARTE shortcuts.
218 *
219 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
220 * @param[in] mask Shortcuts to be disabled.
221 */
222 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
223
224 /**
225 * @brief Function for enabling UARTE interrupts.
226 *
227 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
228 * @param[in] mask Mask of interrupts to be enabled.
229 */
230 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask);
231
232 /**
233 * @brief Function for checking if the specified interrupts are enabled.
234 *
235 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
236 * @param[in] mask Mask of interrupts to be checked.
237 *
238 * @return Mask of enabled interrupts.
239 */
240 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask);
241
242 /**
243 * @brief Function for disabling the specified interrupts.
244 *
245 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
246 * @param[in] mask Mask of interrupts to be disabled.
247 */
248 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask);
249
250 #if defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
251 /**
252 * @brief Function for setting the subscribe configuration for a given
253 * UARTE task.
254 *
255 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
256 * @param[in] task Task for which to set the configuration.
257 * @param[in] channel Channel through which to subscribe events.
258 */
259 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
260 nrf_uarte_task_t task,
261 uint8_t channel);
262
263 /**
264 * @brief Function for clearing the subscribe configuration for a given
265 * UARTE task.
266 *
267 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
268 * @param[in] task Task for which to clear the configuration.
269 */
270 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
271 nrf_uarte_task_t task);
272
273 /**
274 * @brief Function for setting the publish configuration for a given
275 * UARTE event.
276 *
277 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
278 * @param[in] event Event for which to set the configuration.
279 * @param[in] channel Channel through which to publish the event.
280 */
281 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
282 nrf_uarte_event_t event,
283 uint8_t channel);
284
285 /**
286 * @brief Function for clearing the publish configuration for a given
287 * UARTE event.
288 *
289 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
290 * @param[in] event Event for which to clear the configuration.
291 */
292 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
293 nrf_uarte_event_t event);
294 #endif // defined(DPPI_PRESENT) || defined(__NRFX_DOXYGEN__)
295
296 /**
297 * @brief Function for getting error source mask. Function is clearing error source flags after reading.
298 *
299 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
300 *
301 * @return Mask with error source flags.
302 */
303 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg);
304
305 /**
306 * @brief Function for enabling UARTE.
307 *
308 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
309 */
310 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg);
311
312 /**
313 * @brief Function for disabling UARTE.
314 *
315 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
316 */
317 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg);
318
319 /**
320 * @brief Function for configuring TX/RX pins.
321 *
322 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
323 * @param[in] pseltxd TXD pin number.
324 * @param[in] pselrxd RXD pin number.
325 */
326 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
327 uint32_t pseltxd,
328 uint32_t pselrxd);
329
330 /**
331 * @brief Function for disconnecting TX/RX pins.
332 *
333 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
334 */
335 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
336
337 /**
338 * @brief Function for getting TX pin selection.
339 *
340 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
341 *
342 * @return TX pin selection.
343 */
344 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg);
345
346 /**
347 * @brief Function for getting RX pin selection.
348 *
349 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
350 *
351 * @return RX pin selection.
352 */
353 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg);
354
355 /**
356 * @brief Function for getting RTS pin selection.
357 *
358 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
359 *
360 * @return RTS pin selection.
361 */
362 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg);
363
364 /**
365 * @brief Function for getting CTS pin selection.
366 *
367 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
368 *
369 * @return CTS pin selection.
370 */
371 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg);
372
373 /**
374 * @brief Function for configuring flow control pins.
375 *
376 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
377 * @param[in] pselrts RTS pin number.
378 * @param[in] pselcts CTS pin number.
379 */
380 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
381 uint32_t pselrts,
382 uint32_t pselcts);
383
384 /**
385 * @brief Function for disconnecting flow control pins.
386 *
387 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
388 */
389 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg);
390
391 /**
392 * @brief Function for starting an UARTE task.
393 *
394 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
395 * @param[in] task Task.
396 */
397 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task);
398
399 /**
400 * @brief Function for returning the address of the specified task register.
401 *
402 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
403 * @param[in] task Task.
404 *
405 * @return Task address.
406 */
407 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
408 nrf_uarte_task_t task);
409
410 /**
411 * @brief Function for configuring UARTE.
412 *
413 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
414 * @param[in] p_cfg Pointer to UARTE settings structure.
415 */
416 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
417 nrf_uarte_config_t const * p_cfg);
418
419 /**
420 * @brief Function for setting UARTE baud rate.
421 *
422 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
423 * @param[in] baudrate Baud rate.
424 */
425 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,
426 nrf_uarte_baudrate_t baudrate);
427
428 /**
429 * @brief Function for setting the transmit buffer.
430 *
431 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
432 * @param[in] p_buffer Pointer to the buffer with data to send.
433 * @param[in] length Maximum number of data bytes to transmit.
434 */
435 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
436 uint8_t const * p_buffer,
437 size_t length);
438
439 /**
440 * @brief Function for getting number of bytes transmitted in the last transaction.
441 *
442 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
443 *
444 * @retval Amount of bytes transmitted.
445 */
446 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg);
447
448 /**
449 * @brief Function for setting the receive buffer.
450 *
451 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
452 * @param[in] p_buffer Pointer to the buffer for received data.
453 * @param[in] length Maximum number of data bytes to receive.
454 */
455 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
456 uint8_t * p_buffer,
457 size_t length);
458
459 /**
460 * @brief Function for getting number of bytes received in the last transaction.
461 *
462 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
463 *
464 * @retval Amount of bytes received.
465 */
466 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg);
467
468 #ifndef NRF_DECLARE_ONLY
nrf_uarte_event_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)469 NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
470 {
471 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
472 nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
473 }
474
nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)475 NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
476 nrf_uarte_event_t event)
477 {
478 return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
479 }
480
nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_event_t event)481 NRF_STATIC_INLINE uint32_t nrf_uarte_event_address_get(NRF_UARTE_Type const * p_reg,
482 nrf_uarte_event_t event)
483 {
484 return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
485 }
486
nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg,uint32_t mask)487 NRF_STATIC_INLINE void nrf_uarte_shorts_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
488 {
489 p_reg->SHORTS |= mask;
490 }
491
nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg,uint32_t mask)492 NRF_STATIC_INLINE void nrf_uarte_shorts_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
493 {
494 p_reg->SHORTS &= ~(mask);
495 }
496
nrf_uarte_int_enable(NRF_UARTE_Type * p_reg,uint32_t mask)497 NRF_STATIC_INLINE void nrf_uarte_int_enable(NRF_UARTE_Type * p_reg, uint32_t mask)
498 {
499 p_reg->INTENSET = mask;
500 }
501
nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg,uint32_t mask)502 NRF_STATIC_INLINE uint32_t nrf_uarte_int_enable_check(NRF_UARTE_Type const * p_reg, uint32_t mask)
503 {
504 return p_reg->INTENSET & mask;
505 }
506
nrf_uarte_int_disable(NRF_UARTE_Type * p_reg,uint32_t mask)507 NRF_STATIC_INLINE void nrf_uarte_int_disable(NRF_UARTE_Type * p_reg, uint32_t mask)
508 {
509 p_reg->INTENCLR = mask;
510 }
511
512 #if defined(DPPI_PRESENT)
nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task,uint8_t channel)513 NRF_STATIC_INLINE void nrf_uarte_subscribe_set(NRF_UARTE_Type * p_reg,
514 nrf_uarte_task_t task,
515 uint8_t channel)
516 {
517 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
518 ((uint32_t)channel | UARTE_SUBSCRIBE_STARTRX_EN_Msk);
519 }
520
nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)521 NRF_STATIC_INLINE void nrf_uarte_subscribe_clear(NRF_UARTE_Type * p_reg,
522 nrf_uarte_task_t task)
523 {
524 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
525 }
526
nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event,uint8_t channel)527 NRF_STATIC_INLINE void nrf_uarte_publish_set(NRF_UARTE_Type * p_reg,
528 nrf_uarte_event_t event,
529 uint8_t channel)
530 {
531 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) =
532 ((uint32_t)channel | UARTE_PUBLISH_CTS_EN_Msk);
533 }
534
nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,nrf_uarte_event_t event)535 NRF_STATIC_INLINE void nrf_uarte_publish_clear(NRF_UARTE_Type * p_reg,
536 nrf_uarte_event_t event)
537 {
538 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) event + 0x80uL)) = 0;
539 }
540 #endif // defined(DPPI_PRESENT)
541
nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)542 NRF_STATIC_INLINE uint32_t nrf_uarte_errorsrc_get_and_clear(NRF_UARTE_Type * p_reg)
543 {
544 uint32_t errsrc_mask = p_reg->ERRORSRC;
545 p_reg->ERRORSRC = errsrc_mask;
546 return errsrc_mask;
547 }
548
nrf_uarte_enable(NRF_UARTE_Type * p_reg)549 NRF_STATIC_INLINE void nrf_uarte_enable(NRF_UARTE_Type * p_reg)
550 {
551 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Enabled;
552 }
553
nrf_uarte_disable(NRF_UARTE_Type * p_reg)554 NRF_STATIC_INLINE void nrf_uarte_disable(NRF_UARTE_Type * p_reg)
555 {
556 p_reg->ENABLE = UARTE_ENABLE_ENABLE_Disabled;
557 }
558
nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,uint32_t pseltxd,uint32_t pselrxd)559 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
560 uint32_t pseltxd,
561 uint32_t pselrxd)
562 {
563 p_reg->PSEL.TXD = pseltxd;
564 p_reg->PSEL.RXD = pselrxd;
565 }
566
nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)567 NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg)
568 {
569 nrf_uarte_txrx_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
570 }
571
nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)572 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg)
573 {
574 return p_reg->PSEL.TXD;
575 }
576
nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)577 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg)
578 {
579 return p_reg->PSEL.RXD;
580 }
581
nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)582 NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg)
583 {
584 return p_reg->PSEL.RTS;
585 }
586
nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)587 NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg)
588 {
589 return p_reg->PSEL.CTS;
590 }
591
nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,uint32_t pselrts,uint32_t pselcts)592 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_set(NRF_UARTE_Type * p_reg,
593 uint32_t pselrts,
594 uint32_t pselcts)
595 {
596 p_reg->PSEL.RTS = pselrts;
597 p_reg->PSEL.CTS = pselcts;
598 }
599
nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)600 NRF_STATIC_INLINE void nrf_uarte_hwfc_pins_disconnect(NRF_UARTE_Type * p_reg)
601 {
602 nrf_uarte_hwfc_pins_set(p_reg, NRF_UARTE_PSEL_DISCONNECTED, NRF_UARTE_PSEL_DISCONNECTED);
603 }
604
nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg,nrf_uarte_task_t task)605 NRF_STATIC_INLINE void nrf_uarte_task_trigger(NRF_UARTE_Type * p_reg, nrf_uarte_task_t task)
606 {
607 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
608 }
609
nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,nrf_uarte_task_t task)610 NRF_STATIC_INLINE uint32_t nrf_uarte_task_address_get(NRF_UARTE_Type const * p_reg,
611 nrf_uarte_task_t task)
612 {
613 return (uint32_t)p_reg + (uint32_t)task;
614 }
615
nrf_uarte_configure(NRF_UARTE_Type * p_reg,nrf_uarte_config_t const * p_cfg)616 NRF_STATIC_INLINE void nrf_uarte_configure(NRF_UARTE_Type * p_reg,
617 nrf_uarte_config_t const * p_cfg)
618 {
619 p_reg->CONFIG = (uint32_t)p_cfg->parity
620 #if defined(UARTE_CONFIG_STOP_Msk)
621 | (uint32_t)p_cfg->stop
622 #endif
623 #if defined(UARTE_CONFIG_PARITYTYPE_Msk)
624 | (uint32_t)p_cfg->paritytype
625 #endif
626 | (uint32_t)p_cfg->hwfc;
627 }
628
nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg,nrf_uarte_baudrate_t baudrate)629 NRF_STATIC_INLINE void nrf_uarte_baudrate_set(NRF_UARTE_Type * p_reg, nrf_uarte_baudrate_t baudrate)
630 {
631 p_reg->BAUDRATE = baudrate;
632 }
633
nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t const * p_buffer,size_t length)634 NRF_STATIC_INLINE void nrf_uarte_tx_buffer_set(NRF_UARTE_Type * p_reg,
635 uint8_t const * p_buffer,
636 size_t length)
637 {
638 p_reg->TXD.PTR = (uint32_t)p_buffer;
639 p_reg->TXD.MAXCNT = length;
640 }
641
nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)642 NRF_STATIC_INLINE uint32_t nrf_uarte_tx_amount_get(NRF_UARTE_Type const * p_reg)
643 {
644 return p_reg->TXD.AMOUNT;
645 }
646
nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,uint8_t * p_buffer,size_t length)647 NRF_STATIC_INLINE void nrf_uarte_rx_buffer_set(NRF_UARTE_Type * p_reg,
648 uint8_t * p_buffer,
649 size_t length)
650 {
651 p_reg->RXD.PTR = (uint32_t)p_buffer;
652 p_reg->RXD.MAXCNT = length;
653 }
654
nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)655 NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
656 {
657 return p_reg->RXD.AMOUNT;
658 }
659 #endif // NRF_DECLARE_ONLY
660
661 /** @} */
662
663 #ifdef __cplusplus
664 }
665 #endif
666
667 #endif // NRF_UARTE_H__
668