1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "reg_helper.h"
27 #include "dcn30_optc.h"
28 #include "dc.h"
29 #include "dcn_calc_math.h"
30 #include "dc_dmub_srv.h"
31
32 #include "dml/dcn30/dcn30_fpu.h"
33 #include "dc_trace.h"
34
35 #define REG(reg)\
36 optc1->tg_regs->reg
37
38 #define CTX \
39 optc1->base.ctx
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 optc1->tg_shift->field_name, optc1->tg_mask->field_name
44
optc3_triplebuffer_lock(struct timing_generator * optc)45 void optc3_triplebuffer_lock(struct timing_generator *optc)
46 {
47 struct optc *optc1 = DCN10TG_FROM_TG(optc);
48
49 REG_UPDATE(OTG_GLOBAL_CONTROL2,
50 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
51
52 REG_SET(OTG_VUPDATE_KEEPOUT, 0,
53 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
54
55 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
56 OTG_MASTER_UPDATE_LOCK, 1);
57
58 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
59 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
60 UPDATE_LOCK_STATUS, 1,
61 1, 10);
62
63 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
64 }
65
optc3_lock_doublebuffer_enable(struct timing_generator * optc)66 void optc3_lock_doublebuffer_enable(struct timing_generator *optc)
67 {
68 struct optc *optc1 = DCN10TG_FROM_TG(optc);
69 uint32_t v_blank_start = 0;
70 uint32_t v_blank_end = 0;
71 uint32_t h_blank_start = 0;
72 uint32_t h_blank_end = 0;
73
74 REG_GET_2(OTG_V_BLANK_START_END,
75 OTG_V_BLANK_START, &v_blank_start,
76 OTG_V_BLANK_END, &v_blank_end);
77 REG_GET_2(OTG_H_BLANK_START_END,
78 OTG_H_BLANK_START, &h_blank_start,
79 OTG_H_BLANK_END, &h_blank_end);
80
81 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
82 MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start - 1,
83 MASTER_UPDATE_LOCK_DB_END_Y, v_blank_start);
84 REG_UPDATE_2(OTG_GLOBAL_CONTROL4,
85 DIG_UPDATE_POSITION_X, h_blank_start - 180 - 1,
86 DIG_UPDATE_POSITION_Y, v_blank_start - 1);
87 // there is a DIG_UPDATE_VCOUNT_MODE and it is 0.
88
89 REG_UPDATE_3(OTG_GLOBAL_CONTROL0,
90 MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1,
91 MASTER_UPDATE_LOCK_DB_END_X, h_blank_start - 180,
92 MASTER_UPDATE_LOCK_DB_EN, 1);
93 REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
94
95 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0,
96 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, 0,
97 MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, 100,
98 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1);
99
100 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
101 }
102
optc3_lock_doublebuffer_disable(struct timing_generator * optc)103 void optc3_lock_doublebuffer_disable(struct timing_generator *optc)
104 {
105 struct optc *optc1 = DCN10TG_FROM_TG(optc);
106
107 REG_UPDATE_2(OTG_GLOBAL_CONTROL0,
108 MASTER_UPDATE_LOCK_DB_START_X, 0,
109 MASTER_UPDATE_LOCK_DB_END_X, 0);
110 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
111 MASTER_UPDATE_LOCK_DB_START_Y, 0,
112 MASTER_UPDATE_LOCK_DB_END_Y, 0);
113
114 REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0);
115 REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 0);
116
117 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
118 }
119
optc3_lock(struct timing_generator * optc)120 void optc3_lock(struct timing_generator *optc)
121 {
122 struct optc *optc1 = DCN10TG_FROM_TG(optc);
123
124 REG_UPDATE(OTG_GLOBAL_CONTROL2,
125 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
126 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
127 OTG_MASTER_UPDATE_LOCK, 1);
128
129 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
130 UPDATE_LOCK_STATUS, 1,
131 1, 10);
132
133 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
134 }
135
optc3_set_out_mux(struct timing_generator * optc,enum otg_out_mux_dest dest)136 void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest)
137 {
138 struct optc *optc1 = DCN10TG_FROM_TG(optc);
139
140 REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest);
141 }
142
optc3_program_blank_color(struct timing_generator * optc,const struct tg_color * blank_color)143 void optc3_program_blank_color(struct timing_generator *optc,
144 const struct tg_color *blank_color)
145 {
146 struct optc *optc1 = DCN10TG_FROM_TG(optc);
147
148 REG_SET_3(OTG_BLANK_DATA_COLOR, 0,
149 OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb,
150 OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y,
151 OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr);
152
153 REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0,
154 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10,
155 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10,
156 OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10);
157 }
158
optc3_set_drr_trigger_window(struct timing_generator * optc,uint32_t window_start,uint32_t window_end)159 void optc3_set_drr_trigger_window(struct timing_generator *optc,
160 uint32_t window_start, uint32_t window_end)
161 {
162 struct optc *optc1 = DCN10TG_FROM_TG(optc);
163
164 REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0,
165 OTG_DRR_TRIGGER_WINDOW_START_X, window_start,
166 OTG_DRR_TRIGGER_WINDOW_END_X, window_end);
167 }
168
optc3_set_vtotal_change_limit(struct timing_generator * optc,uint32_t limit)169 void optc3_set_vtotal_change_limit(struct timing_generator *optc,
170 uint32_t limit)
171 {
172 struct optc *optc1 = DCN10TG_FROM_TG(optc);
173
174
175 REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0,
176 OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit);
177 }
178
179
180 /* Set DSC-related configuration.
181 * dsc_mode: 0 disables DSC, other values enable DSC in specified format
182 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format
183 * dsc_slice_width: Slice width in pixels
184 */
optc3_set_dsc_config(struct timing_generator * optc,enum optc_dsc_mode dsc_mode,uint32_t dsc_bytes_per_pixel,uint32_t dsc_slice_width)185 void optc3_set_dsc_config(struct timing_generator *optc,
186 enum optc_dsc_mode dsc_mode,
187 uint32_t dsc_bytes_per_pixel,
188 uint32_t dsc_slice_width)
189 {
190 struct optc *optc1 = DCN10TG_FROM_TG(optc);
191
192 optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width);
193 REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
194 }
195
optc3_set_odm_bypass(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing)196 void optc3_set_odm_bypass(struct timing_generator *optc,
197 const struct dc_crtc_timing *dc_crtc_timing)
198 {
199 struct optc *optc1 = DCN10TG_FROM_TG(optc);
200 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
201
202 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
203 OPTC_NUM_OF_INPUT_SEGMENT, 0,
204 OPTC_SEG0_SRC_SEL, optc->inst,
205 OPTC_SEG1_SRC_SEL, 0xf,
206 OPTC_SEG2_SRC_SEL, 0xf,
207 OPTC_SEG3_SRC_SEL, 0xf
208 );
209
210 h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing);
211 REG_SET(OTG_H_TIMING_CNTL, 0,
212 OTG_H_TIMING_DIV_MODE, h_div);
213
214 REG_SET(OPTC_MEMORY_CONFIG, 0,
215 OPTC_MEM_SEL, 0);
216 optc1->opp_count = 1;
217 }
218
optc3_set_odm_combine(struct timing_generator * optc,int * opp_id,int opp_cnt,struct dc_crtc_timing * timing)219 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt,
220 struct dc_crtc_timing *timing)
221 {
222 struct optc *optc1 = DCN10TG_FROM_TG(optc);
223 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right)
224 / opp_cnt;
225 uint32_t memory_mask = 0;
226
227 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic
228 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1);
229 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start
230 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0,
231 * MASTER_UPDATE_LOCK_DB_X, 160,
232 * MASTER_UPDATE_LOCK_DB_Y, 240);
233 */
234
235 ASSERT(opp_cnt == 2 || opp_cnt == 4);
236
237 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192,
238 * however, for ODM combine we can simplify by always using 4.
239 */
240 if (opp_cnt == 2) {
241 /* To make sure there's no memory overlap, each instance "reserves" 2
242 * memories and they are uniquely combined here.
243 */
244 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2);
245 } else if (opp_cnt == 4) {
246 /* To make sure there's no memory overlap, each instance "reserves" 1
247 * memory and they are uniquely combined here.
248 */
249 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2);
250 }
251
252 if (REG(OPTC_MEMORY_CONFIG))
253 REG_SET(OPTC_MEMORY_CONFIG, 0,
254 OPTC_MEM_SEL, memory_mask);
255
256 if (opp_cnt == 2) {
257 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0,
258 OPTC_NUM_OF_INPUT_SEGMENT, 1,
259 OPTC_SEG0_SRC_SEL, opp_id[0],
260 OPTC_SEG1_SRC_SEL, opp_id[1]);
261 } else if (opp_cnt == 4) {
262 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0,
263 OPTC_NUM_OF_INPUT_SEGMENT, 3,
264 OPTC_SEG0_SRC_SEL, opp_id[0],
265 OPTC_SEG1_SRC_SEL, opp_id[1],
266 OPTC_SEG2_SRC_SEL, opp_id[2],
267 OPTC_SEG3_SRC_SEL, opp_id[3]);
268 }
269
270 REG_UPDATE(OPTC_WIDTH_CONTROL,
271 OPTC_SEGMENT_WIDTH, mpcc_hactive);
272
273 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1);
274 optc1->opp_count = opp_cnt;
275 }
276
277 /**
278 * optc3_set_timing_double_buffer() - DRR double buffering control
279 *
280 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
281 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
282 *
283 * Options: any time, start of frame, dp start of frame (range timing)
284 */
optc3_set_timing_double_buffer(struct timing_generator * optc,bool enable)285 static void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable)
286 {
287 struct optc *optc1 = DCN10TG_FROM_TG(optc);
288 uint32_t mode = enable ? 2 : 0;
289
290 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
291 OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode);
292 }
293
optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator * optc)294 void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc)
295 {
296 struct optc *optc1 = DCN10TG_FROM_TG(optc);
297
298 REG_WAIT(OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, 0, 2, 100000); /* 1 vupdate at 5hz */
299
300 }
301
optc3_set_vtotal_min_max(struct timing_generator * optc,int vtotal_min,int vtotal_max)302 void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
303 {
304 optc1_set_vtotal_min_max(optc, vtotal_min, vtotal_max);
305 }
306
optc3_tg_init(struct timing_generator * optc)307 void optc3_tg_init(struct timing_generator *optc)
308 {
309 optc3_set_timing_double_buffer(optc, true);
310 optc1_clear_optc_underflow(optc);
311 }
312
313 static struct timing_generator_funcs dcn30_tg_funcs = {
314 .validate_timing = optc1_validate_timing,
315 .program_timing = optc1_program_timing,
316 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
317 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
318 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
319 .program_global_sync = optc1_program_global_sync,
320 .enable_crtc = optc2_enable_crtc,
321 .disable_crtc = optc1_disable_crtc,
322 /* used by enable_timing_synchronization. Not need for FPGA */
323 .is_counter_moving = optc1_is_counter_moving,
324 .get_position = optc1_get_position,
325 .get_frame_count = optc1_get_vblank_counter,
326 .get_scanoutpos = optc1_get_crtc_scanoutpos,
327 .get_otg_active_size = optc1_get_otg_active_size,
328 .set_early_control = optc1_set_early_control,
329 /* used by enable_timing_synchronization. Not need for FPGA */
330 .wait_for_state = optc1_wait_for_state,
331 .set_blank_color = optc3_program_blank_color,
332 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
333 .triplebuffer_lock = optc3_triplebuffer_lock,
334 .triplebuffer_unlock = optc2_triplebuffer_unlock,
335 .enable_reset_trigger = optc1_enable_reset_trigger,
336 .enable_crtc_reset = optc1_enable_crtc_reset,
337 .disable_reset_trigger = optc1_disable_reset_trigger,
338 .lock = optc3_lock,
339 .unlock = optc1_unlock,
340 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
341 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
342 .enable_optc_clock = optc1_enable_optc_clock,
343 .set_drr = optc1_set_drr,
344 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
345 .set_vtotal_min_max = optc3_set_vtotal_min_max,
346 .set_static_screen_control = optc1_set_static_screen_control,
347 .program_stereo = optc1_program_stereo,
348 .is_stereo_left_eye = optc1_is_stereo_left_eye,
349 .tg_init = optc3_tg_init,
350 .is_tg_enabled = optc1_is_tg_enabled,
351 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
352 .clear_optc_underflow = optc1_clear_optc_underflow,
353 .setup_global_swap_lock = NULL,
354 .get_crc = optc1_get_crc,
355 .configure_crc = optc2_configure_crc,
356 .set_dsc_config = optc3_set_dsc_config,
357 .get_dsc_status = optc2_get_dsc_status,
358 .set_dwb_source = NULL,
359 .set_odm_bypass = optc3_set_odm_bypass,
360 .set_odm_combine = optc3_set_odm_combine,
361 .get_optc_source = optc2_get_optc_source,
362 .set_out_mux = optc3_set_out_mux,
363 .set_drr_trigger_window = optc3_set_drr_trigger_window,
364 .set_vtotal_change_limit = optc3_set_vtotal_change_limit,
365 .set_gsl = optc2_set_gsl,
366 .set_gsl_source_select = optc2_set_gsl_source_select,
367 .set_vtg_params = optc1_set_vtg_params,
368 .program_manual_trigger = optc2_program_manual_trigger,
369 .setup_manual_trigger = optc2_setup_manual_trigger,
370 .get_hw_timing = optc1_get_hw_timing,
371 .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear,
372 };
373
dcn30_timing_generator_init(struct optc * optc1)374 void dcn30_timing_generator_init(struct optc *optc1)
375 {
376 optc1->base.funcs = &dcn30_tg_funcs;
377
378 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
379 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
380
381 optc1->min_h_blank = 32;
382 optc1->min_v_blank = 3;
383 optc1->min_v_blank_interlace = 5;
384 optc1->min_h_sync_width = 4;
385 optc1->min_v_sync_width = 1;
386 }
387