| /u-boot-v2022.01-rc1/drivers/ddr/marvell/axp/ |
| A D | ddr3_write_leveling.c | 68 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
188 u32 cs, cnt, pup_num, sum, phase, delay, max_pup_num, pup, sdram_offset; in ddr3_wl_supplement() local
476 u32 reg, phase, delay, cs, pup, pup_num; in ddr3_write_leveling_hw_reg_dimm() local
661 u32 reg, cs, cnt, pup, max_pup_num; in ddr3_write_leveling_sw() local
886 u32 reg, cs, cnt, pup; in ddr3_write_leveling_sw_reg_dimm() local
1129 u32 reg, pup_num, delay, phase, phaseMax, max_pup_num, pup, in ddr3_write_leveling_single_cs() local
1340 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr, u32 data) in ddr3_write_ctrl_pup_reg()
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| A D | ddr3_pbs.c | 97 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_tx() local
412 u32 cur_max_pup, pup; in ddr3_tx_shift_dqs_adll_step_before_fail() local
539 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_rx() local
924 u32 cur_max_pup, pup, pass_pup; in ddr3_rx_shift_dqs_to_first_fail() local
1087 static void lock_pups(u32 pup, u32 *pup_locked, u8 *unlock_pup_dq_array, in lock_pups()
1149 u32 pup, dq; in ddr3_pbs_per_bit() local
1419 u32 pup, phys_pup, dq; in ddr3_set_pbs_results() local
1508 static void ddr3_pbs_write_pup_dqs_reg(u32 cs, u32 pup, u32 dqs_delay) in ddr3_pbs_write_pup_dqs_reg()
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| A D | ddr3_read_leveling.c | 92 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
182 u32 reg, cs, ecc, pup_num, phase, delay, pup; in ddr3_read_leveling_sw() local
336 static void overrun(u32 cs, MV_DRAM_INFO *info, u32 pup, u32 locked_pups, in overrun()
404 u32 reg, delay, phase, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_rl_mode() local
756 u32 reg, delay, phase, sum, pup, rd_sample_delay, add, locked_pups, in ddr3_read_leveling_single_cs_window_mode() local
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| A D | ddr3_dqs.c | 298 u32 victim_dq, pup, tmp; in ddr3_find_adll_limits() local
829 int ddr3_check_window_limits(u32 pup, int high_limit, int low_limit, int is_tx, in ddr3_check_window_limits()
893 u32 pup; in ddr3_center_calc() local
957 u32 pup; in ddr3_special_pattern_i_search() local
1118 u32 pup; in ddr3_special_pattern_ii_search() local
1265 u32 pup, pup_num; in ddr3_set_dqs_centralization_results() local
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| A D | ddr3_sdram.c | 91 static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern, in compare_pattern_v1()
129 static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern) in compare_pattern_v2()
225 u32 pup = 0; in ddr3_sdram_dm_compare() local
291 u32 ui, dq, pup; in ddr3_sdram_pbs_compare() local
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| A D | ddr3_hw_training.c | 549 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) in ddr3_write_pup_reg()
599 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup) in ddr3_read_pup_reg()
699 u32 val, pup, tmp_cs, cs, i, dq; in ddr3_save_training() local
1050 u32 pup, reg, phase; in ddr3_get_min_max_rl_phase() local
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| /u-boot-v2022.01-rc1/drivers/ddr/marvell/a38x/ |
| A D | ddr3_training_pbs.c | 48 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; in ddr3_tip_pbs() local
942 u32 data_value = 0, bit = 0, if_id = 0, pup = 0; in ddr3_tip_print_pbs_result() local
992 u32 if_id, pup, bit; in ddr3_tip_clean_pbs_result() local
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| A D | ddr3_training_hw_algo.c | 162 u32 pup = 0, if_id = 0, num_pup = 0, rep = 0; in ddr3_tip_vref() local
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| A D | ddr3_debug.c | 946 u32 pup = 0, start_pup = 0, end_pup = 0; in ddr3_tip_run_sweep_test() local
1092 u32 pup = 0, start_pup = 0, end_pup = 0, start_adll = 0; in ddr3_tip_run_leveling_sweep_test() local
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