1 // SPDX-License-Identifier: GPL-2.0-only
2 //
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
4 //
5 // Copyright 2018 Realtek Semiconductor Corp.
6 // Author: Bard Liao <bardliao@realtek.com>
7 //
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/acpi.h>
18 #include <linux/gpio.h>
19 #include <linux/of_gpio.h>
20 #include <linux/mutex.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/jack.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 #include <sound/rt5682.h>
30
31 #include "rl6231.h"
32 #include "rt5682.h"
33
34 const char *rt5682_supply_names[RT5682_NUM_SUPPLIES] = {
35 "AVDD",
36 "MICVDD",
37 "VBAT",
38 "DBVDD",
39 "LDO1-IN",
40 };
41 EXPORT_SYMBOL_GPL(rt5682_supply_names);
42
43 static const struct reg_sequence patch_list[] = {
44 {RT5682_HP_IMP_SENS_CTRL_19, 0x1000},
45 {RT5682_DAC_ADC_DIG_VOL1, 0xa020},
46 {RT5682_I2C_CTRL, 0x000f},
47 {RT5682_PLL2_INTERNAL, 0x8266},
48 {RT5682_SAR_IL_CMD_1, 0x22b7},
49 {RT5682_SAR_IL_CMD_3, 0x0365},
50 {RT5682_SAR_IL_CMD_6, 0x0110},
51 {RT5682_CHARGE_PUMP_1, 0x0210},
52 {RT5682_HP_LOGIC_CTRL_2, 0x0007},
53 {RT5682_SAR_IL_CMD_2, 0xac00},
54 {RT5682_CBJ_CTRL_7, 0x0104},
55 };
56
rt5682_apply_patch_list(struct rt5682_priv * rt5682,struct device * dev)57 void rt5682_apply_patch_list(struct rt5682_priv *rt5682, struct device *dev)
58 {
59 int ret;
60
61 ret = regmap_multi_reg_write(rt5682->regmap, patch_list,
62 ARRAY_SIZE(patch_list));
63 if (ret)
64 dev_warn(dev, "Failed to apply regmap patch: %d\n", ret);
65 }
66 EXPORT_SYMBOL_GPL(rt5682_apply_patch_list);
67
68 const struct reg_default rt5682_reg[RT5682_REG_NUM] = {
69 {0x0002, 0x8080},
70 {0x0003, 0x8000},
71 {0x0005, 0x0000},
72 {0x0006, 0x0000},
73 {0x0008, 0x800f},
74 {0x000b, 0x0000},
75 {0x0010, 0x4040},
76 {0x0011, 0x0000},
77 {0x0012, 0x1404},
78 {0x0013, 0x1000},
79 {0x0014, 0xa00a},
80 {0x0015, 0x0404},
81 {0x0016, 0x0404},
82 {0x0019, 0xafaf},
83 {0x001c, 0x2f2f},
84 {0x001f, 0x0000},
85 {0x0022, 0x5757},
86 {0x0023, 0x0039},
87 {0x0024, 0x000b},
88 {0x0026, 0xc0c4},
89 {0x0029, 0x8080},
90 {0x002a, 0xa0a0},
91 {0x002b, 0x0300},
92 {0x0030, 0x0000},
93 {0x003c, 0x0080},
94 {0x0044, 0x0c0c},
95 {0x0049, 0x0000},
96 {0x0061, 0x0000},
97 {0x0062, 0x0000},
98 {0x0063, 0x003f},
99 {0x0064, 0x0000},
100 {0x0065, 0x0000},
101 {0x0066, 0x0030},
102 {0x0067, 0x0000},
103 {0x006b, 0x0000},
104 {0x006c, 0x0000},
105 {0x006d, 0x2200},
106 {0x006e, 0x0a10},
107 {0x0070, 0x8000},
108 {0x0071, 0x8000},
109 {0x0073, 0x0000},
110 {0x0074, 0x0000},
111 {0x0075, 0x0002},
112 {0x0076, 0x0001},
113 {0x0079, 0x0000},
114 {0x007a, 0x0000},
115 {0x007b, 0x0000},
116 {0x007c, 0x0100},
117 {0x007e, 0x0000},
118 {0x0080, 0x0000},
119 {0x0081, 0x0000},
120 {0x0082, 0x0000},
121 {0x0083, 0x0000},
122 {0x0084, 0x0000},
123 {0x0085, 0x0000},
124 {0x0086, 0x0005},
125 {0x0087, 0x0000},
126 {0x0088, 0x0000},
127 {0x008c, 0x0003},
128 {0x008d, 0x0000},
129 {0x008e, 0x0060},
130 {0x008f, 0x1000},
131 {0x0091, 0x0c26},
132 {0x0092, 0x0073},
133 {0x0093, 0x0000},
134 {0x0094, 0x0080},
135 {0x0098, 0x0000},
136 {0x009a, 0x0000},
137 {0x009b, 0x0000},
138 {0x009c, 0x0000},
139 {0x009d, 0x0000},
140 {0x009e, 0x100c},
141 {0x009f, 0x0000},
142 {0x00a0, 0x0000},
143 {0x00a3, 0x0002},
144 {0x00a4, 0x0001},
145 {0x00ae, 0x2040},
146 {0x00af, 0x0000},
147 {0x00b6, 0x0000},
148 {0x00b7, 0x0000},
149 {0x00b8, 0x0000},
150 {0x00b9, 0x0002},
151 {0x00be, 0x0000},
152 {0x00c0, 0x0160},
153 {0x00c1, 0x82a0},
154 {0x00c2, 0x0000},
155 {0x00d0, 0x0000},
156 {0x00d1, 0x2244},
157 {0x00d2, 0x3300},
158 {0x00d3, 0x2200},
159 {0x00d4, 0x0000},
160 {0x00d9, 0x0009},
161 {0x00da, 0x0000},
162 {0x00db, 0x0000},
163 {0x00dc, 0x00c0},
164 {0x00dd, 0x2220},
165 {0x00de, 0x3131},
166 {0x00df, 0x3131},
167 {0x00e0, 0x3131},
168 {0x00e2, 0x0000},
169 {0x00e3, 0x4000},
170 {0x00e4, 0x0aa0},
171 {0x00e5, 0x3131},
172 {0x00e6, 0x3131},
173 {0x00e7, 0x3131},
174 {0x00e8, 0x3131},
175 {0x00ea, 0xb320},
176 {0x00eb, 0x0000},
177 {0x00f0, 0x0000},
178 {0x00f1, 0x00d0},
179 {0x00f2, 0x00d0},
180 {0x00f6, 0x0000},
181 {0x00fa, 0x0000},
182 {0x00fb, 0x0000},
183 {0x00fc, 0x0000},
184 {0x00fd, 0x0000},
185 {0x00fe, 0x10ec},
186 {0x00ff, 0x6530},
187 {0x0100, 0xa0a0},
188 {0x010b, 0x0000},
189 {0x010c, 0xae00},
190 {0x010d, 0xaaa0},
191 {0x010e, 0x8aa2},
192 {0x010f, 0x02a2},
193 {0x0110, 0xc000},
194 {0x0111, 0x04a2},
195 {0x0112, 0x2800},
196 {0x0113, 0x0000},
197 {0x0117, 0x0100},
198 {0x0125, 0x0410},
199 {0x0132, 0x6026},
200 {0x0136, 0x5555},
201 {0x0138, 0x3700},
202 {0x013a, 0x2000},
203 {0x013b, 0x2000},
204 {0x013c, 0x2005},
205 {0x013f, 0x0000},
206 {0x0142, 0x0000},
207 {0x0145, 0x0002},
208 {0x0146, 0x0000},
209 {0x0147, 0x0000},
210 {0x0148, 0x0000},
211 {0x0149, 0x0000},
212 {0x0150, 0x79a1},
213 {0x0156, 0xaaaa},
214 {0x0160, 0x4ec0},
215 {0x0161, 0x0080},
216 {0x0162, 0x0200},
217 {0x0163, 0x0800},
218 {0x0164, 0x0000},
219 {0x0165, 0x0000},
220 {0x0166, 0x0000},
221 {0x0167, 0x000f},
222 {0x0168, 0x000f},
223 {0x0169, 0x0021},
224 {0x0190, 0x413d},
225 {0x0194, 0x0000},
226 {0x0195, 0x0000},
227 {0x0197, 0x0022},
228 {0x0198, 0x0000},
229 {0x0199, 0x0000},
230 {0x01af, 0x0000},
231 {0x01b0, 0x0400},
232 {0x01b1, 0x0000},
233 {0x01b2, 0x0000},
234 {0x01b3, 0x0000},
235 {0x01b4, 0x0000},
236 {0x01b5, 0x0000},
237 {0x01b6, 0x01c3},
238 {0x01b7, 0x02a0},
239 {0x01b8, 0x03e9},
240 {0x01b9, 0x1389},
241 {0x01ba, 0xc351},
242 {0x01bb, 0x0009},
243 {0x01bc, 0x0018},
244 {0x01bd, 0x002a},
245 {0x01be, 0x004c},
246 {0x01bf, 0x0097},
247 {0x01c0, 0x433d},
248 {0x01c2, 0x0000},
249 {0x01c3, 0x0000},
250 {0x01c4, 0x0000},
251 {0x01c5, 0x0000},
252 {0x01c6, 0x0000},
253 {0x01c7, 0x0000},
254 {0x01c8, 0x40af},
255 {0x01c9, 0x0702},
256 {0x01ca, 0x0000},
257 {0x01cb, 0x0000},
258 {0x01cc, 0x5757},
259 {0x01cd, 0x5757},
260 {0x01ce, 0x5757},
261 {0x01cf, 0x5757},
262 {0x01d0, 0x5757},
263 {0x01d1, 0x5757},
264 {0x01d2, 0x5757},
265 {0x01d3, 0x5757},
266 {0x01d4, 0x5757},
267 {0x01d5, 0x5757},
268 {0x01d6, 0x0000},
269 {0x01d7, 0x0008},
270 {0x01d8, 0x0029},
271 {0x01d9, 0x3333},
272 {0x01da, 0x0000},
273 {0x01db, 0x0004},
274 {0x01dc, 0x0000},
275 {0x01de, 0x7c00},
276 {0x01df, 0x0320},
277 {0x01e0, 0x06a1},
278 {0x01e1, 0x0000},
279 {0x01e2, 0x0000},
280 {0x01e3, 0x0000},
281 {0x01e4, 0x0000},
282 {0x01e6, 0x0001},
283 {0x01e7, 0x0000},
284 {0x01e8, 0x0000},
285 {0x01ea, 0x0000},
286 {0x01eb, 0x0000},
287 {0x01ec, 0x0000},
288 {0x01ed, 0x0000},
289 {0x01ee, 0x0000},
290 {0x01ef, 0x0000},
291 {0x01f0, 0x0000},
292 {0x01f1, 0x0000},
293 {0x01f2, 0x0000},
294 {0x01f3, 0x0000},
295 {0x01f4, 0x0000},
296 {0x0210, 0x6297},
297 {0x0211, 0xa005},
298 {0x0212, 0x824c},
299 {0x0213, 0xf7ff},
300 {0x0214, 0xf24c},
301 {0x0215, 0x0102},
302 {0x0216, 0x00a3},
303 {0x0217, 0x0048},
304 {0x0218, 0xa2c0},
305 {0x0219, 0x0400},
306 {0x021a, 0x00c8},
307 {0x021b, 0x00c0},
308 {0x021c, 0x0000},
309 {0x0250, 0x4500},
310 {0x0251, 0x40b3},
311 {0x0252, 0x0000},
312 {0x0253, 0x0000},
313 {0x0254, 0x0000},
314 {0x0255, 0x0000},
315 {0x0256, 0x0000},
316 {0x0257, 0x0000},
317 {0x0258, 0x0000},
318 {0x0259, 0x0000},
319 {0x025a, 0x0005},
320 {0x0270, 0x0000},
321 {0x02ff, 0x0110},
322 {0x0300, 0x001f},
323 {0x0301, 0x032c},
324 {0x0302, 0x5f21},
325 {0x0303, 0x4000},
326 {0x0304, 0x4000},
327 {0x0305, 0x06d5},
328 {0x0306, 0x8000},
329 {0x0307, 0x0700},
330 {0x0310, 0x4560},
331 {0x0311, 0xa4a8},
332 {0x0312, 0x7418},
333 {0x0313, 0x0000},
334 {0x0314, 0x0006},
335 {0x0315, 0xffff},
336 {0x0316, 0xc400},
337 {0x0317, 0x0000},
338 {0x03c0, 0x7e00},
339 {0x03c1, 0x8000},
340 {0x03c2, 0x8000},
341 {0x03c3, 0x8000},
342 {0x03c4, 0x8000},
343 {0x03c5, 0x8000},
344 {0x03c6, 0x8000},
345 {0x03c7, 0x8000},
346 {0x03c8, 0x8000},
347 {0x03c9, 0x8000},
348 {0x03ca, 0x8000},
349 {0x03cb, 0x8000},
350 {0x03cc, 0x8000},
351 {0x03d0, 0x0000},
352 {0x03d1, 0x0000},
353 {0x03d2, 0x0000},
354 {0x03d3, 0x0000},
355 {0x03d4, 0x2000},
356 {0x03d5, 0x2000},
357 {0x03d6, 0x0000},
358 {0x03d7, 0x0000},
359 {0x03d8, 0x2000},
360 {0x03d9, 0x2000},
361 {0x03da, 0x2000},
362 {0x03db, 0x2000},
363 {0x03dc, 0x0000},
364 {0x03dd, 0x0000},
365 {0x03de, 0x0000},
366 {0x03df, 0x2000},
367 {0x03e0, 0x0000},
368 {0x03e1, 0x0000},
369 {0x03e2, 0x0000},
370 {0x03e3, 0x0000},
371 {0x03e4, 0x0000},
372 {0x03e5, 0x0000},
373 {0x03e6, 0x0000},
374 {0x03e7, 0x0000},
375 {0x03e8, 0x0000},
376 {0x03e9, 0x0000},
377 {0x03ea, 0x0000},
378 {0x03eb, 0x0000},
379 {0x03ec, 0x0000},
380 {0x03ed, 0x0000},
381 {0x03ee, 0x0000},
382 {0x03ef, 0x0000},
383 {0x03f0, 0x0800},
384 {0x03f1, 0x0800},
385 {0x03f2, 0x0800},
386 {0x03f3, 0x0800},
387 };
388 EXPORT_SYMBOL_GPL(rt5682_reg);
389
rt5682_volatile_register(struct device * dev,unsigned int reg)390 bool rt5682_volatile_register(struct device *dev, unsigned int reg)
391 {
392 switch (reg) {
393 case RT5682_RESET:
394 case RT5682_CBJ_CTRL_2:
395 case RT5682_INT_ST_1:
396 case RT5682_4BTN_IL_CMD_1:
397 case RT5682_AJD1_CTRL:
398 case RT5682_HP_CALIB_CTRL_1:
399 case RT5682_DEVICE_ID:
400 case RT5682_I2C_MODE:
401 case RT5682_HP_CALIB_CTRL_10:
402 case RT5682_EFUSE_CTRL_2:
403 case RT5682_JD_TOP_VC_VTRL:
404 case RT5682_HP_IMP_SENS_CTRL_19:
405 case RT5682_IL_CMD_1:
406 case RT5682_SAR_IL_CMD_2:
407 case RT5682_SAR_IL_CMD_4:
408 case RT5682_SAR_IL_CMD_10:
409 case RT5682_SAR_IL_CMD_11:
410 case RT5682_EFUSE_CTRL_6...RT5682_EFUSE_CTRL_11:
411 case RT5682_HP_CALIB_STA_1...RT5682_HP_CALIB_STA_11:
412 return true;
413 default:
414 return false;
415 }
416 }
417 EXPORT_SYMBOL_GPL(rt5682_volatile_register);
418
rt5682_readable_register(struct device * dev,unsigned int reg)419 bool rt5682_readable_register(struct device *dev, unsigned int reg)
420 {
421 switch (reg) {
422 case RT5682_RESET:
423 case RT5682_VERSION_ID:
424 case RT5682_VENDOR_ID:
425 case RT5682_DEVICE_ID:
426 case RT5682_HP_CTRL_1:
427 case RT5682_HP_CTRL_2:
428 case RT5682_HPL_GAIN:
429 case RT5682_HPR_GAIN:
430 case RT5682_I2C_CTRL:
431 case RT5682_CBJ_BST_CTRL:
432 case RT5682_CBJ_CTRL_1:
433 case RT5682_CBJ_CTRL_2:
434 case RT5682_CBJ_CTRL_3:
435 case RT5682_CBJ_CTRL_4:
436 case RT5682_CBJ_CTRL_5:
437 case RT5682_CBJ_CTRL_6:
438 case RT5682_CBJ_CTRL_7:
439 case RT5682_DAC1_DIG_VOL:
440 case RT5682_STO1_ADC_DIG_VOL:
441 case RT5682_STO1_ADC_BOOST:
442 case RT5682_HP_IMP_GAIN_1:
443 case RT5682_HP_IMP_GAIN_2:
444 case RT5682_SIDETONE_CTRL:
445 case RT5682_STO1_ADC_MIXER:
446 case RT5682_AD_DA_MIXER:
447 case RT5682_STO1_DAC_MIXER:
448 case RT5682_A_DAC1_MUX:
449 case RT5682_DIG_INF2_DATA:
450 case RT5682_REC_MIXER:
451 case RT5682_CAL_REC:
452 case RT5682_ALC_BACK_GAIN:
453 case RT5682_PWR_DIG_1:
454 case RT5682_PWR_DIG_2:
455 case RT5682_PWR_ANLG_1:
456 case RT5682_PWR_ANLG_2:
457 case RT5682_PWR_ANLG_3:
458 case RT5682_PWR_MIXER:
459 case RT5682_PWR_VOL:
460 case RT5682_CLK_DET:
461 case RT5682_RESET_LPF_CTRL:
462 case RT5682_RESET_HPF_CTRL:
463 case RT5682_DMIC_CTRL_1:
464 case RT5682_I2S1_SDP:
465 case RT5682_I2S2_SDP:
466 case RT5682_ADDA_CLK_1:
467 case RT5682_ADDA_CLK_2:
468 case RT5682_I2S1_F_DIV_CTRL_1:
469 case RT5682_I2S1_F_DIV_CTRL_2:
470 case RT5682_TDM_CTRL:
471 case RT5682_TDM_ADDA_CTRL_1:
472 case RT5682_TDM_ADDA_CTRL_2:
473 case RT5682_DATA_SEL_CTRL_1:
474 case RT5682_TDM_TCON_CTRL:
475 case RT5682_GLB_CLK:
476 case RT5682_PLL_CTRL_1:
477 case RT5682_PLL_CTRL_2:
478 case RT5682_PLL_TRACK_1:
479 case RT5682_PLL_TRACK_2:
480 case RT5682_PLL_TRACK_3:
481 case RT5682_PLL_TRACK_4:
482 case RT5682_PLL_TRACK_5:
483 case RT5682_PLL_TRACK_6:
484 case RT5682_PLL_TRACK_11:
485 case RT5682_SDW_REF_CLK:
486 case RT5682_DEPOP_1:
487 case RT5682_DEPOP_2:
488 case RT5682_HP_CHARGE_PUMP_1:
489 case RT5682_HP_CHARGE_PUMP_2:
490 case RT5682_MICBIAS_1:
491 case RT5682_MICBIAS_2:
492 case RT5682_PLL_TRACK_12:
493 case RT5682_PLL_TRACK_14:
494 case RT5682_PLL2_CTRL_1:
495 case RT5682_PLL2_CTRL_2:
496 case RT5682_PLL2_CTRL_3:
497 case RT5682_PLL2_CTRL_4:
498 case RT5682_RC_CLK_CTRL:
499 case RT5682_I2S_M_CLK_CTRL_1:
500 case RT5682_I2S2_F_DIV_CTRL_1:
501 case RT5682_I2S2_F_DIV_CTRL_2:
502 case RT5682_EQ_CTRL_1:
503 case RT5682_EQ_CTRL_2:
504 case RT5682_IRQ_CTRL_1:
505 case RT5682_IRQ_CTRL_2:
506 case RT5682_IRQ_CTRL_3:
507 case RT5682_IRQ_CTRL_4:
508 case RT5682_INT_ST_1:
509 case RT5682_GPIO_CTRL_1:
510 case RT5682_GPIO_CTRL_2:
511 case RT5682_GPIO_CTRL_3:
512 case RT5682_HP_AMP_DET_CTRL_1:
513 case RT5682_HP_AMP_DET_CTRL_2:
514 case RT5682_MID_HP_AMP_DET:
515 case RT5682_LOW_HP_AMP_DET:
516 case RT5682_DELAY_BUF_CTRL:
517 case RT5682_SV_ZCD_1:
518 case RT5682_SV_ZCD_2:
519 case RT5682_IL_CMD_1:
520 case RT5682_IL_CMD_2:
521 case RT5682_IL_CMD_3:
522 case RT5682_IL_CMD_4:
523 case RT5682_IL_CMD_5:
524 case RT5682_IL_CMD_6:
525 case RT5682_4BTN_IL_CMD_1:
526 case RT5682_4BTN_IL_CMD_2:
527 case RT5682_4BTN_IL_CMD_3:
528 case RT5682_4BTN_IL_CMD_4:
529 case RT5682_4BTN_IL_CMD_5:
530 case RT5682_4BTN_IL_CMD_6:
531 case RT5682_4BTN_IL_CMD_7:
532 case RT5682_ADC_STO1_HP_CTRL_1:
533 case RT5682_ADC_STO1_HP_CTRL_2:
534 case RT5682_AJD1_CTRL:
535 case RT5682_JD1_THD:
536 case RT5682_JD2_THD:
537 case RT5682_JD_CTRL_1:
538 case RT5682_DUMMY_1:
539 case RT5682_DUMMY_2:
540 case RT5682_DUMMY_3:
541 case RT5682_DAC_ADC_DIG_VOL1:
542 case RT5682_BIAS_CUR_CTRL_2:
543 case RT5682_BIAS_CUR_CTRL_3:
544 case RT5682_BIAS_CUR_CTRL_4:
545 case RT5682_BIAS_CUR_CTRL_5:
546 case RT5682_BIAS_CUR_CTRL_6:
547 case RT5682_BIAS_CUR_CTRL_7:
548 case RT5682_BIAS_CUR_CTRL_8:
549 case RT5682_BIAS_CUR_CTRL_9:
550 case RT5682_BIAS_CUR_CTRL_10:
551 case RT5682_VREF_REC_OP_FB_CAP_CTRL:
552 case RT5682_CHARGE_PUMP_1:
553 case RT5682_DIG_IN_CTRL_1:
554 case RT5682_PAD_DRIVING_CTRL:
555 case RT5682_SOFT_RAMP_DEPOP:
556 case RT5682_CHOP_DAC:
557 case RT5682_CHOP_ADC:
558 case RT5682_CALIB_ADC_CTRL:
559 case RT5682_VOL_TEST:
560 case RT5682_SPKVDD_DET_STA:
561 case RT5682_TEST_MODE_CTRL_1:
562 case RT5682_TEST_MODE_CTRL_2:
563 case RT5682_TEST_MODE_CTRL_3:
564 case RT5682_TEST_MODE_CTRL_4:
565 case RT5682_TEST_MODE_CTRL_5:
566 case RT5682_PLL1_INTERNAL:
567 case RT5682_PLL2_INTERNAL:
568 case RT5682_STO_NG2_CTRL_1:
569 case RT5682_STO_NG2_CTRL_2:
570 case RT5682_STO_NG2_CTRL_3:
571 case RT5682_STO_NG2_CTRL_4:
572 case RT5682_STO_NG2_CTRL_5:
573 case RT5682_STO_NG2_CTRL_6:
574 case RT5682_STO_NG2_CTRL_7:
575 case RT5682_STO_NG2_CTRL_8:
576 case RT5682_STO_NG2_CTRL_9:
577 case RT5682_STO_NG2_CTRL_10:
578 case RT5682_STO1_DAC_SIL_DET:
579 case RT5682_SIL_PSV_CTRL1:
580 case RT5682_SIL_PSV_CTRL2:
581 case RT5682_SIL_PSV_CTRL3:
582 case RT5682_SIL_PSV_CTRL4:
583 case RT5682_SIL_PSV_CTRL5:
584 case RT5682_HP_IMP_SENS_CTRL_01:
585 case RT5682_HP_IMP_SENS_CTRL_02:
586 case RT5682_HP_IMP_SENS_CTRL_03:
587 case RT5682_HP_IMP_SENS_CTRL_04:
588 case RT5682_HP_IMP_SENS_CTRL_05:
589 case RT5682_HP_IMP_SENS_CTRL_06:
590 case RT5682_HP_IMP_SENS_CTRL_07:
591 case RT5682_HP_IMP_SENS_CTRL_08:
592 case RT5682_HP_IMP_SENS_CTRL_09:
593 case RT5682_HP_IMP_SENS_CTRL_10:
594 case RT5682_HP_IMP_SENS_CTRL_11:
595 case RT5682_HP_IMP_SENS_CTRL_12:
596 case RT5682_HP_IMP_SENS_CTRL_13:
597 case RT5682_HP_IMP_SENS_CTRL_14:
598 case RT5682_HP_IMP_SENS_CTRL_15:
599 case RT5682_HP_IMP_SENS_CTRL_16:
600 case RT5682_HP_IMP_SENS_CTRL_17:
601 case RT5682_HP_IMP_SENS_CTRL_18:
602 case RT5682_HP_IMP_SENS_CTRL_19:
603 case RT5682_HP_IMP_SENS_CTRL_20:
604 case RT5682_HP_IMP_SENS_CTRL_21:
605 case RT5682_HP_IMP_SENS_CTRL_22:
606 case RT5682_HP_IMP_SENS_CTRL_23:
607 case RT5682_HP_IMP_SENS_CTRL_24:
608 case RT5682_HP_IMP_SENS_CTRL_25:
609 case RT5682_HP_IMP_SENS_CTRL_26:
610 case RT5682_HP_IMP_SENS_CTRL_27:
611 case RT5682_HP_IMP_SENS_CTRL_28:
612 case RT5682_HP_IMP_SENS_CTRL_29:
613 case RT5682_HP_IMP_SENS_CTRL_30:
614 case RT5682_HP_IMP_SENS_CTRL_31:
615 case RT5682_HP_IMP_SENS_CTRL_32:
616 case RT5682_HP_IMP_SENS_CTRL_33:
617 case RT5682_HP_IMP_SENS_CTRL_34:
618 case RT5682_HP_IMP_SENS_CTRL_35:
619 case RT5682_HP_IMP_SENS_CTRL_36:
620 case RT5682_HP_IMP_SENS_CTRL_37:
621 case RT5682_HP_IMP_SENS_CTRL_38:
622 case RT5682_HP_IMP_SENS_CTRL_39:
623 case RT5682_HP_IMP_SENS_CTRL_40:
624 case RT5682_HP_IMP_SENS_CTRL_41:
625 case RT5682_HP_IMP_SENS_CTRL_42:
626 case RT5682_HP_IMP_SENS_CTRL_43:
627 case RT5682_HP_LOGIC_CTRL_1:
628 case RT5682_HP_LOGIC_CTRL_2:
629 case RT5682_HP_LOGIC_CTRL_3:
630 case RT5682_HP_CALIB_CTRL_1:
631 case RT5682_HP_CALIB_CTRL_2:
632 case RT5682_HP_CALIB_CTRL_3:
633 case RT5682_HP_CALIB_CTRL_4:
634 case RT5682_HP_CALIB_CTRL_5:
635 case RT5682_HP_CALIB_CTRL_6:
636 case RT5682_HP_CALIB_CTRL_7:
637 case RT5682_HP_CALIB_CTRL_9:
638 case RT5682_HP_CALIB_CTRL_10:
639 case RT5682_HP_CALIB_CTRL_11:
640 case RT5682_HP_CALIB_STA_1:
641 case RT5682_HP_CALIB_STA_2:
642 case RT5682_HP_CALIB_STA_3:
643 case RT5682_HP_CALIB_STA_4:
644 case RT5682_HP_CALIB_STA_5:
645 case RT5682_HP_CALIB_STA_6:
646 case RT5682_HP_CALIB_STA_7:
647 case RT5682_HP_CALIB_STA_8:
648 case RT5682_HP_CALIB_STA_9:
649 case RT5682_HP_CALIB_STA_10:
650 case RT5682_HP_CALIB_STA_11:
651 case RT5682_SAR_IL_CMD_1:
652 case RT5682_SAR_IL_CMD_2:
653 case RT5682_SAR_IL_CMD_3:
654 case RT5682_SAR_IL_CMD_4:
655 case RT5682_SAR_IL_CMD_5:
656 case RT5682_SAR_IL_CMD_6:
657 case RT5682_SAR_IL_CMD_7:
658 case RT5682_SAR_IL_CMD_8:
659 case RT5682_SAR_IL_CMD_9:
660 case RT5682_SAR_IL_CMD_10:
661 case RT5682_SAR_IL_CMD_11:
662 case RT5682_SAR_IL_CMD_12:
663 case RT5682_SAR_IL_CMD_13:
664 case RT5682_EFUSE_CTRL_1:
665 case RT5682_EFUSE_CTRL_2:
666 case RT5682_EFUSE_CTRL_3:
667 case RT5682_EFUSE_CTRL_4:
668 case RT5682_EFUSE_CTRL_5:
669 case RT5682_EFUSE_CTRL_6:
670 case RT5682_EFUSE_CTRL_7:
671 case RT5682_EFUSE_CTRL_8:
672 case RT5682_EFUSE_CTRL_9:
673 case RT5682_EFUSE_CTRL_10:
674 case RT5682_EFUSE_CTRL_11:
675 case RT5682_JD_TOP_VC_VTRL:
676 case RT5682_DRC1_CTRL_0:
677 case RT5682_DRC1_CTRL_1:
678 case RT5682_DRC1_CTRL_2:
679 case RT5682_DRC1_CTRL_3:
680 case RT5682_DRC1_CTRL_4:
681 case RT5682_DRC1_CTRL_5:
682 case RT5682_DRC1_CTRL_6:
683 case RT5682_DRC1_HARD_LMT_CTRL_1:
684 case RT5682_DRC1_HARD_LMT_CTRL_2:
685 case RT5682_DRC1_PRIV_1:
686 case RT5682_DRC1_PRIV_2:
687 case RT5682_DRC1_PRIV_3:
688 case RT5682_DRC1_PRIV_4:
689 case RT5682_DRC1_PRIV_5:
690 case RT5682_DRC1_PRIV_6:
691 case RT5682_DRC1_PRIV_7:
692 case RT5682_DRC1_PRIV_8:
693 case RT5682_EQ_AUTO_RCV_CTRL1:
694 case RT5682_EQ_AUTO_RCV_CTRL2:
695 case RT5682_EQ_AUTO_RCV_CTRL3:
696 case RT5682_EQ_AUTO_RCV_CTRL4:
697 case RT5682_EQ_AUTO_RCV_CTRL5:
698 case RT5682_EQ_AUTO_RCV_CTRL6:
699 case RT5682_EQ_AUTO_RCV_CTRL7:
700 case RT5682_EQ_AUTO_RCV_CTRL8:
701 case RT5682_EQ_AUTO_RCV_CTRL9:
702 case RT5682_EQ_AUTO_RCV_CTRL10:
703 case RT5682_EQ_AUTO_RCV_CTRL11:
704 case RT5682_EQ_AUTO_RCV_CTRL12:
705 case RT5682_EQ_AUTO_RCV_CTRL13:
706 case RT5682_ADC_L_EQ_LPF1_A1:
707 case RT5682_R_EQ_LPF1_A1:
708 case RT5682_L_EQ_LPF1_H0:
709 case RT5682_R_EQ_LPF1_H0:
710 case RT5682_L_EQ_BPF1_A1:
711 case RT5682_R_EQ_BPF1_A1:
712 case RT5682_L_EQ_BPF1_A2:
713 case RT5682_R_EQ_BPF1_A2:
714 case RT5682_L_EQ_BPF1_H0:
715 case RT5682_R_EQ_BPF1_H0:
716 case RT5682_L_EQ_BPF2_A1:
717 case RT5682_R_EQ_BPF2_A1:
718 case RT5682_L_EQ_BPF2_A2:
719 case RT5682_R_EQ_BPF2_A2:
720 case RT5682_L_EQ_BPF2_H0:
721 case RT5682_R_EQ_BPF2_H0:
722 case RT5682_L_EQ_BPF3_A1:
723 case RT5682_R_EQ_BPF3_A1:
724 case RT5682_L_EQ_BPF3_A2:
725 case RT5682_R_EQ_BPF3_A2:
726 case RT5682_L_EQ_BPF3_H0:
727 case RT5682_R_EQ_BPF3_H0:
728 case RT5682_L_EQ_BPF4_A1:
729 case RT5682_R_EQ_BPF4_A1:
730 case RT5682_L_EQ_BPF4_A2:
731 case RT5682_R_EQ_BPF4_A2:
732 case RT5682_L_EQ_BPF4_H0:
733 case RT5682_R_EQ_BPF4_H0:
734 case RT5682_L_EQ_HPF1_A1:
735 case RT5682_R_EQ_HPF1_A1:
736 case RT5682_L_EQ_HPF1_H0:
737 case RT5682_R_EQ_HPF1_H0:
738 case RT5682_L_EQ_PRE_VOL:
739 case RT5682_R_EQ_PRE_VOL:
740 case RT5682_L_EQ_POST_VOL:
741 case RT5682_R_EQ_POST_VOL:
742 case RT5682_I2C_MODE:
743 return true;
744 default:
745 return false;
746 }
747 }
748 EXPORT_SYMBOL_GPL(rt5682_readable_register);
749
750 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
751 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
752 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
753
754 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
755 static const DECLARE_TLV_DB_RANGE(bst_tlv,
756 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
757 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
758 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
759 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
760 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
761 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
762 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
763 );
764
765 /* Interface data select */
766 static const char * const rt5682_data_select[] = {
767 "L/R", "R/L", "L/L", "R/R"
768 };
769
770 static SOC_ENUM_SINGLE_DECL(rt5682_if2_adc_enum,
771 RT5682_DIG_INF2_DATA, RT5682_IF2_ADC_SEL_SFT, rt5682_data_select);
772
773 static SOC_ENUM_SINGLE_DECL(rt5682_if1_01_adc_enum,
774 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC1_SEL_SFT, rt5682_data_select);
775
776 static SOC_ENUM_SINGLE_DECL(rt5682_if1_23_adc_enum,
777 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC2_SEL_SFT, rt5682_data_select);
778
779 static SOC_ENUM_SINGLE_DECL(rt5682_if1_45_adc_enum,
780 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC3_SEL_SFT, rt5682_data_select);
781
782 static SOC_ENUM_SINGLE_DECL(rt5682_if1_67_adc_enum,
783 RT5682_TDM_ADDA_CTRL_1, RT5682_IF1_ADC4_SEL_SFT, rt5682_data_select);
784
785 static const struct snd_kcontrol_new rt5682_if2_adc_swap_mux =
786 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5682_if2_adc_enum);
787
788 static const struct snd_kcontrol_new rt5682_if1_01_adc_swap_mux =
789 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5682_if1_01_adc_enum);
790
791 static const struct snd_kcontrol_new rt5682_if1_23_adc_swap_mux =
792 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5682_if1_23_adc_enum);
793
794 static const struct snd_kcontrol_new rt5682_if1_45_adc_swap_mux =
795 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5682_if1_45_adc_enum);
796
797 static const struct snd_kcontrol_new rt5682_if1_67_adc_swap_mux =
798 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5682_if1_67_adc_enum);
799
800 static const char * const rt5682_dac_select[] = {
801 "IF1", "SOUND"
802 };
803
804 static SOC_ENUM_SINGLE_DECL(rt5682_dacl_enum,
805 RT5682_AD_DA_MIXER, RT5682_DAC1_L_SEL_SFT, rt5682_dac_select);
806
807 static const struct snd_kcontrol_new rt5682_dac_l_mux =
808 SOC_DAPM_ENUM("DAC L Mux", rt5682_dacl_enum);
809
810 static SOC_ENUM_SINGLE_DECL(rt5682_dacr_enum,
811 RT5682_AD_DA_MIXER, RT5682_DAC1_R_SEL_SFT, rt5682_dac_select);
812
813 static const struct snd_kcontrol_new rt5682_dac_r_mux =
814 SOC_DAPM_ENUM("DAC R Mux", rt5682_dacr_enum);
815
rt5682_reset(struct rt5682_priv * rt5682)816 void rt5682_reset(struct rt5682_priv *rt5682)
817 {
818 regmap_write(rt5682->regmap, RT5682_RESET, 0);
819 if (!rt5682->is_sdw)
820 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1);
821 }
822 EXPORT_SYMBOL_GPL(rt5682_reset);
823
824 /**
825 * rt5682_sel_asrc_clk_src - select ASRC clock source for a set of filters
826 * @component: SoC audio component device.
827 * @filter_mask: mask of filters.
828 * @clk_src: clock source
829 *
830 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5682 can
831 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
832 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
833 * ASRC function will track i2s clock and generate a corresponding system clock
834 * for codec. This function provides an API to select the clock source for a
835 * set of filters specified by the mask. And the component driver will turn on
836 * ASRC for these filters if ASRC is selected as their clock source.
837 */
rt5682_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)838 int rt5682_sel_asrc_clk_src(struct snd_soc_component *component,
839 unsigned int filter_mask, unsigned int clk_src)
840 {
841 switch (clk_src) {
842 case RT5682_CLK_SEL_SYS:
843 case RT5682_CLK_SEL_I2S1_ASRC:
844 case RT5682_CLK_SEL_I2S2_ASRC:
845 break;
846
847 default:
848 return -EINVAL;
849 }
850
851 if (filter_mask & RT5682_DA_STEREO1_FILTER) {
852 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_2,
853 RT5682_FILTER_CLK_SEL_MASK,
854 clk_src << RT5682_FILTER_CLK_SEL_SFT);
855 }
856
857 if (filter_mask & RT5682_AD_STEREO1_FILTER) {
858 snd_soc_component_update_bits(component, RT5682_PLL_TRACK_3,
859 RT5682_FILTER_CLK_SEL_MASK,
860 clk_src << RT5682_FILTER_CLK_SEL_SFT);
861 }
862
863 return 0;
864 }
865 EXPORT_SYMBOL_GPL(rt5682_sel_asrc_clk_src);
866
rt5682_button_detect(struct snd_soc_component * component)867 static int rt5682_button_detect(struct snd_soc_component *component)
868 {
869 int btn_type, val;
870
871 val = snd_soc_component_read(component, RT5682_4BTN_IL_CMD_1);
872 btn_type = val & 0xfff0;
873 snd_soc_component_write(component, RT5682_4BTN_IL_CMD_1, val);
874 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type);
875 snd_soc_component_update_bits(component,
876 RT5682_SAR_IL_CMD_2, 0x10, 0x10);
877
878 return btn_type;
879 }
880
rt5682_enable_push_button_irq(struct snd_soc_component * component,bool enable)881 static void rt5682_enable_push_button_irq(struct snd_soc_component *component,
882 bool enable)
883 {
884 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
885
886 if (enable) {
887 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
888 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_EN);
889 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
890 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_BTN);
891 snd_soc_component_write(component, RT5682_IL_CMD_1, 0x0040);
892 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
893 RT5682_4BTN_IL_MASK | RT5682_4BTN_IL_RST_MASK,
894 RT5682_4BTN_IL_EN | RT5682_4BTN_IL_NOR);
895 if (rt5682->is_sdw)
896 snd_soc_component_update_bits(component,
897 RT5682_IRQ_CTRL_3,
898 RT5682_IL_IRQ_MASK | RT5682_IL_IRQ_TYPE_MASK,
899 RT5682_IL_IRQ_EN | RT5682_IL_IRQ_PUL);
900 else
901 snd_soc_component_update_bits(component,
902 RT5682_IRQ_CTRL_3, RT5682_IL_IRQ_MASK,
903 RT5682_IL_IRQ_EN);
904 } else {
905 snd_soc_component_update_bits(component, RT5682_IRQ_CTRL_3,
906 RT5682_IL_IRQ_MASK, RT5682_IL_IRQ_DIS);
907 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
908 RT5682_SAR_BUTT_DET_MASK, RT5682_SAR_BUTT_DET_DIS);
909 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
910 RT5682_4BTN_IL_MASK, RT5682_4BTN_IL_DIS);
911 snd_soc_component_update_bits(component, RT5682_4BTN_IL_CMD_2,
912 RT5682_4BTN_IL_RST_MASK, RT5682_4BTN_IL_RST);
913 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_13,
914 RT5682_SAR_SOUR_MASK, RT5682_SAR_SOUR_TYPE);
915 }
916 }
917
918 /**
919 * rt5682_headset_detect - Detect headset.
920 * @component: SoC audio component device.
921 * @jack_insert: Jack insert or not.
922 *
923 * Detect whether is headset or not when jack inserted.
924 *
925 * Returns detect status.
926 */
rt5682_headset_detect(struct snd_soc_component * component,int jack_insert)927 static int rt5682_headset_detect(struct snd_soc_component *component, int jack_insert)
928 {
929 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
930 struct snd_soc_dapm_context *dapm = &component->dapm;
931 unsigned int val, count;
932
933 if (jack_insert) {
934 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
935 RT5682_PWR_VREF2 | RT5682_PWR_MB,
936 RT5682_PWR_VREF2 | RT5682_PWR_MB);
937 snd_soc_component_update_bits(component,
938 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
939 usleep_range(15000, 20000);
940 snd_soc_component_update_bits(component,
941 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, RT5682_PWR_FV2);
942 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
943 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
944 snd_soc_component_update_bits(component,
945 RT5682_HP_CHARGE_PUMP_1,
946 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
947 rt5682_enable_push_button_irq(component, false);
948 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
949 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
950 usleep_range(55000, 60000);
951 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
952 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_HIGH);
953
954 count = 0;
955 val = snd_soc_component_read(component, RT5682_CBJ_CTRL_2)
956 & RT5682_JACK_TYPE_MASK;
957 while (val == 0 && count < 50) {
958 usleep_range(10000, 15000);
959 val = snd_soc_component_read(component,
960 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
961 count++;
962 }
963
964 switch (val) {
965 case 0x1:
966 case 0x2:
967 rt5682->jack_type = SND_JACK_HEADSET;
968 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
969 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_EN);
970 rt5682_enable_push_button_irq(component, true);
971 break;
972 default:
973 rt5682->jack_type = SND_JACK_HEADPHONE;
974 break;
975 }
976
977 snd_soc_component_update_bits(component,
978 RT5682_HP_CHARGE_PUMP_1,
979 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK,
980 RT5682_OSW_L_EN | RT5682_OSW_R_EN);
981 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
982 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
983 RT5682_PWR_CLK25M_PU | RT5682_PWR_CLK1M_PU);
984 } else {
985 rt5682_enable_push_button_irq(component, false);
986 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
987 RT5682_TRIG_JD_MASK, RT5682_TRIG_JD_LOW);
988 if (!snd_soc_dapm_get_pin_status(dapm, "MICBIAS") &&
989 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
990 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
991 snd_soc_component_update_bits(component,
992 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
993 if (!snd_soc_dapm_get_pin_status(dapm, "Vref2") &&
994 !snd_soc_dapm_get_pin_status(dapm, "PLL1") &&
995 !snd_soc_dapm_get_pin_status(dapm, "PLL2B"))
996 snd_soc_component_update_bits(component,
997 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
998 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
999 RT5682_PWR_CBJ, 0);
1000 snd_soc_component_update_bits(component, RT5682_MICBIAS_2,
1001 RT5682_PWR_CLK25M_MASK | RT5682_PWR_CLK1M_MASK,
1002 RT5682_PWR_CLK25M_PD | RT5682_PWR_CLK1M_PD);
1003 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
1004 RT5682_FAST_OFF_MASK, RT5682_FAST_OFF_DIS);
1005
1006 rt5682->jack_type = 0;
1007 }
1008
1009 dev_dbg(component->dev, "jack_type = %d\n", rt5682->jack_type);
1010 return rt5682->jack_type;
1011 }
1012
rt5682_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hs_jack,void * data)1013 static int rt5682_set_jack_detect(struct snd_soc_component *component,
1014 struct snd_soc_jack *hs_jack, void *data)
1015 {
1016 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1017
1018 rt5682->hs_jack = hs_jack;
1019
1020 if (!hs_jack) {
1021 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1022 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1023 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1024 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1025 cancel_delayed_work_sync(&rt5682->jack_detect_work);
1026
1027 return 0;
1028 }
1029
1030 if (!rt5682->is_sdw) {
1031 switch (rt5682->pdata.jd_src) {
1032 case RT5682_JD1:
1033 snd_soc_component_update_bits(component,
1034 RT5682_CBJ_CTRL_5, 0x0700, 0x0600);
1035 snd_soc_component_update_bits(component,
1036 RT5682_CBJ_CTRL_2, RT5682_EXT_JD_SRC,
1037 RT5682_EXT_JD_SRC_MANUAL);
1038 snd_soc_component_write(component, RT5682_CBJ_CTRL_1,
1039 0xd142);
1040 snd_soc_component_update_bits(component,
1041 RT5682_CBJ_CTRL_3, RT5682_CBJ_IN_BUF_EN,
1042 RT5682_CBJ_IN_BUF_EN);
1043 snd_soc_component_update_bits(component,
1044 RT5682_SAR_IL_CMD_1, RT5682_SAR_POW_MASK,
1045 RT5682_SAR_POW_EN);
1046 regmap_update_bits(rt5682->regmap, RT5682_GPIO_CTRL_1,
1047 RT5682_GP1_PIN_MASK, RT5682_GP1_PIN_IRQ);
1048 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1049 RT5682_POW_IRQ | RT5682_POW_JDH |
1050 RT5682_POW_ANA, RT5682_POW_IRQ |
1051 RT5682_POW_JDH | RT5682_POW_ANA);
1052 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_2,
1053 RT5682_PWR_JDH, RT5682_PWR_JDH);
1054 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1055 RT5682_JD1_EN_MASK | RT5682_JD1_POL_MASK,
1056 RT5682_JD1_EN | RT5682_JD1_POL_NOR);
1057 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_4,
1058 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1059 rt5682->pdata.btndet_delay));
1060 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_5,
1061 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1062 rt5682->pdata.btndet_delay));
1063 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_6,
1064 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1065 rt5682->pdata.btndet_delay));
1066 regmap_update_bits(rt5682->regmap, RT5682_4BTN_IL_CMD_7,
1067 0x7f7f, (rt5682->pdata.btndet_delay << 8 |
1068 rt5682->pdata.btndet_delay));
1069 mod_delayed_work(system_power_efficient_wq,
1070 &rt5682->jack_detect_work,
1071 msecs_to_jiffies(250));
1072 break;
1073
1074 case RT5682_JD_NULL:
1075 regmap_update_bits(rt5682->regmap, RT5682_IRQ_CTRL_2,
1076 RT5682_JD1_EN_MASK, RT5682_JD1_DIS);
1077 regmap_update_bits(rt5682->regmap, RT5682_RC_CLK_CTRL,
1078 RT5682_POW_JDH | RT5682_POW_JDL, 0);
1079 break;
1080
1081 default:
1082 dev_warn(component->dev, "Wrong JD source\n");
1083 break;
1084 }
1085 }
1086
1087 return 0;
1088 }
1089
rt5682_jack_detect_handler(struct work_struct * work)1090 void rt5682_jack_detect_handler(struct work_struct *work)
1091 {
1092 struct rt5682_priv *rt5682 =
1093 container_of(work, struct rt5682_priv, jack_detect_work.work);
1094 struct snd_soc_dapm_context *dapm;
1095 int val, btn_type;
1096
1097 if (!rt5682->component ||
1098 !snd_soc_card_is_instantiated(rt5682->component->card)) {
1099 /* card not yet ready, try later */
1100 mod_delayed_work(system_power_efficient_wq,
1101 &rt5682->jack_detect_work, msecs_to_jiffies(15));
1102 return;
1103 }
1104
1105 if (rt5682->is_sdw) {
1106 if (pm_runtime_status_suspended(rt5682->slave->dev.parent)) {
1107 dev_dbg(&rt5682->slave->dev,
1108 "%s: parent device is pm_runtime_status_suspended, skipping jack detection\n",
1109 __func__);
1110 return;
1111 }
1112 }
1113
1114 dapm = snd_soc_component_get_dapm(rt5682->component);
1115
1116 snd_soc_dapm_mutex_lock(dapm);
1117 mutex_lock(&rt5682->calibrate_mutex);
1118
1119 val = snd_soc_component_read(rt5682->component, RT5682_AJD1_CTRL)
1120 & RT5682_JDH_RS_MASK;
1121 if (!val) {
1122 /* jack in */
1123 if (rt5682->jack_type == 0) {
1124 /* jack was out, report jack type */
1125 rt5682->jack_type =
1126 rt5682_headset_detect(rt5682->component, 1);
1127 rt5682->irq_work_delay_time = 0;
1128 } else if ((rt5682->jack_type & SND_JACK_HEADSET) ==
1129 SND_JACK_HEADSET) {
1130 /* jack is already in, report button event */
1131 rt5682->jack_type = SND_JACK_HEADSET;
1132 btn_type = rt5682_button_detect(rt5682->component);
1133 /**
1134 * rt5682 can report three kinds of button behavior,
1135 * one click, double click and hold. However,
1136 * currently we will report button pressed/released
1137 * event. So all the three button behaviors are
1138 * treated as button pressed.
1139 */
1140 switch (btn_type) {
1141 case 0x8000:
1142 case 0x4000:
1143 case 0x2000:
1144 rt5682->jack_type |= SND_JACK_BTN_0;
1145 break;
1146 case 0x1000:
1147 case 0x0800:
1148 case 0x0400:
1149 rt5682->jack_type |= SND_JACK_BTN_1;
1150 break;
1151 case 0x0200:
1152 case 0x0100:
1153 case 0x0080:
1154 rt5682->jack_type |= SND_JACK_BTN_2;
1155 break;
1156 case 0x0040:
1157 case 0x0020:
1158 case 0x0010:
1159 rt5682->jack_type |= SND_JACK_BTN_3;
1160 break;
1161 case 0x0000: /* unpressed */
1162 break;
1163 default:
1164 dev_err(rt5682->component->dev,
1165 "Unexpected button code 0x%04x\n",
1166 btn_type);
1167 break;
1168 }
1169 }
1170 } else {
1171 /* jack out */
1172 rt5682->jack_type = rt5682_headset_detect(rt5682->component, 0);
1173 rt5682->irq_work_delay_time = 50;
1174 }
1175
1176 mutex_unlock(&rt5682->calibrate_mutex);
1177 snd_soc_dapm_mutex_unlock(dapm);
1178
1179 snd_soc_jack_report(rt5682->hs_jack, rt5682->jack_type,
1180 SND_JACK_HEADSET |
1181 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1182 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1183
1184 if (!rt5682->is_sdw) {
1185 if (rt5682->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1186 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1187 schedule_delayed_work(&rt5682->jd_check_work, 0);
1188 else
1189 cancel_delayed_work_sync(&rt5682->jd_check_work);
1190 }
1191 }
1192 EXPORT_SYMBOL_GPL(rt5682_jack_detect_handler);
1193
1194 static const struct snd_kcontrol_new rt5682_snd_controls[] = {
1195 /* DAC Digital Volume */
1196 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5682_DAC1_DIG_VOL,
1197 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
1198
1199 /* IN Boost Volume */
1200 SOC_SINGLE_TLV("CBJ Boost Volume", RT5682_CBJ_BST_CTRL,
1201 RT5682_BST_CBJ_SFT, 8, 0, bst_tlv),
1202
1203 /* ADC Digital Volume Control */
1204 SOC_DOUBLE("STO1 ADC Capture Switch", RT5682_STO1_ADC_DIG_VOL,
1205 RT5682_L_MUTE_SFT, RT5682_R_MUTE_SFT, 1, 1),
1206 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5682_STO1_ADC_DIG_VOL,
1207 RT5682_L_VOL_SFT + 1, RT5682_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
1208
1209 /* ADC Boost Volume Control */
1210 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5682_STO1_ADC_BOOST,
1211 RT5682_STO1_ADC_L_BST_SFT, RT5682_STO1_ADC_R_BST_SFT,
1212 3, 0, adc_bst_tlv),
1213 };
1214
rt5682_div_sel(struct rt5682_priv * rt5682,int target,const int div[],int size)1215 static int rt5682_div_sel(struct rt5682_priv *rt5682,
1216 int target, const int div[], int size)
1217 {
1218 int i;
1219
1220 if (rt5682->sysclk < target) {
1221 dev_err(rt5682->component->dev,
1222 "sysclk rate %d is too low\n", rt5682->sysclk);
1223 return 0;
1224 }
1225
1226 for (i = 0; i < size - 1; i++) {
1227 dev_dbg(rt5682->component->dev, "div[%d]=%d\n", i, div[i]);
1228 if (target * div[i] == rt5682->sysclk)
1229 return i;
1230 if (target * div[i + 1] > rt5682->sysclk) {
1231 dev_dbg(rt5682->component->dev,
1232 "can't find div for sysclk %d\n",
1233 rt5682->sysclk);
1234 return i;
1235 }
1236 }
1237
1238 if (target * div[i] < rt5682->sysclk)
1239 dev_err(rt5682->component->dev,
1240 "sysclk rate %d is too high\n", rt5682->sysclk);
1241
1242 return size - 1;
1243 }
1244
1245 /**
1246 * set_dmic_clk - Set parameter of dmic.
1247 *
1248 * @w: DAPM widget.
1249 * @kcontrol: The kcontrol of this widget.
1250 * @event: Event id.
1251 *
1252 * Choose dmic clock between 1MHz and 3MHz.
1253 * It is better for clock to approximate 3MHz.
1254 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1255 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1256 struct snd_kcontrol *kcontrol, int event)
1257 {
1258 struct snd_soc_component *component =
1259 snd_soc_dapm_to_component(w->dapm);
1260 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1261 int idx, dmic_clk_rate = 3072000;
1262 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1263
1264 if (rt5682->pdata.dmic_clk_rate)
1265 dmic_clk_rate = rt5682->pdata.dmic_clk_rate;
1266
1267 idx = rt5682_div_sel(rt5682, dmic_clk_rate, div, ARRAY_SIZE(div));
1268
1269 snd_soc_component_update_bits(component, RT5682_DMIC_CTRL_1,
1270 RT5682_DMIC_CLK_MASK, idx << RT5682_DMIC_CLK_SFT);
1271
1272 return 0;
1273 }
1274
set_filter_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1275 static int set_filter_clk(struct snd_soc_dapm_widget *w,
1276 struct snd_kcontrol *kcontrol, int event)
1277 {
1278 struct snd_soc_component *component =
1279 snd_soc_dapm_to_component(w->dapm);
1280 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1281 int ref, val, reg, idx;
1282 static const int div_f[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1283 static const int div_o[] = {1, 2, 4, 6, 8, 12, 16, 24, 32, 48};
1284
1285 if (rt5682->is_sdw)
1286 return 0;
1287
1288 val = snd_soc_component_read(component, RT5682_GPIO_CTRL_1) &
1289 RT5682_GP4_PIN_MASK;
1290 if (w->shift == RT5682_PWR_ADC_S1F_BIT &&
1291 val == RT5682_GP4_PIN_ADCDAT2)
1292 ref = 256 * rt5682->lrck[RT5682_AIF2];
1293 else
1294 ref = 256 * rt5682->lrck[RT5682_AIF1];
1295
1296 idx = rt5682_div_sel(rt5682, ref, div_f, ARRAY_SIZE(div_f));
1297
1298 if (w->shift == RT5682_PWR_ADC_S1F_BIT)
1299 reg = RT5682_PLL_TRACK_3;
1300 else
1301 reg = RT5682_PLL_TRACK_2;
1302
1303 snd_soc_component_update_bits(component, reg,
1304 RT5682_FILTER_CLK_DIV_MASK, idx << RT5682_FILTER_CLK_DIV_SFT);
1305
1306 /* select over sample rate */
1307 for (idx = 0; idx < ARRAY_SIZE(div_o); idx++) {
1308 if (rt5682->sysclk <= 12288000 * div_o[idx])
1309 break;
1310 }
1311
1312 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
1313 RT5682_ADC_OSR_MASK | RT5682_DAC_OSR_MASK,
1314 (idx << RT5682_ADC_OSR_SFT) | (idx << RT5682_DAC_OSR_SFT));
1315
1316 return 0;
1317 }
1318
is_sys_clk_from_pll1(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1319 static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1320 struct snd_soc_dapm_widget *sink)
1321 {
1322 unsigned int val;
1323 struct snd_soc_component *component =
1324 snd_soc_dapm_to_component(w->dapm);
1325
1326 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1327 val &= RT5682_SCLK_SRC_MASK;
1328 if (val == RT5682_SCLK_SRC_PLL1)
1329 return 1;
1330 else
1331 return 0;
1332 }
1333
is_sys_clk_from_pll2(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1334 static int is_sys_clk_from_pll2(struct snd_soc_dapm_widget *w,
1335 struct snd_soc_dapm_widget *sink)
1336 {
1337 unsigned int val;
1338 struct snd_soc_component *component =
1339 snd_soc_dapm_to_component(w->dapm);
1340
1341 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1342 val &= RT5682_SCLK_SRC_MASK;
1343 if (val == RT5682_SCLK_SRC_PLL2)
1344 return 1;
1345 else
1346 return 0;
1347 }
1348
is_using_asrc(struct snd_soc_dapm_widget * w,struct snd_soc_dapm_widget * sink)1349 static int is_using_asrc(struct snd_soc_dapm_widget *w,
1350 struct snd_soc_dapm_widget *sink)
1351 {
1352 unsigned int reg, shift, val;
1353 struct snd_soc_component *component =
1354 snd_soc_dapm_to_component(w->dapm);
1355
1356 switch (w->shift) {
1357 case RT5682_ADC_STO1_ASRC_SFT:
1358 reg = RT5682_PLL_TRACK_3;
1359 shift = RT5682_FILTER_CLK_SEL_SFT;
1360 break;
1361 case RT5682_DAC_STO1_ASRC_SFT:
1362 reg = RT5682_PLL_TRACK_2;
1363 shift = RT5682_FILTER_CLK_SEL_SFT;
1364 break;
1365 default:
1366 return 0;
1367 }
1368
1369 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
1370 switch (val) {
1371 case RT5682_CLK_SEL_I2S1_ASRC:
1372 case RT5682_CLK_SEL_I2S2_ASRC:
1373 return 1;
1374 default:
1375 return 0;
1376 }
1377 }
1378
1379 /* Digital Mixer */
1380 static const struct snd_kcontrol_new rt5682_sto1_adc_l_mix[] = {
1381 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1382 RT5682_M_STO1_ADC_L1_SFT, 1, 1),
1383 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1384 RT5682_M_STO1_ADC_L2_SFT, 1, 1),
1385 };
1386
1387 static const struct snd_kcontrol_new rt5682_sto1_adc_r_mix[] = {
1388 SOC_DAPM_SINGLE("ADC1 Switch", RT5682_STO1_ADC_MIXER,
1389 RT5682_M_STO1_ADC_R1_SFT, 1, 1),
1390 SOC_DAPM_SINGLE("ADC2 Switch", RT5682_STO1_ADC_MIXER,
1391 RT5682_M_STO1_ADC_R2_SFT, 1, 1),
1392 };
1393
1394 static const struct snd_kcontrol_new rt5682_dac_l_mix[] = {
1395 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1396 RT5682_M_ADCMIX_L_SFT, 1, 1),
1397 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1398 RT5682_M_DAC1_L_SFT, 1, 1),
1399 };
1400
1401 static const struct snd_kcontrol_new rt5682_dac_r_mix[] = {
1402 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5682_AD_DA_MIXER,
1403 RT5682_M_ADCMIX_R_SFT, 1, 1),
1404 SOC_DAPM_SINGLE("DAC1 Switch", RT5682_AD_DA_MIXER,
1405 RT5682_M_DAC1_R_SFT, 1, 1),
1406 };
1407
1408 static const struct snd_kcontrol_new rt5682_sto1_dac_l_mix[] = {
1409 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1410 RT5682_M_DAC_L1_STO_L_SFT, 1, 1),
1411 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1412 RT5682_M_DAC_R1_STO_L_SFT, 1, 1),
1413 };
1414
1415 static const struct snd_kcontrol_new rt5682_sto1_dac_r_mix[] = {
1416 SOC_DAPM_SINGLE("DAC L1 Switch", RT5682_STO1_DAC_MIXER,
1417 RT5682_M_DAC_L1_STO_R_SFT, 1, 1),
1418 SOC_DAPM_SINGLE("DAC R1 Switch", RT5682_STO1_DAC_MIXER,
1419 RT5682_M_DAC_R1_STO_R_SFT, 1, 1),
1420 };
1421
1422 /* Analog Input Mixer */
1423 static const struct snd_kcontrol_new rt5682_rec1_l_mix[] = {
1424 SOC_DAPM_SINGLE("CBJ Switch", RT5682_REC_MIXER,
1425 RT5682_M_CBJ_RM1_L_SFT, 1, 1),
1426 };
1427
1428 /* STO1 ADC1 Source */
1429 /* MX-26 [13] [5] */
1430 static const char * const rt5682_sto1_adc1_src[] = {
1431 "DAC MIX", "ADC"
1432 };
1433
1434 static SOC_ENUM_SINGLE_DECL(
1435 rt5682_sto1_adc1l_enum, RT5682_STO1_ADC_MIXER,
1436 RT5682_STO1_ADC1L_SRC_SFT, rt5682_sto1_adc1_src);
1437
1438 static const struct snd_kcontrol_new rt5682_sto1_adc1l_mux =
1439 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1l_enum);
1440
1441 static SOC_ENUM_SINGLE_DECL(
1442 rt5682_sto1_adc1r_enum, RT5682_STO1_ADC_MIXER,
1443 RT5682_STO1_ADC1R_SRC_SFT, rt5682_sto1_adc1_src);
1444
1445 static const struct snd_kcontrol_new rt5682_sto1_adc1r_mux =
1446 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5682_sto1_adc1r_enum);
1447
1448 /* STO1 ADC Source */
1449 /* MX-26 [11:10] [3:2] */
1450 static const char * const rt5682_sto1_adc_src[] = {
1451 "ADC1 L", "ADC1 R"
1452 };
1453
1454 static SOC_ENUM_SINGLE_DECL(
1455 rt5682_sto1_adcl_enum, RT5682_STO1_ADC_MIXER,
1456 RT5682_STO1_ADCL_SRC_SFT, rt5682_sto1_adc_src);
1457
1458 static const struct snd_kcontrol_new rt5682_sto1_adcl_mux =
1459 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5682_sto1_adcl_enum);
1460
1461 static SOC_ENUM_SINGLE_DECL(
1462 rt5682_sto1_adcr_enum, RT5682_STO1_ADC_MIXER,
1463 RT5682_STO1_ADCR_SRC_SFT, rt5682_sto1_adc_src);
1464
1465 static const struct snd_kcontrol_new rt5682_sto1_adcr_mux =
1466 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5682_sto1_adcr_enum);
1467
1468 /* STO1 ADC2 Source */
1469 /* MX-26 [12] [4] */
1470 static const char * const rt5682_sto1_adc2_src[] = {
1471 "DAC MIX", "DMIC"
1472 };
1473
1474 static SOC_ENUM_SINGLE_DECL(
1475 rt5682_sto1_adc2l_enum, RT5682_STO1_ADC_MIXER,
1476 RT5682_STO1_ADC2L_SRC_SFT, rt5682_sto1_adc2_src);
1477
1478 static const struct snd_kcontrol_new rt5682_sto1_adc2l_mux =
1479 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5682_sto1_adc2l_enum);
1480
1481 static SOC_ENUM_SINGLE_DECL(
1482 rt5682_sto1_adc2r_enum, RT5682_STO1_ADC_MIXER,
1483 RT5682_STO1_ADC2R_SRC_SFT, rt5682_sto1_adc2_src);
1484
1485 static const struct snd_kcontrol_new rt5682_sto1_adc2r_mux =
1486 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5682_sto1_adc2r_enum);
1487
1488 /* MX-79 [6:4] I2S1 ADC data location */
1489 static const unsigned int rt5682_if1_adc_slot_values[] = {
1490 0,
1491 2,
1492 4,
1493 6,
1494 };
1495
1496 static const char * const rt5682_if1_adc_slot_src[] = {
1497 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1498 };
1499
1500 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_if1_adc_slot_enum,
1501 RT5682_TDM_CTRL, RT5682_TDM_ADC_LCA_SFT, RT5682_TDM_ADC_LCA_MASK,
1502 rt5682_if1_adc_slot_src, rt5682_if1_adc_slot_values);
1503
1504 static const struct snd_kcontrol_new rt5682_if1_adc_slot_mux =
1505 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5682_if1_adc_slot_enum);
1506
1507 /* Analog DAC L1 Source, Analog DAC R1 Source*/
1508 /* MX-2B [4], MX-2B [0]*/
1509 static const char * const rt5682_alg_dac1_src[] = {
1510 "Stereo1 DAC Mixer", "DAC1"
1511 };
1512
1513 static SOC_ENUM_SINGLE_DECL(
1514 rt5682_alg_dac_l1_enum, RT5682_A_DAC1_MUX,
1515 RT5682_A_DACL1_SFT, rt5682_alg_dac1_src);
1516
1517 static const struct snd_kcontrol_new rt5682_alg_dac_l1_mux =
1518 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5682_alg_dac_l1_enum);
1519
1520 static SOC_ENUM_SINGLE_DECL(
1521 rt5682_alg_dac_r1_enum, RT5682_A_DAC1_MUX,
1522 RT5682_A_DACR1_SFT, rt5682_alg_dac1_src);
1523
1524 static const struct snd_kcontrol_new rt5682_alg_dac_r1_mux =
1525 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5682_alg_dac_r1_enum);
1526
1527 /* Out Switch */
1528 static const struct snd_kcontrol_new hpol_switch =
1529 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1530 RT5682_L_MUTE_SFT, 1, 1);
1531 static const struct snd_kcontrol_new hpor_switch =
1532 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5682_HP_CTRL_1,
1533 RT5682_R_MUTE_SFT, 1, 1);
1534
rt5682_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1535 static int rt5682_hp_event(struct snd_soc_dapm_widget *w,
1536 struct snd_kcontrol *kcontrol, int event)
1537 {
1538 struct snd_soc_component *component =
1539 snd_soc_dapm_to_component(w->dapm);
1540
1541 switch (event) {
1542 case SND_SOC_DAPM_PRE_PMU:
1543 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1544 RT5682_HP_C2_DAC_AMP_MUTE, 0);
1545 snd_soc_component_update_bits(component, RT5682_HP_LOGIC_CTRL_2,
1546 RT5682_HP_LC2_SIG_SOUR2_MASK, RT5682_HP_LC2_SIG_SOUR2_REG);
1547 snd_soc_component_update_bits(component,
1548 RT5682_DEPOP_1, 0x60, 0x60);
1549 snd_soc_component_update_bits(component,
1550 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0080);
1551 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1552 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN,
1553 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN);
1554 usleep_range(5000, 10000);
1555 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1556 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_L);
1557 break;
1558
1559 case SND_SOC_DAPM_POST_PMD:
1560 snd_soc_component_update_bits(component, RT5682_HP_CTRL_2,
1561 RT5682_HP_C2_DAC_L_EN | RT5682_HP_C2_DAC_R_EN, 0);
1562 snd_soc_component_update_bits(component, RT5682_CHARGE_PUMP_1,
1563 RT5682_CP_SW_SIZE_MASK, RT5682_CP_SW_SIZE_M);
1564 snd_soc_component_update_bits(component,
1565 RT5682_DEPOP_1, 0x60, 0x0);
1566 snd_soc_component_update_bits(component,
1567 RT5682_DAC_ADC_DIG_VOL1, 0x00c0, 0x0000);
1568 break;
1569 }
1570
1571 return 0;
1572 }
1573
set_dmic_power(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1574 static int set_dmic_power(struct snd_soc_dapm_widget *w,
1575 struct snd_kcontrol *kcontrol, int event)
1576 {
1577 struct snd_soc_component *component =
1578 snd_soc_dapm_to_component(w->dapm);
1579 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
1580 unsigned int delay = 50, val;
1581
1582 if (rt5682->pdata.dmic_delay)
1583 delay = rt5682->pdata.dmic_delay;
1584
1585 switch (event) {
1586 case SND_SOC_DAPM_POST_PMU:
1587 val = snd_soc_component_read(component, RT5682_GLB_CLK);
1588 val &= RT5682_SCLK_SRC_MASK;
1589 if (val == RT5682_SCLK_SRC_PLL1 || val == RT5682_SCLK_SRC_PLL2)
1590 snd_soc_component_update_bits(component,
1591 RT5682_PWR_ANLG_1,
1592 RT5682_PWR_VREF2 | RT5682_PWR_MB,
1593 RT5682_PWR_VREF2 | RT5682_PWR_MB);
1594
1595 /*Add delay to avoid pop noise*/
1596 msleep(delay);
1597 break;
1598
1599 case SND_SOC_DAPM_POST_PMD:
1600 if (!rt5682->jack_type) {
1601 if (!snd_soc_dapm_get_pin_status(w->dapm, "MICBIAS"))
1602 snd_soc_component_update_bits(component,
1603 RT5682_PWR_ANLG_1, RT5682_PWR_MB, 0);
1604 if (!snd_soc_dapm_get_pin_status(w->dapm, "Vref2"))
1605 snd_soc_component_update_bits(component,
1606 RT5682_PWR_ANLG_1, RT5682_PWR_VREF2, 0);
1607 }
1608 break;
1609 }
1610
1611 return 0;
1612 }
1613
rt5682_set_verf(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1614 static int rt5682_set_verf(struct snd_soc_dapm_widget *w,
1615 struct snd_kcontrol *kcontrol, int event)
1616 {
1617 struct snd_soc_component *component =
1618 snd_soc_dapm_to_component(w->dapm);
1619
1620 switch (event) {
1621 case SND_SOC_DAPM_PRE_PMU:
1622 switch (w->shift) {
1623 case RT5682_PWR_VREF1_BIT:
1624 snd_soc_component_update_bits(component,
1625 RT5682_PWR_ANLG_1, RT5682_PWR_FV1, 0);
1626 break;
1627
1628 case RT5682_PWR_VREF2_BIT:
1629 snd_soc_component_update_bits(component,
1630 RT5682_PWR_ANLG_1, RT5682_PWR_FV2, 0);
1631 break;
1632 }
1633 break;
1634
1635 case SND_SOC_DAPM_POST_PMU:
1636 usleep_range(15000, 20000);
1637 switch (w->shift) {
1638 case RT5682_PWR_VREF1_BIT:
1639 snd_soc_component_update_bits(component,
1640 RT5682_PWR_ANLG_1, RT5682_PWR_FV1,
1641 RT5682_PWR_FV1);
1642 break;
1643
1644 case RT5682_PWR_VREF2_BIT:
1645 snd_soc_component_update_bits(component,
1646 RT5682_PWR_ANLG_1, RT5682_PWR_FV2,
1647 RT5682_PWR_FV2);
1648 break;
1649 }
1650 break;
1651 }
1652
1653 return 0;
1654 }
1655
1656 static const unsigned int rt5682_adcdat_pin_values[] = {
1657 1,
1658 3,
1659 };
1660
1661 static const char * const rt5682_adcdat_pin_select[] = {
1662 "ADCDAT1",
1663 "ADCDAT2",
1664 };
1665
1666 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_adcdat_pin_enum,
1667 RT5682_GPIO_CTRL_1, RT5682_GP4_PIN_SFT, RT5682_GP4_PIN_MASK,
1668 rt5682_adcdat_pin_select, rt5682_adcdat_pin_values);
1669
1670 static const struct snd_kcontrol_new rt5682_adcdat_pin_ctrl =
1671 SOC_DAPM_ENUM("ADCDAT", rt5682_adcdat_pin_enum);
1672
1673 static const unsigned int rt5682_hpo_sig_out_values[] = {
1674 2,
1675 7,
1676 };
1677
1678 static const char * const rt5682_hpo_sig_out_mode[] = {
1679 "Legacy",
1680 "OneBit",
1681 };
1682
1683 static SOC_VALUE_ENUM_SINGLE_DECL(rt5682_hpo_sig_out_enum,
1684 RT5682_HP_LOGIC_CTRL_2, 0, RT5682_HP_LC2_SIG_SOUR1_MASK,
1685 rt5682_hpo_sig_out_mode, rt5682_hpo_sig_out_values);
1686
1687 static const struct snd_kcontrol_new rt5682_hpo_sig_demux =
1688 SOC_DAPM_ENUM("HPO Signal Demux", rt5682_hpo_sig_out_enum);
1689
1690 static const struct snd_soc_dapm_widget rt5682_dapm_widgets[] = {
1691 SND_SOC_DAPM_SUPPLY("LDO2", RT5682_PWR_ANLG_3, RT5682_PWR_LDO2_BIT,
1692 0, NULL, 0),
1693 SND_SOC_DAPM_SUPPLY("PLL1", RT5682_PWR_ANLG_3, RT5682_PWR_PLL_BIT,
1694 0, NULL, 0),
1695 SND_SOC_DAPM_SUPPLY("PLL2B", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2B_BIT,
1696 0, NULL, 0),
1697 SND_SOC_DAPM_SUPPLY("PLL2F", RT5682_PWR_ANLG_3, RT5682_PWR_PLL2F_BIT,
1698 0, set_filter_clk, SND_SOC_DAPM_PRE_PMU),
1699 SND_SOC_DAPM_SUPPLY("Vref1", RT5682_PWR_ANLG_1, RT5682_PWR_VREF1_BIT, 0,
1700 rt5682_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1701 SND_SOC_DAPM_SUPPLY("Vref2", SND_SOC_NOPM, 0, 0, NULL, 0),
1702 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, NULL, 0),
1703
1704 /* ASRC */
1705 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1706 RT5682_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1707 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5682_PLL_TRACK_1,
1708 RT5682_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1709 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5682_PLL_TRACK_1,
1710 RT5682_AD_ASRC_SFT, 0, NULL, 0),
1711 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5682_PLL_TRACK_1,
1712 RT5682_DA_ASRC_SFT, 0, NULL, 0),
1713 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5682_PLL_TRACK_1,
1714 RT5682_DMIC_ASRC_SFT, 0, NULL, 0),
1715
1716 /* Input Side */
1717 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5682_PWR_ANLG_2, RT5682_PWR_MB1_BIT,
1718 0, NULL, 0),
1719 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5682_PWR_ANLG_2, RT5682_PWR_MB2_BIT,
1720 0, NULL, 0),
1721
1722 /* Input Lines */
1723 SND_SOC_DAPM_INPUT("DMIC L1"),
1724 SND_SOC_DAPM_INPUT("DMIC R1"),
1725
1726 SND_SOC_DAPM_INPUT("IN1P"),
1727
1728 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1729 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1730 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5682_DMIC_CTRL_1,
1731 RT5682_DMIC_1_EN_SFT, 0, set_dmic_power,
1732 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1733
1734 /* Boost */
1735 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1736 0, 0, NULL, 0),
1737
1738 /* REC Mixer */
1739 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5682_rec1_l_mix,
1740 ARRAY_SIZE(rt5682_rec1_l_mix)),
1741 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5682_PWR_ANLG_2,
1742 RT5682_PWR_RM1_L_BIT, 0, NULL, 0),
1743
1744 /* ADCs */
1745 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1746 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1747
1748 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5682_PWR_DIG_1,
1749 RT5682_PWR_ADC_L1_BIT, 0, NULL, 0),
1750 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5682_PWR_DIG_1,
1751 RT5682_PWR_ADC_R1_BIT, 0, NULL, 0),
1752 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5682_CHOP_ADC,
1753 RT5682_CKGEN_ADC1_SFT, 0, NULL, 0),
1754
1755 /* ADC Mux */
1756 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1757 &rt5682_sto1_adc1l_mux),
1758 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1759 &rt5682_sto1_adc1r_mux),
1760 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1761 &rt5682_sto1_adc2l_mux),
1762 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1763 &rt5682_sto1_adc2r_mux),
1764 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1765 &rt5682_sto1_adcl_mux),
1766 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1767 &rt5682_sto1_adcr_mux),
1768 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1769 &rt5682_if1_adc_slot_mux),
1770
1771 /* ADC Mixer */
1772 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5682_PWR_DIG_2,
1773 RT5682_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1774 SND_SOC_DAPM_PRE_PMU),
1775 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5682_STO1_ADC_DIG_VOL,
1776 RT5682_L_MUTE_SFT, 1, rt5682_sto1_adc_l_mix,
1777 ARRAY_SIZE(rt5682_sto1_adc_l_mix)),
1778 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5682_STO1_ADC_DIG_VOL,
1779 RT5682_R_MUTE_SFT, 1, rt5682_sto1_adc_r_mix,
1780 ARRAY_SIZE(rt5682_sto1_adc_r_mix)),
1781
1782 /* ADC PGA */
1783 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1784
1785 /* Digital Interface */
1786 SND_SOC_DAPM_SUPPLY("I2S1", RT5682_PWR_DIG_1, RT5682_PWR_I2S1_BIT,
1787 0, NULL, 0),
1788 SND_SOC_DAPM_SUPPLY("I2S2", RT5682_PWR_DIG_1, RT5682_PWR_I2S2_BIT,
1789 0, NULL, 0),
1790 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1791 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1792 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1793 SND_SOC_DAPM_PGA("SOUND DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1794 SND_SOC_DAPM_PGA("SOUND DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1795
1796 /* Digital Interface Select */
1797 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1798 &rt5682_if1_01_adc_swap_mux),
1799 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1800 &rt5682_if1_23_adc_swap_mux),
1801 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1802 &rt5682_if1_45_adc_swap_mux),
1803 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1804 &rt5682_if1_67_adc_swap_mux),
1805 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1806 &rt5682_if2_adc_swap_mux),
1807
1808 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1809 &rt5682_adcdat_pin_ctrl),
1810
1811 SND_SOC_DAPM_MUX("DAC L Mux", SND_SOC_NOPM, 0, 0,
1812 &rt5682_dac_l_mux),
1813 SND_SOC_DAPM_MUX("DAC R Mux", SND_SOC_NOPM, 0, 0,
1814 &rt5682_dac_r_mux),
1815
1816 /* Audio Interface */
1817 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1818 RT5682_I2S1_SDP, RT5682_SEL_ADCDAT_SFT, 1),
1819 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1820 RT5682_I2S2_SDP, RT5682_I2S2_PIN_CFG_SFT, 1),
1821 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1822 SND_SOC_DAPM_AIF_IN("SDWRX", "SDW Playback", 0, SND_SOC_NOPM, 0, 0),
1823 SND_SOC_DAPM_AIF_OUT("SDWTX", "SDW Capture", 0, SND_SOC_NOPM, 0, 0),
1824
1825 /* Output Side */
1826 /* DAC mixer before sound effect */
1827 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1828 rt5682_dac_l_mix, ARRAY_SIZE(rt5682_dac_l_mix)),
1829 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1830 rt5682_dac_r_mix, ARRAY_SIZE(rt5682_dac_r_mix)),
1831
1832 /* DAC channel Mux */
1833 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1834 &rt5682_alg_dac_l1_mux),
1835 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1836 &rt5682_alg_dac_r1_mux),
1837
1838 /* DAC Mixer */
1839 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5682_PWR_DIG_2,
1840 RT5682_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1841 SND_SOC_DAPM_PRE_PMU),
1842 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1843 rt5682_sto1_dac_l_mix, ARRAY_SIZE(rt5682_sto1_dac_l_mix)),
1844 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1845 rt5682_sto1_dac_r_mix, ARRAY_SIZE(rt5682_sto1_dac_r_mix)),
1846
1847 /* DACs */
1848 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5682_PWR_DIG_1,
1849 RT5682_PWR_DAC_L1_BIT, 0),
1850 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5682_PWR_DIG_1,
1851 RT5682_PWR_DAC_R1_BIT, 0),
1852 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5682_CHOP_DAC,
1853 RT5682_CKGEN_DAC1_SFT, 0, NULL, 0),
1854
1855 /* HPO */
1856 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5682_hp_event,
1857 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1858
1859 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5682_PWR_ANLG_1,
1860 RT5682_PWR_HA_L_BIT, 0, NULL, 0),
1861 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5682_PWR_ANLG_1,
1862 RT5682_PWR_HA_R_BIT, 0, NULL, 0),
1863 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5682_DEPOP_1,
1864 RT5682_PUMP_EN_SFT, 0, NULL, 0),
1865 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5682_DEPOP_1,
1866 RT5682_CAPLESS_EN_SFT, 0, NULL, 0),
1867
1868 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1869 &hpol_switch),
1870 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1871 &hpor_switch),
1872
1873 SND_SOC_DAPM_OUT_DRV("HPO Legacy", SND_SOC_NOPM, 0, 0, NULL, 0),
1874 SND_SOC_DAPM_OUT_DRV("HPO OneBit", SND_SOC_NOPM, 0, 0, NULL, 0),
1875 SND_SOC_DAPM_DEMUX("HPO Signal Demux", SND_SOC_NOPM, 0, 0, &rt5682_hpo_sig_demux),
1876
1877 /* CLK DET */
1878 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5682_CLK_DET,
1879 RT5682_SYS_CLK_DET_SFT, 0, NULL, 0),
1880 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5682_CLK_DET,
1881 RT5682_PLL1_CLK_DET_SFT, 0, NULL, 0),
1882 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5682_CLK_DET,
1883 RT5682_PLL2_CLK_DET_SFT, 0, NULL, 0),
1884 SND_SOC_DAPM_SUPPLY("CLKDET", RT5682_CLK_DET,
1885 RT5682_POW_CLK_DET_SFT, 0, NULL, 0),
1886
1887 /* Output Lines */
1888 SND_SOC_DAPM_OUTPUT("HPOL"),
1889 SND_SOC_DAPM_OUTPUT("HPOR"),
1890 };
1891
1892 static const struct snd_soc_dapm_route rt5682_dapm_routes[] = {
1893 /*PLL*/
1894 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1895 {"ADC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1896 {"ADC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1897 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1898 {"DAC Stereo1 Filter", NULL, "PLL2B", is_sys_clk_from_pll2},
1899 {"DAC Stereo1 Filter", NULL, "PLL2F", is_sys_clk_from_pll2},
1900
1901 /*ASRC*/
1902 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1903 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1904 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1905 {"ADC STO1 ASRC", NULL, "DA ASRC"},
1906 {"ADC STO1 ASRC", NULL, "CLKDET"},
1907 {"DAC STO1 ASRC", NULL, "AD ASRC"},
1908 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1909 {"DAC STO1 ASRC", NULL, "CLKDET"},
1910
1911 /*Vref*/
1912 {"MICBIAS1", NULL, "Vref1"},
1913 {"MICBIAS2", NULL, "Vref1"},
1914
1915 {"CLKDET SYS", NULL, "CLKDET"},
1916
1917 {"BST1 CBJ", NULL, "IN1P"},
1918
1919 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1920 {"RECMIX1L", NULL, "RECMIX1L Power"},
1921
1922 {"ADC1 L", NULL, "RECMIX1L"},
1923 {"ADC1 L", NULL, "ADC1 L Power"},
1924 {"ADC1 L", NULL, "ADC1 clock"},
1925
1926 {"DMIC L1", NULL, "DMIC CLK"},
1927 {"DMIC L1", NULL, "DMIC1 Power"},
1928 {"DMIC R1", NULL, "DMIC CLK"},
1929 {"DMIC R1", NULL, "DMIC1 Power"},
1930 {"DMIC CLK", NULL, "DMIC ASRC"},
1931
1932 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1933 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1934 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1935 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1936
1937 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1938 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1939 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1940 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1941
1942 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1943 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1944 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1945 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1946
1947 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1948 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1949 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1950
1951 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1952 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1953 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1954
1955 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1956 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1957
1958 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1959 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1960 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1961 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1962 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1963 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1964 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1965 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1966 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1967 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1968 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1969 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1970 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1971 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1972 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1973 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1974
1975 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1976 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1977 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1978 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1979 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1980 {"AIF1TX", NULL, "I2S1"},
1981 {"AIF1TX", NULL, "ADCDAT Mux"},
1982 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1983 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1984 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1985 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1986 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1987 {"AIF2TX", NULL, "ADCDAT Mux"},
1988
1989 {"SDWTX", NULL, "PLL2B"},
1990 {"SDWTX", NULL, "PLL2F"},
1991 {"SDWTX", NULL, "ADCDAT Mux"},
1992
1993 {"IF1 DAC1 L", NULL, "AIF1RX"},
1994 {"IF1 DAC1 L", NULL, "I2S1"},
1995 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1996 {"IF1 DAC1 R", NULL, "AIF1RX"},
1997 {"IF1 DAC1 R", NULL, "I2S1"},
1998 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1999
2000 {"SOUND DAC L", NULL, "SDWRX"},
2001 {"SOUND DAC L", NULL, "DAC Stereo1 Filter"},
2002 {"SOUND DAC L", NULL, "PLL2B"},
2003 {"SOUND DAC L", NULL, "PLL2F"},
2004 {"SOUND DAC R", NULL, "SDWRX"},
2005 {"SOUND DAC R", NULL, "DAC Stereo1 Filter"},
2006 {"SOUND DAC R", NULL, "PLL2B"},
2007 {"SOUND DAC R", NULL, "PLL2F"},
2008
2009 {"DAC L Mux", "IF1", "IF1 DAC1 L"},
2010 {"DAC L Mux", "SOUND", "SOUND DAC L"},
2011 {"DAC R Mux", "IF1", "IF1 DAC1 R"},
2012 {"DAC R Mux", "SOUND", "SOUND DAC R"},
2013
2014 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
2015 {"DAC1 MIXL", "DAC1 Switch", "DAC L Mux"},
2016 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
2017 {"DAC1 MIXR", "DAC1 Switch", "DAC R Mux"},
2018
2019 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
2020 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
2021
2022 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
2023 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
2024
2025 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
2026 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
2027 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
2028 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
2029
2030 {"DAC L1", NULL, "DAC L1 Source"},
2031 {"DAC R1", NULL, "DAC R1 Source"},
2032
2033 {"DAC L1", NULL, "DAC 1 Clock"},
2034 {"DAC R1", NULL, "DAC 1 Clock"},
2035
2036 {"HP Amp", NULL, "DAC L1"},
2037 {"HP Amp", NULL, "DAC R1"},
2038 {"HP Amp", NULL, "HP Amp L"},
2039 {"HP Amp", NULL, "HP Amp R"},
2040 {"HP Amp", NULL, "Capless"},
2041 {"HP Amp", NULL, "Charge Pump"},
2042 {"HP Amp", NULL, "CLKDET SYS"},
2043 {"HP Amp", NULL, "Vref1"},
2044
2045 {"HPO Signal Demux", NULL, "HP Amp"},
2046
2047 {"HPO Legacy", "Legacy", "HPO Signal Demux"},
2048 {"HPO OneBit", "OneBit", "HPO Signal Demux"},
2049
2050 {"HPOL Playback", "Switch", "HPO Legacy"},
2051 {"HPOR Playback", "Switch", "HPO Legacy"},
2052
2053 {"HPOL", NULL, "HPOL Playback"},
2054 {"HPOR", NULL, "HPOR Playback"},
2055 {"HPOL", NULL, "HPO OneBit"},
2056 {"HPOR", NULL, "HPO OneBit"},
2057 };
2058
rt5682_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2059 static int rt5682_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2060 unsigned int rx_mask, int slots, int slot_width)
2061 {
2062 struct snd_soc_component *component = dai->component;
2063 unsigned int cl, val = 0;
2064
2065 if (tx_mask || rx_mask)
2066 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2067 RT5682_TDM_EN, RT5682_TDM_EN);
2068 else
2069 snd_soc_component_update_bits(component, RT5682_TDM_ADDA_CTRL_2,
2070 RT5682_TDM_EN, 0);
2071
2072 switch (slots) {
2073 case 4:
2074 val |= RT5682_TDM_TX_CH_4;
2075 val |= RT5682_TDM_RX_CH_4;
2076 break;
2077 case 6:
2078 val |= RT5682_TDM_TX_CH_6;
2079 val |= RT5682_TDM_RX_CH_6;
2080 break;
2081 case 8:
2082 val |= RT5682_TDM_TX_CH_8;
2083 val |= RT5682_TDM_RX_CH_8;
2084 break;
2085 case 2:
2086 break;
2087 default:
2088 return -EINVAL;
2089 }
2090
2091 snd_soc_component_update_bits(component, RT5682_TDM_CTRL,
2092 RT5682_TDM_TX_CH_MASK | RT5682_TDM_RX_CH_MASK, val);
2093
2094 switch (slot_width) {
2095 case 8:
2096 if (tx_mask || rx_mask)
2097 return -EINVAL;
2098 cl = RT5682_I2S1_TX_CHL_8 | RT5682_I2S1_RX_CHL_8;
2099 break;
2100 case 16:
2101 val = RT5682_TDM_CL_16;
2102 cl = RT5682_I2S1_TX_CHL_16 | RT5682_I2S1_RX_CHL_16;
2103 break;
2104 case 20:
2105 val = RT5682_TDM_CL_20;
2106 cl = RT5682_I2S1_TX_CHL_20 | RT5682_I2S1_RX_CHL_20;
2107 break;
2108 case 24:
2109 val = RT5682_TDM_CL_24;
2110 cl = RT5682_I2S1_TX_CHL_24 | RT5682_I2S1_RX_CHL_24;
2111 break;
2112 case 32:
2113 val = RT5682_TDM_CL_32;
2114 cl = RT5682_I2S1_TX_CHL_32 | RT5682_I2S1_RX_CHL_32;
2115 break;
2116 default:
2117 return -EINVAL;
2118 }
2119
2120 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2121 RT5682_TDM_CL_MASK, val);
2122 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2123 RT5682_I2S1_TX_CHL_MASK | RT5682_I2S1_RX_CHL_MASK, cl);
2124
2125 return 0;
2126 }
2127
rt5682_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2128 static int rt5682_hw_params(struct snd_pcm_substream *substream,
2129 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2130 {
2131 struct snd_soc_component *component = dai->component;
2132 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2133 unsigned int len_1 = 0, len_2 = 0;
2134 int pre_div, frame_size;
2135
2136 rt5682->lrck[dai->id] = params_rate(params);
2137 pre_div = rl6231_get_clk_info(rt5682->sysclk, rt5682->lrck[dai->id]);
2138
2139 frame_size = snd_soc_params_to_frame_size(params);
2140 if (frame_size < 0) {
2141 dev_err(component->dev, "Unsupported frame size: %d\n",
2142 frame_size);
2143 return -EINVAL;
2144 }
2145
2146 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
2147 rt5682->lrck[dai->id], pre_div, dai->id);
2148
2149 switch (params_width(params)) {
2150 case 16:
2151 break;
2152 case 20:
2153 len_1 |= RT5682_I2S1_DL_20;
2154 len_2 |= RT5682_I2S2_DL_20;
2155 break;
2156 case 24:
2157 len_1 |= RT5682_I2S1_DL_24;
2158 len_2 |= RT5682_I2S2_DL_24;
2159 break;
2160 case 32:
2161 len_1 |= RT5682_I2S1_DL_32;
2162 len_2 |= RT5682_I2S2_DL_24;
2163 break;
2164 case 8:
2165 len_1 |= RT5682_I2S2_DL_8;
2166 len_2 |= RT5682_I2S2_DL_8;
2167 break;
2168 default:
2169 return -EINVAL;
2170 }
2171
2172 switch (dai->id) {
2173 case RT5682_AIF1:
2174 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2175 RT5682_I2S1_DL_MASK, len_1);
2176 if (rt5682->master[RT5682_AIF1]) {
2177 snd_soc_component_update_bits(component,
2178 RT5682_ADDA_CLK_1, RT5682_I2S_M_DIV_MASK |
2179 RT5682_I2S_CLK_SRC_MASK,
2180 pre_div << RT5682_I2S_M_DIV_SFT |
2181 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2182 }
2183 if (params_channels(params) == 1) /* mono mode */
2184 snd_soc_component_update_bits(component,
2185 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2186 RT5682_I2S1_MONO_EN);
2187 else
2188 snd_soc_component_update_bits(component,
2189 RT5682_I2S1_SDP, RT5682_I2S1_MONO_MASK,
2190 RT5682_I2S1_MONO_DIS);
2191 break;
2192 case RT5682_AIF2:
2193 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2194 RT5682_I2S2_DL_MASK, len_2);
2195 if (rt5682->master[RT5682_AIF2]) {
2196 snd_soc_component_update_bits(component,
2197 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_M_PD_MASK,
2198 pre_div << RT5682_I2S2_M_PD_SFT);
2199 }
2200 if (params_channels(params) == 1) /* mono mode */
2201 snd_soc_component_update_bits(component,
2202 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2203 RT5682_I2S2_MONO_EN);
2204 else
2205 snd_soc_component_update_bits(component,
2206 RT5682_I2S2_SDP, RT5682_I2S2_MONO_MASK,
2207 RT5682_I2S2_MONO_DIS);
2208 break;
2209 default:
2210 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2211 return -EINVAL;
2212 }
2213
2214 return 0;
2215 }
2216
rt5682_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2217 static int rt5682_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2218 {
2219 struct snd_soc_component *component = dai->component;
2220 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2221 unsigned int reg_val = 0, tdm_ctrl = 0;
2222
2223 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2224 case SND_SOC_DAIFMT_CBM_CFM:
2225 rt5682->master[dai->id] = 1;
2226 break;
2227 case SND_SOC_DAIFMT_CBS_CFS:
2228 rt5682->master[dai->id] = 0;
2229 break;
2230 default:
2231 return -EINVAL;
2232 }
2233
2234 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2235 case SND_SOC_DAIFMT_NB_NF:
2236 break;
2237 case SND_SOC_DAIFMT_IB_NF:
2238 reg_val |= RT5682_I2S_BP_INV;
2239 tdm_ctrl |= RT5682_TDM_S_BP_INV;
2240 break;
2241 case SND_SOC_DAIFMT_NB_IF:
2242 if (dai->id == RT5682_AIF1)
2243 tdm_ctrl |= RT5682_TDM_S_LP_INV | RT5682_TDM_M_BP_INV;
2244 else
2245 return -EINVAL;
2246 break;
2247 case SND_SOC_DAIFMT_IB_IF:
2248 if (dai->id == RT5682_AIF1)
2249 tdm_ctrl |= RT5682_TDM_S_BP_INV | RT5682_TDM_S_LP_INV |
2250 RT5682_TDM_M_BP_INV | RT5682_TDM_M_LP_INV;
2251 else
2252 return -EINVAL;
2253 break;
2254 default:
2255 return -EINVAL;
2256 }
2257
2258 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2259 case SND_SOC_DAIFMT_I2S:
2260 break;
2261 case SND_SOC_DAIFMT_LEFT_J:
2262 reg_val |= RT5682_I2S_DF_LEFT;
2263 tdm_ctrl |= RT5682_TDM_DF_LEFT;
2264 break;
2265 case SND_SOC_DAIFMT_DSP_A:
2266 reg_val |= RT5682_I2S_DF_PCM_A;
2267 tdm_ctrl |= RT5682_TDM_DF_PCM_A;
2268 break;
2269 case SND_SOC_DAIFMT_DSP_B:
2270 reg_val |= RT5682_I2S_DF_PCM_B;
2271 tdm_ctrl |= RT5682_TDM_DF_PCM_B;
2272 break;
2273 default:
2274 return -EINVAL;
2275 }
2276
2277 switch (dai->id) {
2278 case RT5682_AIF1:
2279 snd_soc_component_update_bits(component, RT5682_I2S1_SDP,
2280 RT5682_I2S_DF_MASK, reg_val);
2281 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2282 RT5682_TDM_MS_MASK | RT5682_TDM_S_BP_MASK |
2283 RT5682_TDM_DF_MASK | RT5682_TDM_M_BP_MASK |
2284 RT5682_TDM_M_LP_MASK | RT5682_TDM_S_LP_MASK,
2285 tdm_ctrl | rt5682->master[dai->id]);
2286 break;
2287 case RT5682_AIF2:
2288 if (rt5682->master[dai->id] == 0)
2289 reg_val |= RT5682_I2S2_MS_S;
2290 snd_soc_component_update_bits(component, RT5682_I2S2_SDP,
2291 RT5682_I2S2_MS_MASK | RT5682_I2S_BP_MASK |
2292 RT5682_I2S_DF_MASK, reg_val);
2293 break;
2294 default:
2295 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2296 return -EINVAL;
2297 }
2298 return 0;
2299 }
2300
rt5682_set_component_sysclk(struct snd_soc_component * component,int clk_id,int source,unsigned int freq,int dir)2301 static int rt5682_set_component_sysclk(struct snd_soc_component *component,
2302 int clk_id, int source, unsigned int freq, int dir)
2303 {
2304 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2305 unsigned int reg_val = 0, src = 0;
2306
2307 if (freq == rt5682->sysclk && clk_id == rt5682->sysclk_src)
2308 return 0;
2309
2310 switch (clk_id) {
2311 case RT5682_SCLK_S_MCLK:
2312 reg_val |= RT5682_SCLK_SRC_MCLK;
2313 src = RT5682_CLK_SRC_MCLK;
2314 break;
2315 case RT5682_SCLK_S_PLL1:
2316 reg_val |= RT5682_SCLK_SRC_PLL1;
2317 src = RT5682_CLK_SRC_PLL1;
2318 break;
2319 case RT5682_SCLK_S_PLL2:
2320 reg_val |= RT5682_SCLK_SRC_PLL2;
2321 src = RT5682_CLK_SRC_PLL2;
2322 break;
2323 case RT5682_SCLK_S_RCCLK:
2324 reg_val |= RT5682_SCLK_SRC_RCCLK;
2325 src = RT5682_CLK_SRC_RCCLK;
2326 break;
2327 default:
2328 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2329 return -EINVAL;
2330 }
2331 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2332 RT5682_SCLK_SRC_MASK, reg_val);
2333
2334 if (rt5682->master[RT5682_AIF2]) {
2335 snd_soc_component_update_bits(component,
2336 RT5682_I2S_M_CLK_CTRL_1, RT5682_I2S2_SRC_MASK,
2337 src << RT5682_I2S2_SRC_SFT);
2338 }
2339
2340 rt5682->sysclk = freq;
2341 rt5682->sysclk_src = clk_id;
2342
2343 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2344 freq, clk_id);
2345
2346 return 0;
2347 }
2348
rt5682_set_component_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2349 static int rt5682_set_component_pll(struct snd_soc_component *component,
2350 int pll_id, int source, unsigned int freq_in,
2351 unsigned int freq_out)
2352 {
2353 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2354 struct rl6231_pll_code pll_code, pll2f_code, pll2b_code;
2355 unsigned int pll2_fout1, pll2_ps_val;
2356 int ret;
2357
2358 if (source == rt5682->pll_src[pll_id] &&
2359 freq_in == rt5682->pll_in[pll_id] &&
2360 freq_out == rt5682->pll_out[pll_id])
2361 return 0;
2362
2363 if (!freq_in || !freq_out) {
2364 dev_dbg(component->dev, "PLL disabled\n");
2365
2366 rt5682->pll_in[pll_id] = 0;
2367 rt5682->pll_out[pll_id] = 0;
2368 snd_soc_component_update_bits(component, RT5682_GLB_CLK,
2369 RT5682_SCLK_SRC_MASK, RT5682_SCLK_SRC_MCLK);
2370 return 0;
2371 }
2372
2373 if (pll_id == RT5682_PLL2) {
2374 switch (source) {
2375 case RT5682_PLL2_S_MCLK:
2376 snd_soc_component_update_bits(component,
2377 RT5682_GLB_CLK, RT5682_PLL2_SRC_MASK,
2378 RT5682_PLL2_SRC_MCLK);
2379 break;
2380 default:
2381 dev_err(component->dev, "Unknown PLL2 Source %d\n",
2382 source);
2383 return -EINVAL;
2384 }
2385
2386 /**
2387 * PLL2 concatenates 2 PLL units.
2388 * We suggest the Fout of the front PLL is 3.84MHz.
2389 */
2390 pll2_fout1 = 3840000;
2391 ret = rl6231_pll_calc(freq_in, pll2_fout1, &pll2f_code);
2392 if (ret < 0) {
2393 dev_err(component->dev, "Unsupported input clock %d\n",
2394 freq_in);
2395 return ret;
2396 }
2397 dev_dbg(component->dev, "PLL2F: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2398 freq_in, pll2_fout1,
2399 pll2f_code.m_bp,
2400 (pll2f_code.m_bp ? 0 : pll2f_code.m_code),
2401 pll2f_code.n_code, pll2f_code.k_code);
2402
2403 ret = rl6231_pll_calc(pll2_fout1, freq_out, &pll2b_code);
2404 if (ret < 0) {
2405 dev_err(component->dev, "Unsupported input clock %d\n",
2406 pll2_fout1);
2407 return ret;
2408 }
2409 dev_dbg(component->dev, "PLL2B: fin=%d fout=%d bypass=%d m=%d n=%d k=%d\n",
2410 pll2_fout1, freq_out,
2411 pll2b_code.m_bp,
2412 (pll2b_code.m_bp ? 0 : pll2b_code.m_code),
2413 pll2b_code.n_code, pll2b_code.k_code);
2414
2415 snd_soc_component_write(component, RT5682_PLL2_CTRL_1,
2416 pll2f_code.k_code << RT5682_PLL2F_K_SFT |
2417 pll2b_code.k_code << RT5682_PLL2B_K_SFT |
2418 pll2b_code.m_code);
2419 snd_soc_component_write(component, RT5682_PLL2_CTRL_2,
2420 pll2f_code.m_code << RT5682_PLL2F_M_SFT |
2421 pll2b_code.n_code);
2422 snd_soc_component_write(component, RT5682_PLL2_CTRL_3,
2423 pll2f_code.n_code << RT5682_PLL2F_N_SFT);
2424
2425 if (freq_out == 22579200)
2426 pll2_ps_val = 1 << RT5682_PLL2B_SEL_PS_SFT;
2427 else
2428 pll2_ps_val = 1 << RT5682_PLL2B_PS_BYP_SFT;
2429 snd_soc_component_update_bits(component, RT5682_PLL2_CTRL_4,
2430 RT5682_PLL2B_SEL_PS_MASK | RT5682_PLL2B_PS_BYP_MASK |
2431 RT5682_PLL2B_M_BP_MASK | RT5682_PLL2F_M_BP_MASK | 0xf,
2432 pll2_ps_val |
2433 (pll2b_code.m_bp ? 1 : 0) << RT5682_PLL2B_M_BP_SFT |
2434 (pll2f_code.m_bp ? 1 : 0) << RT5682_PLL2F_M_BP_SFT |
2435 0xf);
2436 } else {
2437 switch (source) {
2438 case RT5682_PLL1_S_MCLK:
2439 snd_soc_component_update_bits(component,
2440 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2441 RT5682_PLL1_SRC_MCLK);
2442 break;
2443 case RT5682_PLL1_S_BCLK1:
2444 snd_soc_component_update_bits(component,
2445 RT5682_GLB_CLK, RT5682_PLL1_SRC_MASK,
2446 RT5682_PLL1_SRC_BCLK1);
2447 break;
2448 default:
2449 dev_err(component->dev, "Unknown PLL1 Source %d\n",
2450 source);
2451 return -EINVAL;
2452 }
2453
2454 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2455 if (ret < 0) {
2456 dev_err(component->dev, "Unsupported input clock %d\n",
2457 freq_in);
2458 return ret;
2459 }
2460
2461 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2462 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2463 pll_code.n_code, pll_code.k_code);
2464
2465 snd_soc_component_write(component, RT5682_PLL_CTRL_1,
2466 (pll_code.n_code << RT5682_PLL_N_SFT) | pll_code.k_code);
2467 snd_soc_component_write(component, RT5682_PLL_CTRL_2,
2468 ((pll_code.m_bp ? 0 : pll_code.m_code) << RT5682_PLL_M_SFT) |
2469 ((pll_code.m_bp << RT5682_PLL_M_BP_SFT) | RT5682_PLL_RST));
2470 }
2471
2472 rt5682->pll_in[pll_id] = freq_in;
2473 rt5682->pll_out[pll_id] = freq_out;
2474 rt5682->pll_src[pll_id] = source;
2475
2476 return 0;
2477 }
2478
rt5682_set_bclk1_ratio(struct snd_soc_dai * dai,unsigned int ratio)2479 static int rt5682_set_bclk1_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2480 {
2481 struct snd_soc_component *component = dai->component;
2482 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2483
2484 rt5682->bclk[dai->id] = ratio;
2485
2486 switch (ratio) {
2487 case 256:
2488 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2489 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_256);
2490 break;
2491 case 128:
2492 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2493 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_128);
2494 break;
2495 case 64:
2496 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2497 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_64);
2498 break;
2499 case 32:
2500 snd_soc_component_update_bits(component, RT5682_TDM_TCON_CTRL,
2501 RT5682_TDM_BCLK_MS1_MASK, RT5682_TDM_BCLK_MS1_32);
2502 break;
2503 default:
2504 dev_err(dai->dev, "Invalid bclk1 ratio %d\n", ratio);
2505 return -EINVAL;
2506 }
2507
2508 return 0;
2509 }
2510
rt5682_set_bclk2_ratio(struct snd_soc_dai * dai,unsigned int ratio)2511 static int rt5682_set_bclk2_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2512 {
2513 struct snd_soc_component *component = dai->component;
2514 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2515
2516 rt5682->bclk[dai->id] = ratio;
2517
2518 switch (ratio) {
2519 case 64:
2520 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2521 RT5682_I2S2_BCLK_MS2_MASK,
2522 RT5682_I2S2_BCLK_MS2_64);
2523 break;
2524 case 32:
2525 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_2,
2526 RT5682_I2S2_BCLK_MS2_MASK,
2527 RT5682_I2S2_BCLK_MS2_32);
2528 break;
2529 default:
2530 dev_err(dai->dev, "Invalid bclk2 ratio %d\n", ratio);
2531 return -EINVAL;
2532 }
2533
2534 return 0;
2535 }
2536
rt5682_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)2537 static int rt5682_set_bias_level(struct snd_soc_component *component,
2538 enum snd_soc_bias_level level)
2539 {
2540 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2541
2542 switch (level) {
2543 case SND_SOC_BIAS_PREPARE:
2544 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2545 RT5682_PWR_BG, RT5682_PWR_BG);
2546 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2547 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO,
2548 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO);
2549 break;
2550
2551 case SND_SOC_BIAS_STANDBY:
2552 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2553 RT5682_DIG_GATE_CTRL, RT5682_DIG_GATE_CTRL);
2554 break;
2555 case SND_SOC_BIAS_OFF:
2556 regmap_update_bits(rt5682->regmap, RT5682_PWR_DIG_1,
2557 RT5682_DIG_GATE_CTRL | RT5682_PWR_LDO, 0);
2558 regmap_update_bits(rt5682->regmap, RT5682_PWR_ANLG_1,
2559 RT5682_PWR_BG, 0);
2560 break;
2561 case SND_SOC_BIAS_ON:
2562 break;
2563 }
2564
2565 return 0;
2566 }
2567
2568 #ifdef CONFIG_COMMON_CLK
2569 #define CLK_PLL2_FIN 48000000
2570 #define CLK_48 48000
2571 #define CLK_44 44100
2572
rt5682_clk_check(struct rt5682_priv * rt5682)2573 static bool rt5682_clk_check(struct rt5682_priv *rt5682)
2574 {
2575 if (!rt5682->master[RT5682_AIF1]) {
2576 dev_dbg(rt5682->i2c_dev, "sysclk/dai not set correctly\n");
2577 return false;
2578 }
2579 return true;
2580 }
2581
rt5682_wclk_prepare(struct clk_hw * hw)2582 static int rt5682_wclk_prepare(struct clk_hw *hw)
2583 {
2584 struct rt5682_priv *rt5682 =
2585 container_of(hw, struct rt5682_priv,
2586 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2587 struct snd_soc_component *component;
2588 struct snd_soc_dapm_context *dapm;
2589
2590 if (!rt5682_clk_check(rt5682))
2591 return -EINVAL;
2592
2593 component = rt5682->component;
2594 dapm = snd_soc_component_get_dapm(component);
2595
2596 snd_soc_dapm_mutex_lock(dapm);
2597
2598 snd_soc_dapm_force_enable_pin_unlocked(dapm, "MICBIAS");
2599 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2600 RT5682_PWR_MB, RT5682_PWR_MB);
2601
2602 snd_soc_dapm_force_enable_pin_unlocked(dapm, "Vref2");
2603 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2604 RT5682_PWR_VREF2 | RT5682_PWR_FV2,
2605 RT5682_PWR_VREF2);
2606 usleep_range(55000, 60000);
2607 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2608 RT5682_PWR_FV2, RT5682_PWR_FV2);
2609
2610 snd_soc_dapm_force_enable_pin_unlocked(dapm, "I2S1");
2611 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2F");
2612 snd_soc_dapm_force_enable_pin_unlocked(dapm, "PLL2B");
2613 snd_soc_dapm_sync_unlocked(dapm);
2614
2615 snd_soc_dapm_mutex_unlock(dapm);
2616
2617 return 0;
2618 }
2619
rt5682_wclk_unprepare(struct clk_hw * hw)2620 static void rt5682_wclk_unprepare(struct clk_hw *hw)
2621 {
2622 struct rt5682_priv *rt5682 =
2623 container_of(hw, struct rt5682_priv,
2624 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2625 struct snd_soc_component *component;
2626 struct snd_soc_dapm_context *dapm;
2627
2628 if (!rt5682_clk_check(rt5682))
2629 return;
2630
2631 component = rt5682->component;
2632 dapm = snd_soc_component_get_dapm(component);
2633
2634 snd_soc_dapm_mutex_lock(dapm);
2635
2636 snd_soc_dapm_disable_pin_unlocked(dapm, "MICBIAS");
2637 snd_soc_dapm_disable_pin_unlocked(dapm, "Vref2");
2638 if (!rt5682->jack_type)
2639 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_1,
2640 RT5682_PWR_VREF2 | RT5682_PWR_FV2 |
2641 RT5682_PWR_MB, 0);
2642
2643 snd_soc_dapm_disable_pin_unlocked(dapm, "I2S1");
2644 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2F");
2645 snd_soc_dapm_disable_pin_unlocked(dapm, "PLL2B");
2646 snd_soc_dapm_sync_unlocked(dapm);
2647
2648 snd_soc_dapm_mutex_unlock(dapm);
2649 }
2650
rt5682_wclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2651 static unsigned long rt5682_wclk_recalc_rate(struct clk_hw *hw,
2652 unsigned long parent_rate)
2653 {
2654 struct rt5682_priv *rt5682 =
2655 container_of(hw, struct rt5682_priv,
2656 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2657 const char * const clk_name = clk_hw_get_name(hw);
2658
2659 if (!rt5682_clk_check(rt5682))
2660 return 0;
2661 /*
2662 * Only accept to set wclk rate to 44.1k or 48kHz.
2663 */
2664 if (rt5682->lrck[RT5682_AIF1] != CLK_48 &&
2665 rt5682->lrck[RT5682_AIF1] != CLK_44) {
2666 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2667 __func__, clk_name, CLK_44, CLK_48);
2668 return 0;
2669 }
2670
2671 return rt5682->lrck[RT5682_AIF1];
2672 }
2673
rt5682_wclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2674 static long rt5682_wclk_round_rate(struct clk_hw *hw, unsigned long rate,
2675 unsigned long *parent_rate)
2676 {
2677 struct rt5682_priv *rt5682 =
2678 container_of(hw, struct rt5682_priv,
2679 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2680 const char * const clk_name = clk_hw_get_name(hw);
2681
2682 if (!rt5682_clk_check(rt5682))
2683 return -EINVAL;
2684 /*
2685 * Only accept to set wclk rate to 44.1k or 48kHz.
2686 * It will force to 48kHz if not both.
2687 */
2688 if (rate != CLK_48 && rate != CLK_44) {
2689 dev_warn(rt5682->i2c_dev, "%s: clk %s only support %d or %d Hz output\n",
2690 __func__, clk_name, CLK_44, CLK_48);
2691 rate = CLK_48;
2692 }
2693
2694 return rate;
2695 }
2696
rt5682_wclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2697 static int rt5682_wclk_set_rate(struct clk_hw *hw, unsigned long rate,
2698 unsigned long parent_rate)
2699 {
2700 struct rt5682_priv *rt5682 =
2701 container_of(hw, struct rt5682_priv,
2702 dai_clks_hw[RT5682_DAI_WCLK_IDX]);
2703 struct snd_soc_component *component;
2704 struct clk_hw *parent_hw;
2705 const char * const clk_name = clk_hw_get_name(hw);
2706 int pre_div;
2707 unsigned int clk_pll2_out;
2708
2709 if (!rt5682_clk_check(rt5682))
2710 return -EINVAL;
2711
2712 component = rt5682->component;
2713
2714 /*
2715 * Whether the wclk's parent clk (mclk) exists or not, please ensure
2716 * it is fixed or set to 48MHz before setting wclk rate. It's a
2717 * temporary limitation. Only accept 48MHz clk as the clk provider.
2718 *
2719 * It will set the codec anyway by assuming mclk is 48MHz.
2720 */
2721 parent_hw = clk_hw_get_parent(hw);
2722 if (!parent_hw)
2723 dev_warn(rt5682->i2c_dev,
2724 "Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
2725 CLK_PLL2_FIN);
2726
2727 if (parent_rate != CLK_PLL2_FIN)
2728 dev_warn(rt5682->i2c_dev, "clk %s only support %d Hz input\n",
2729 clk_name, CLK_PLL2_FIN);
2730
2731 /*
2732 * To achieve the rate conversion from 48MHz to 44.1k or 48kHz,
2733 * PLL2 is needed.
2734 */
2735 clk_pll2_out = rate * 512;
2736 rt5682_set_component_pll(component, RT5682_PLL2, RT5682_PLL2_S_MCLK,
2737 CLK_PLL2_FIN, clk_pll2_out);
2738
2739 rt5682_set_component_sysclk(component, RT5682_SCLK_S_PLL2, 0,
2740 clk_pll2_out, SND_SOC_CLOCK_IN);
2741
2742 rt5682->lrck[RT5682_AIF1] = rate;
2743
2744 pre_div = rl6231_get_clk_info(rt5682->sysclk, rate);
2745
2746 snd_soc_component_update_bits(component, RT5682_ADDA_CLK_1,
2747 RT5682_I2S_M_DIV_MASK | RT5682_I2S_CLK_SRC_MASK,
2748 pre_div << RT5682_I2S_M_DIV_SFT |
2749 (rt5682->sysclk_src) << RT5682_I2S_CLK_SRC_SFT);
2750
2751 return 0;
2752 }
2753
rt5682_bclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2754 static unsigned long rt5682_bclk_recalc_rate(struct clk_hw *hw,
2755 unsigned long parent_rate)
2756 {
2757 struct rt5682_priv *rt5682 =
2758 container_of(hw, struct rt5682_priv,
2759 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2760 unsigned int bclks_per_wclk;
2761
2762 regmap_read(rt5682->regmap, RT5682_TDM_TCON_CTRL, &bclks_per_wclk);
2763
2764 switch (bclks_per_wclk & RT5682_TDM_BCLK_MS1_MASK) {
2765 case RT5682_TDM_BCLK_MS1_256:
2766 return parent_rate * 256;
2767 case RT5682_TDM_BCLK_MS1_128:
2768 return parent_rate * 128;
2769 case RT5682_TDM_BCLK_MS1_64:
2770 return parent_rate * 64;
2771 case RT5682_TDM_BCLK_MS1_32:
2772 return parent_rate * 32;
2773 default:
2774 return 0;
2775 }
2776 }
2777
rt5682_bclk_get_factor(unsigned long rate,unsigned long parent_rate)2778 static unsigned long rt5682_bclk_get_factor(unsigned long rate,
2779 unsigned long parent_rate)
2780 {
2781 unsigned long factor;
2782
2783 factor = rate / parent_rate;
2784 if (factor < 64)
2785 return 32;
2786 else if (factor < 128)
2787 return 64;
2788 else if (factor < 256)
2789 return 128;
2790 else
2791 return 256;
2792 }
2793
rt5682_bclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)2794 static long rt5682_bclk_round_rate(struct clk_hw *hw, unsigned long rate,
2795 unsigned long *parent_rate)
2796 {
2797 struct rt5682_priv *rt5682 =
2798 container_of(hw, struct rt5682_priv,
2799 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2800 unsigned long factor;
2801
2802 if (!*parent_rate || !rt5682_clk_check(rt5682))
2803 return -EINVAL;
2804
2805 /*
2806 * BCLK rates are set as a multiplier of WCLK in HW.
2807 * We don't allow changing the parent WCLK. We just do
2808 * some rounding down based on the parent WCLK rate
2809 * and find the appropriate multiplier of BCLK to
2810 * get the rounded down BCLK value.
2811 */
2812 factor = rt5682_bclk_get_factor(rate, *parent_rate);
2813
2814 return *parent_rate * factor;
2815 }
2816
rt5682_bclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)2817 static int rt5682_bclk_set_rate(struct clk_hw *hw, unsigned long rate,
2818 unsigned long parent_rate)
2819 {
2820 struct rt5682_priv *rt5682 =
2821 container_of(hw, struct rt5682_priv,
2822 dai_clks_hw[RT5682_DAI_BCLK_IDX]);
2823 struct snd_soc_component *component;
2824 struct snd_soc_dai *dai;
2825 unsigned long factor;
2826
2827 if (!rt5682_clk_check(rt5682))
2828 return -EINVAL;
2829
2830 component = rt5682->component;
2831
2832 factor = rt5682_bclk_get_factor(rate, parent_rate);
2833
2834 for_each_component_dais(component, dai)
2835 if (dai->id == RT5682_AIF1)
2836 return rt5682_set_bclk1_ratio(dai, factor);
2837
2838 dev_err(rt5682->i2c_dev, "dai %d not found in component\n",
2839 RT5682_AIF1);
2840 return -ENODEV;
2841 }
2842
2843 static const struct clk_ops rt5682_dai_clk_ops[RT5682_DAI_NUM_CLKS] = {
2844 [RT5682_DAI_WCLK_IDX] = {
2845 .prepare = rt5682_wclk_prepare,
2846 .unprepare = rt5682_wclk_unprepare,
2847 .recalc_rate = rt5682_wclk_recalc_rate,
2848 .round_rate = rt5682_wclk_round_rate,
2849 .set_rate = rt5682_wclk_set_rate,
2850 },
2851 [RT5682_DAI_BCLK_IDX] = {
2852 .recalc_rate = rt5682_bclk_recalc_rate,
2853 .round_rate = rt5682_bclk_round_rate,
2854 .set_rate = rt5682_bclk_set_rate,
2855 },
2856 };
2857
rt5682_register_dai_clks(struct rt5682_priv * rt5682)2858 int rt5682_register_dai_clks(struct rt5682_priv *rt5682)
2859 {
2860 struct device *dev = rt5682->i2c_dev;
2861 struct rt5682_platform_data *pdata = &rt5682->pdata;
2862 struct clk_hw *dai_clk_hw;
2863 int i, ret;
2864
2865 for (i = 0; i < RT5682_DAI_NUM_CLKS; ++i) {
2866 struct clk_init_data init = { };
2867 const struct clk_hw *parent;
2868
2869 dai_clk_hw = &rt5682->dai_clks_hw[i];
2870
2871 switch (i) {
2872 case RT5682_DAI_WCLK_IDX:
2873 /* Make MCLK the parent of WCLK */
2874 if (rt5682->mclk) {
2875 parent = __clk_get_hw(rt5682->mclk);
2876 init.parent_hws = &parent;
2877 init.num_parents = 1;
2878 }
2879 break;
2880 case RT5682_DAI_BCLK_IDX:
2881 /* Make WCLK the parent of BCLK */
2882 parent = &rt5682->dai_clks_hw[RT5682_DAI_WCLK_IDX];
2883 init.parent_hws = &parent;
2884 init.num_parents = 1;
2885 break;
2886 default:
2887 dev_err(dev, "Invalid clock index\n");
2888 return -EINVAL;
2889 }
2890
2891 init.name = pdata->dai_clk_names[i];
2892 init.ops = &rt5682_dai_clk_ops[i];
2893 init.flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_GATE;
2894 dai_clk_hw->init = &init;
2895
2896 ret = devm_clk_hw_register(dev, dai_clk_hw);
2897 if (ret) {
2898 dev_warn(dev, "Failed to register %s: %d\n",
2899 init.name, ret);
2900 return ret;
2901 }
2902
2903 if (dev->of_node) {
2904 devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
2905 dai_clk_hw);
2906 } else {
2907 ret = devm_clk_hw_register_clkdev(dev, dai_clk_hw,
2908 init.name,
2909 dev_name(dev));
2910 if (ret)
2911 return ret;
2912 }
2913 }
2914
2915 return 0;
2916 }
2917 EXPORT_SYMBOL_GPL(rt5682_register_dai_clks);
2918 #endif /* CONFIG_COMMON_CLK */
2919
rt5682_probe(struct snd_soc_component * component)2920 static int rt5682_probe(struct snd_soc_component *component)
2921 {
2922 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2923 struct sdw_slave *slave;
2924 unsigned long time;
2925 struct snd_soc_dapm_context *dapm = &component->dapm;
2926
2927 rt5682->component = component;
2928
2929 if (rt5682->is_sdw) {
2930 slave = rt5682->slave;
2931 time = wait_for_completion_timeout(
2932 &slave->initialization_complete,
2933 msecs_to_jiffies(RT5682_PROBE_TIMEOUT));
2934 if (!time) {
2935 dev_err(&slave->dev, "Initialization not complete, timed out\n");
2936 return -ETIMEDOUT;
2937 }
2938 }
2939
2940 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
2941 snd_soc_dapm_disable_pin(dapm, "Vref2");
2942 snd_soc_dapm_sync(dapm);
2943 return 0;
2944 }
2945
rt5682_remove(struct snd_soc_component * component)2946 static void rt5682_remove(struct snd_soc_component *component)
2947 {
2948 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2949
2950 rt5682_reset(rt5682);
2951 }
2952
2953 #ifdef CONFIG_PM
rt5682_suspend(struct snd_soc_component * component)2954 static int rt5682_suspend(struct snd_soc_component *component)
2955 {
2956 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
2957 unsigned int val;
2958
2959 if (rt5682->is_sdw)
2960 return 0;
2961
2962 cancel_delayed_work_sync(&rt5682->jack_detect_work);
2963 cancel_delayed_work_sync(&rt5682->jd_check_work);
2964 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
2965 val = snd_soc_component_read(component,
2966 RT5682_CBJ_CTRL_2) & RT5682_JACK_TYPE_MASK;
2967
2968 switch (val) {
2969 case 0x1:
2970 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2971 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2972 RT5682_SAR_SEL_MB1_NOSEL | RT5682_SAR_SEL_MB2_SEL);
2973 break;
2974 case 0x2:
2975 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2976 RT5682_SAR_SEL_MB1_MASK | RT5682_SAR_SEL_MB2_MASK,
2977 RT5682_SAR_SEL_MB1_SEL | RT5682_SAR_SEL_MB2_NOSEL);
2978 break;
2979 default:
2980 break;
2981 }
2982
2983 /* enter SAR ADC power saving mode */
2984 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2985 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK |
2986 RT5682_SAR_SEL_MB1_MB2_MASK, 0);
2987 usleep_range(5000, 6000);
2988 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
2989 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
2990 RT5682_CTRL_MB1_REG | RT5682_CTRL_MB2_REG);
2991 usleep_range(10000, 12000);
2992 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
2993 RT5682_SAR_BUTT_DET_MASK | RT5682_SAR_BUTDET_MODE_MASK,
2994 RT5682_SAR_BUTT_DET_EN | RT5682_SAR_BUTDET_POW_SAV);
2995 snd_soc_component_update_bits(component, RT5682_HP_CHARGE_PUMP_1,
2996 RT5682_OSW_L_MASK | RT5682_OSW_R_MASK, 0);
2997 }
2998
2999 regcache_cache_only(rt5682->regmap, true);
3000 regcache_mark_dirty(rt5682->regmap);
3001 return 0;
3002 }
3003
rt5682_resume(struct snd_soc_component * component)3004 static int rt5682_resume(struct snd_soc_component *component)
3005 {
3006 struct rt5682_priv *rt5682 = snd_soc_component_get_drvdata(component);
3007
3008 if (rt5682->is_sdw)
3009 return 0;
3010
3011 regcache_cache_only(rt5682->regmap, false);
3012 regcache_sync(rt5682->regmap);
3013
3014 if (rt5682->hs_jack && (rt5682->jack_type & SND_JACK_HEADSET) == SND_JACK_HEADSET) {
3015 snd_soc_component_update_bits(component, RT5682_SAR_IL_CMD_1,
3016 RT5682_SAR_BUTDET_MODE_MASK | RT5682_SAR_SEL_MB1_MB2_MASK,
3017 RT5682_SAR_BUTDET_POW_NORM | RT5682_SAR_SEL_MB1_MB2_AUTO);
3018 usleep_range(5000, 6000);
3019 snd_soc_component_update_bits(component, RT5682_CBJ_CTRL_1,
3020 RT5682_MB1_PATH_MASK | RT5682_MB2_PATH_MASK,
3021 RT5682_CTRL_MB1_FSM | RT5682_CTRL_MB2_FSM);
3022 snd_soc_component_update_bits(component, RT5682_PWR_ANLG_3,
3023 RT5682_PWR_CBJ, RT5682_PWR_CBJ);
3024 }
3025
3026 rt5682->jack_type = 0;
3027 mod_delayed_work(system_power_efficient_wq,
3028 &rt5682->jack_detect_work, msecs_to_jiffies(0));
3029
3030 return 0;
3031 }
3032 #else
3033 #define rt5682_suspend NULL
3034 #define rt5682_resume NULL
3035 #endif
3036
3037 const struct snd_soc_dai_ops rt5682_aif1_dai_ops = {
3038 .hw_params = rt5682_hw_params,
3039 .set_fmt = rt5682_set_dai_fmt,
3040 .set_tdm_slot = rt5682_set_tdm_slot,
3041 .set_bclk_ratio = rt5682_set_bclk1_ratio,
3042 };
3043 EXPORT_SYMBOL_GPL(rt5682_aif1_dai_ops);
3044
3045 const struct snd_soc_dai_ops rt5682_aif2_dai_ops = {
3046 .hw_params = rt5682_hw_params,
3047 .set_fmt = rt5682_set_dai_fmt,
3048 .set_bclk_ratio = rt5682_set_bclk2_ratio,
3049 };
3050 EXPORT_SYMBOL_GPL(rt5682_aif2_dai_ops);
3051
3052 const struct snd_soc_component_driver rt5682_soc_component_dev = {
3053 .probe = rt5682_probe,
3054 .remove = rt5682_remove,
3055 .suspend = rt5682_suspend,
3056 .resume = rt5682_resume,
3057 .set_bias_level = rt5682_set_bias_level,
3058 .controls = rt5682_snd_controls,
3059 .num_controls = ARRAY_SIZE(rt5682_snd_controls),
3060 .dapm_widgets = rt5682_dapm_widgets,
3061 .num_dapm_widgets = ARRAY_SIZE(rt5682_dapm_widgets),
3062 .dapm_routes = rt5682_dapm_routes,
3063 .num_dapm_routes = ARRAY_SIZE(rt5682_dapm_routes),
3064 .set_sysclk = rt5682_set_component_sysclk,
3065 .set_pll = rt5682_set_component_pll,
3066 .set_jack = rt5682_set_jack_detect,
3067 .use_pmdown_time = 1,
3068 .endianness = 1,
3069 };
3070 EXPORT_SYMBOL_GPL(rt5682_soc_component_dev);
3071
rt5682_parse_dt(struct rt5682_priv * rt5682,struct device * dev)3072 int rt5682_parse_dt(struct rt5682_priv *rt5682, struct device *dev)
3073 {
3074
3075 device_property_read_u32(dev, "realtek,dmic1-data-pin",
3076 &rt5682->pdata.dmic1_data_pin);
3077 device_property_read_u32(dev, "realtek,dmic1-clk-pin",
3078 &rt5682->pdata.dmic1_clk_pin);
3079 device_property_read_u32(dev, "realtek,jd-src",
3080 &rt5682->pdata.jd_src);
3081 device_property_read_u32(dev, "realtek,btndet-delay",
3082 &rt5682->pdata.btndet_delay);
3083 device_property_read_u32(dev, "realtek,dmic-clk-rate-hz",
3084 &rt5682->pdata.dmic_clk_rate);
3085 device_property_read_u32(dev, "realtek,dmic-delay-ms",
3086 &rt5682->pdata.dmic_delay);
3087
3088 rt5682->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
3089 "realtek,ldo1-en-gpios", 0);
3090
3091 if (device_property_read_string_array(dev, "clock-output-names",
3092 rt5682->pdata.dai_clk_names,
3093 RT5682_DAI_NUM_CLKS) < 0)
3094 dev_warn(dev, "Using default DAI clk names: %s, %s\n",
3095 rt5682->pdata.dai_clk_names[RT5682_DAI_WCLK_IDX],
3096 rt5682->pdata.dai_clk_names[RT5682_DAI_BCLK_IDX]);
3097
3098 rt5682->pdata.dmic_clk_driving_high = device_property_read_bool(dev,
3099 "realtek,dmic-clk-driving-high");
3100
3101 return 0;
3102 }
3103 EXPORT_SYMBOL_GPL(rt5682_parse_dt);
3104
rt5682_calibrate(struct rt5682_priv * rt5682)3105 void rt5682_calibrate(struct rt5682_priv *rt5682)
3106 {
3107 int value, count;
3108
3109 mutex_lock(&rt5682->calibrate_mutex);
3110
3111 rt5682_reset(rt5682);
3112 regmap_write(rt5682->regmap, RT5682_I2C_CTRL, 0x000f);
3113 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xa2af);
3114 usleep_range(15000, 20000);
3115 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0xf2af);
3116 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0300);
3117 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x8000);
3118 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0100);
3119 regmap_write(rt5682->regmap, RT5682_HP_IMP_SENS_CTRL_19, 0x3800);
3120 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x3000);
3121 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x7005);
3122 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0x686c);
3123 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0d0d);
3124 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_2, 0x0321);
3125 regmap_write(rt5682->regmap, RT5682_HP_LOGIC_CTRL_2, 0x0004);
3126 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3127 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_3, 0x06a1);
3128 regmap_write(rt5682->regmap, RT5682_A_DAC1_MUX, 0x0311);
3129 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0x7c00);
3130
3131 regmap_write(rt5682->regmap, RT5682_HP_CALIB_CTRL_1, 0xfc00);
3132
3133 for (count = 0; count < 60; count++) {
3134 regmap_read(rt5682->regmap, RT5682_HP_CALIB_STA_1, &value);
3135 if (!(value & 0x8000))
3136 break;
3137
3138 usleep_range(10000, 10005);
3139 }
3140
3141 if (count >= 60)
3142 dev_err(rt5682->component->dev, "HP Calibration Failure\n");
3143
3144 /* restore settings */
3145 regmap_write(rt5682->regmap, RT5682_PWR_ANLG_1, 0x002f);
3146 regmap_write(rt5682->regmap, RT5682_MICBIAS_2, 0x0080);
3147 regmap_write(rt5682->regmap, RT5682_GLB_CLK, 0x0000);
3148 regmap_write(rt5682->regmap, RT5682_PWR_DIG_1, 0x0000);
3149 regmap_write(rt5682->regmap, RT5682_CHOP_DAC, 0x2000);
3150 regmap_write(rt5682->regmap, RT5682_CALIB_ADC_CTRL, 0x2005);
3151 regmap_write(rt5682->regmap, RT5682_STO1_ADC_MIXER, 0xc0c4);
3152 regmap_write(rt5682->regmap, RT5682_CAL_REC, 0x0c0c);
3153
3154 mutex_unlock(&rt5682->calibrate_mutex);
3155 }
3156 EXPORT_SYMBOL_GPL(rt5682_calibrate);
3157
3158 MODULE_DESCRIPTION("ASoC RT5682 driver");
3159 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
3160 MODULE_LICENSE("GPL v2");
3161