1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pin Control driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 *
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 * Copyright (C) 2017 Marek Vasut
10 */
11
12 #define DRV_NAME "sh-pfc"
13
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <dm/device_compat.h>
18 #include <dm/devres.h>
19 #include <dm/pinctrl.h>
20 #include <linux/bitops.h>
21 #include <linux/bug.h>
22 #include <linux/io.h>
23 #include <linux/sizes.h>
24
25 #include "sh_pfc.h"
26
27 enum sh_pfc_model {
28 SH_PFC_R8A7790 = 0,
29 SH_PFC_R8A7791,
30 SH_PFC_R8A7792,
31 SH_PFC_R8A7793,
32 SH_PFC_R8A7794,
33 SH_PFC_R8A7795,
34 SH_PFC_R8A7796,
35 SH_PFC_R8A774A1,
36 SH_PFC_R8A774B1,
37 SH_PFC_R8A774C0,
38 SH_PFC_R8A774E1,
39 SH_PFC_R8A77965,
40 SH_PFC_R8A77970,
41 SH_PFC_R8A77980,
42 SH_PFC_R8A77990,
43 SH_PFC_R8A77995,
44 SH_PFC_R8A779A0,
45 };
46
47 struct sh_pfc_pin_config {
48 u32 type;
49 const char *name;
50 };
51
52 struct sh_pfc_pinctrl {
53 struct sh_pfc *pfc;
54
55 struct sh_pfc_pin_config *configs;
56 };
57
58 struct sh_pfc_pin_range {
59 u16 start;
60 u16 end;
61 };
62
63 struct sh_pfc_pinctrl_priv {
64 struct sh_pfc pfc;
65 struct sh_pfc_pinctrl pmx;
66 };
67
sh_pfc_get_pin_index(struct sh_pfc * pfc,unsigned int pin)68 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
69 {
70 unsigned int offset;
71 unsigned int i;
72
73 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
74 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
75
76 if (pin <= range->end)
77 return pin >= range->start
78 ? offset + pin - range->start : -1;
79
80 offset += range->end - range->start + 1;
81 }
82
83 return -EINVAL;
84 }
85
sh_pfc_enum_in_range(u16 enum_id,const struct pinmux_range * r)86 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
87 {
88 if (enum_id < r->begin)
89 return 0;
90
91 if (enum_id > r->end)
92 return 0;
93
94 return 1;
95 }
96
sh_pfc_read_raw_reg(void __iomem * mapped_reg,unsigned int reg_width)97 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
98 {
99 switch (reg_width) {
100 case 8:
101 return readb(mapped_reg);
102 case 16:
103 return readw(mapped_reg);
104 case 32:
105 return readl(mapped_reg);
106 }
107
108 BUG();
109 return 0;
110 }
111
sh_pfc_write_raw_reg(void __iomem * mapped_reg,unsigned int reg_width,u32 data)112 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
113 u32 data)
114 {
115 switch (reg_width) {
116 case 8:
117 writeb(data, mapped_reg);
118 return;
119 case 16:
120 writew(data, mapped_reg);
121 return;
122 case 32:
123 writel(data, mapped_reg);
124 return;
125 }
126
127 BUG();
128 }
129
sh_pfc_read(struct sh_pfc * pfc,u32 reg)130 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
131 {
132 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
133 }
134
sh_pfc_unlock_reg(struct sh_pfc * pfc,u32 reg,u32 data)135 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
136 {
137 u32 unlock;
138
139 if (!pfc->info->unlock_reg)
140 return;
141
142 if (pfc->info->unlock_reg >= 0x80000000UL)
143 unlock = pfc->info->unlock_reg;
144 else
145 /* unlock_reg is a mask */
146 unlock = reg & ~pfc->info->unlock_reg;
147
148 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);
149 }
150
sh_pfc_write(struct sh_pfc * pfc,u32 reg,u32 data)151 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
152 {
153 sh_pfc_unlock_reg(pfc, reg, data);
154 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
155 }
156
sh_pfc_config_reg_helper(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int in_pos,void __iomem ** mapped_regp,u32 * maskp,unsigned int * posp)157 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
158 const struct pinmux_cfg_reg *crp,
159 unsigned int in_pos,
160 void __iomem **mapped_regp, u32 *maskp,
161 unsigned int *posp)
162 {
163 unsigned int k;
164
165 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
166
167 if (crp->field_width) {
168 *maskp = (1 << crp->field_width) - 1;
169 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
170 } else {
171 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
172 *posp = crp->reg_width;
173 for (k = 0; k <= in_pos; k++)
174 *posp -= crp->var_field_width[k];
175 }
176 }
177
sh_pfc_write_config_reg(struct sh_pfc * pfc,const struct pinmux_cfg_reg * crp,unsigned int field,u32 value)178 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
179 const struct pinmux_cfg_reg *crp,
180 unsigned int field, u32 value)
181 {
182 void __iomem *mapped_reg;
183 unsigned int pos;
184 u32 mask, data;
185
186 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
187
188 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
189 "r_width = %u, f_width = %u\n",
190 crp->reg, value, field, crp->reg_width, crp->field_width);
191
192 mask = ~(mask << pos);
193 value = value << pos;
194
195 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
196 data &= mask;
197 data |= value;
198
199 sh_pfc_unlock_reg(pfc, crp->reg, data);
200 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
201 }
202
sh_pfc_get_config_reg(struct sh_pfc * pfc,u16 enum_id,const struct pinmux_cfg_reg ** crp,unsigned int * fieldp,u32 * valuep)203 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
204 const struct pinmux_cfg_reg **crp,
205 unsigned int *fieldp, u32 *valuep)
206 {
207 unsigned int k = 0;
208
209 while (1) {
210 const struct pinmux_cfg_reg *config_reg =
211 pfc->info->cfg_regs + k;
212 unsigned int r_width = config_reg->reg_width;
213 unsigned int f_width = config_reg->field_width;
214 unsigned int curr_width;
215 unsigned int bit_pos;
216 unsigned int pos = 0;
217 unsigned int m = 0;
218
219 if (!r_width)
220 break;
221
222 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
223 u32 ncomb;
224 u32 n;
225
226 if (f_width)
227 curr_width = f_width;
228 else
229 curr_width = config_reg->var_field_width[m];
230
231 ncomb = 1 << curr_width;
232 for (n = 0; n < ncomb; n++) {
233 if (config_reg->enum_ids[pos + n] == enum_id) {
234 *crp = config_reg;
235 *fieldp = m;
236 *valuep = n;
237 return 0;
238 }
239 }
240 pos += ncomb;
241 m++;
242 }
243 k++;
244 }
245
246 return -EINVAL;
247 }
248
sh_pfc_mark_to_enum(struct sh_pfc * pfc,u16 mark,int pos,u16 * enum_idp)249 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
250 u16 *enum_idp)
251 {
252 const u16 *data = pfc->info->pinmux_data;
253 unsigned int k;
254
255 if (pos) {
256 *enum_idp = data[pos + 1];
257 return pos + 1;
258 }
259
260 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
261 if (data[k] == mark) {
262 *enum_idp = data[k + 1];
263 return k + 1;
264 }
265 }
266
267 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
268 mark);
269 return -EINVAL;
270 }
271
sh_pfc_config_mux(struct sh_pfc * pfc,unsigned mark,int pinmux_type)272 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
273 {
274 const struct pinmux_range *range;
275 int pos = 0;
276
277 switch (pinmux_type) {
278 case PINMUX_TYPE_GPIO:
279 case PINMUX_TYPE_FUNCTION:
280 range = NULL;
281 break;
282
283 case PINMUX_TYPE_OUTPUT:
284 range = &pfc->info->output;
285 break;
286
287 case PINMUX_TYPE_INPUT:
288 range = &pfc->info->input;
289 break;
290
291 default:
292 return -EINVAL;
293 }
294
295 /* Iterate over all the configuration fields we need to update. */
296 while (1) {
297 const struct pinmux_cfg_reg *cr;
298 unsigned int field;
299 u16 enum_id;
300 u32 value;
301 int in_range;
302 int ret;
303
304 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
305 if (pos < 0)
306 return pos;
307
308 if (!enum_id)
309 break;
310
311 /* Check if the configuration field selects a function. If it
312 * doesn't, skip the field if it's not applicable to the
313 * requested pinmux type.
314 */
315 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
316 if (!in_range) {
317 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
318 /* Functions are allowed to modify all
319 * fields.
320 */
321 in_range = 1;
322 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
323 /* Input/output types can only modify fields
324 * that correspond to their respective ranges.
325 */
326 in_range = sh_pfc_enum_in_range(enum_id, range);
327
328 /*
329 * special case pass through for fixed
330 * input-only or output-only pins without
331 * function enum register association.
332 */
333 if (in_range && enum_id == range->force)
334 continue;
335 }
336 /* GPIOs are only allowed to modify function fields. */
337 }
338
339 if (!in_range)
340 continue;
341
342 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
343 if (ret < 0)
344 return ret;
345
346 sh_pfc_write_config_reg(pfc, cr, field, value);
347 }
348
349 return 0;
350 }
351
352 const struct pinmux_bias_reg *
sh_pfc_pin_to_bias_reg(const struct sh_pfc * pfc,unsigned int pin,unsigned int * bit)353 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
354 unsigned int *bit)
355 {
356 unsigned int i, j;
357
358 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
359 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
360 if (pfc->info->bias_regs[i].pins[j] == pin) {
361 *bit = j;
362 return &pfc->info->bias_regs[i];
363 }
364 }
365 }
366
367 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
368
369 return NULL;
370 }
371
sh_pfc_init_ranges(struct sh_pfc * pfc)372 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
373 {
374 struct sh_pfc_pin_range *range;
375 unsigned int nr_ranges;
376 unsigned int i;
377
378 if (pfc->info->pins[0].pin == (u16)-1) {
379 /* Pin number -1 denotes that the SoC doesn't report pin numbers
380 * in its pin arrays yet. Consider the pin numbers range as
381 * continuous and allocate a single range.
382 */
383 pfc->nr_ranges = 1;
384 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
385 if (pfc->ranges == NULL)
386 return -ENOMEM;
387
388 pfc->ranges->start = 0;
389 pfc->ranges->end = pfc->info->nr_pins - 1;
390 pfc->nr_gpio_pins = pfc->info->nr_pins;
391
392 return 0;
393 }
394
395 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
396 * be sorted by pin numbers, and pins without a GPIO port must come
397 * last.
398 */
399 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
400 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
401 nr_ranges++;
402 }
403
404 pfc->nr_ranges = nr_ranges;
405 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
406 if (pfc->ranges == NULL)
407 return -ENOMEM;
408
409 range = pfc->ranges;
410 range->start = pfc->info->pins[0].pin;
411
412 for (i = 1; i < pfc->info->nr_pins; ++i) {
413 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
414 continue;
415
416 range->end = pfc->info->pins[i-1].pin;
417 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
418 pfc->nr_gpio_pins = range->end + 1;
419
420 range++;
421 range->start = pfc->info->pins[i].pin;
422 }
423
424 range->end = pfc->info->pins[i-1].pin;
425 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
426 pfc->nr_gpio_pins = range->end + 1;
427
428 return 0;
429 }
430
sh_pfc_pinctrl_get_pins_count(struct udevice * dev)431 static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
432 {
433 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
434
435 return priv->pfc.info->nr_pins;
436 }
437
sh_pfc_pinctrl_get_pin_name(struct udevice * dev,unsigned selector)438 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
439 unsigned selector)
440 {
441 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
442
443 return priv->pfc.info->pins[selector].name;
444 }
445
sh_pfc_pinctrl_get_groups_count(struct udevice * dev)446 static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
447 {
448 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
449
450 return priv->pfc.info->nr_groups;
451 }
452
sh_pfc_pinctrl_get_group_name(struct udevice * dev,unsigned selector)453 static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
454 unsigned selector)
455 {
456 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
457
458 return priv->pfc.info->groups[selector].name;
459 }
460
sh_pfc_pinctrl_get_pin_muxing(struct udevice * dev,unsigned int selector,char * buf,int size)461 static int sh_pfc_pinctrl_get_pin_muxing(struct udevice *dev,
462 unsigned int selector,
463 char *buf, int size)
464 {
465 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
466 struct sh_pfc_pinctrl *pmx = &priv->pmx;
467 struct sh_pfc *pfc = &priv->pfc;
468 struct sh_pfc_pin_config *cfg;
469 const struct sh_pfc_pin *pin;
470 int idx;
471
472 pin = &priv->pfc.info->pins[selector];
473 if (!pin) {
474 snprintf(buf, size, "Unknown");
475 return -EINVAL;
476 }
477
478 idx = sh_pfc_get_pin_index(pfc, pin->pin);
479 cfg = &pmx->configs[idx];
480 snprintf(buf, size, "%s", cfg->name);
481
482 return 0;
483 }
484
sh_pfc_pinctrl_get_functions_count(struct udevice * dev)485 static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
486 {
487 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
488
489 return priv->pfc.info->nr_functions;
490 }
491
sh_pfc_pinctrl_get_function_name(struct udevice * dev,unsigned selector)492 static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
493 unsigned selector)
494 {
495 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
496
497 return priv->pfc.info->functions[selector].name;
498 }
499
sh_pfc_gpio_request_enable(struct udevice * dev,unsigned pin_selector)500 static int sh_pfc_gpio_request_enable(struct udevice *dev,
501 unsigned pin_selector)
502 {
503 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
504 struct sh_pfc_pinctrl *pmx = &priv->pmx;
505 struct sh_pfc *pfc = &priv->pfc;
506 struct sh_pfc_pin_config *cfg;
507 const struct sh_pfc_pin *pin = NULL;
508 int i, ret, idx;
509
510 for (i = 0; i < pfc->info->nr_pins; i++) {
511 if (priv->pfc.info->pins[i].pin != pin_selector)
512 continue;
513
514 pin = &priv->pfc.info->pins[i];
515 break;
516 }
517
518 if (!pin)
519 return -EINVAL;
520
521 idx = sh_pfc_get_pin_index(pfc, pin->pin);
522 cfg = &pmx->configs[idx];
523
524 if (cfg->type != PINMUX_TYPE_NONE) {
525 if (!strcmp(cfg->name, pin->name))
526 return 0;
527
528 dev_err(pfc->dev, "Pin already used as %s\n",
529 cfg->name);
530 return -EBUSY;
531 }
532
533 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
534 if (ret)
535 return ret;
536
537 cfg->type = PINMUX_TYPE_GPIO;
538 cfg->name = "gpio";
539
540 return 0;
541 }
542
sh_pfc_gpio_disable_free(struct udevice * dev,unsigned pin_selector)543 static int sh_pfc_gpio_disable_free(struct udevice *dev,
544 unsigned pin_selector)
545 {
546 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
547 struct sh_pfc_pinctrl *pmx = &priv->pmx;
548 struct sh_pfc *pfc = &priv->pfc;
549 struct sh_pfc_pin_config *cfg;
550 const struct sh_pfc_pin *pin = NULL;
551 int i, idx;
552
553 for (i = 0; i < pfc->info->nr_pins; i++) {
554 if (priv->pfc.info->pins[i].pin != pin_selector)
555 continue;
556
557 pin = &priv->pfc.info->pins[i];
558 break;
559 }
560
561 if (!pin)
562 return -EINVAL;
563
564 idx = sh_pfc_get_pin_index(pfc, pin->pin);
565 cfg = &pmx->configs[idx];
566
567 cfg->type = PINMUX_TYPE_NONE;
568 cfg->name = "none";
569
570 return 0;
571 }
572
sh_pfc_pinctrl_pin_set(struct udevice * dev,unsigned pin_selector,unsigned func_selector)573 static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
574 unsigned func_selector)
575 {
576 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
577 struct sh_pfc_pinctrl *pmx = &priv->pmx;
578 struct sh_pfc *pfc = &priv->pfc;
579 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
580 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
581 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
582 int ret;
583
584 if (cfg->type != PINMUX_TYPE_NONE) {
585 if (!strcmp(cfg->name, pin->name))
586 return 0;
587
588 dev_err(pfc->dev, "Pin already used as %s\n",
589 cfg->name);
590 return -EBUSY;
591 }
592
593 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
594 if (ret)
595 return ret;
596
597 cfg->type = PINMUX_TYPE_FUNCTION;
598 cfg->name = "function";
599
600 return 0;
601 }
602
sh_pfc_pinctrl_group_set(struct udevice * dev,unsigned group_selector,unsigned func_selector)603 static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
604 unsigned func_selector)
605 {
606 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
607 struct sh_pfc_pinctrl *pmx = &priv->pmx;
608 struct sh_pfc *pfc = &priv->pfc;
609 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
610 bool grp_pins_configured = true;
611 struct sh_pfc_pin_config *cfg;
612 unsigned int i;
613 int ret = 0;
614 int idx;
615
616 for (i = 0; i < grp->nr_pins; ++i) {
617 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
618 cfg = &pmx->configs[idx];
619
620 if (cfg->type != PINMUX_TYPE_NONE) {
621 if (!strcmp(cfg->name, grp->name))
622 continue;
623
624 dev_err(pfc->dev, "Pin already used as %s\n",
625 cfg->name);
626 ret = -EBUSY;
627 goto done;
628 } else {
629 grp_pins_configured = false;
630 }
631 }
632
633 if (grp_pins_configured)
634 return 0;
635
636 for (i = 0; i < grp->nr_pins; ++i) {
637 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
638 if (ret < 0)
639 break;
640
641 idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
642 cfg = &pmx->configs[idx];
643 cfg->type = PINMUX_TYPE_FUNCTION;
644 cfg->name = priv->pfc.info->groups[group_selector].name;
645 }
646
647 done:
648 return ret;
649 }
650 #if CONFIG_IS_ENABLED(PINCONF)
651 static const struct pinconf_param sh_pfc_pinconf_params[] = {
652 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
653 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
654 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
655 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
656 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
657 };
658
659 static void __iomem *
sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc * pfc,unsigned int pin,unsigned int * offset,unsigned int * size)660 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
661 unsigned int *offset, unsigned int *size)
662 {
663 const struct pinmux_drive_reg_field *field;
664 const struct pinmux_drive_reg *reg;
665 unsigned int i;
666
667 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
668 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
669 field = ®->fields[i];
670
671 if (field->size && field->pin == pin) {
672 *offset = field->offset;
673 *size = field->size;
674
675 return (void __iomem *)(uintptr_t)reg->reg;
676 }
677 }
678 }
679
680 return NULL;
681 }
682
sh_pfc_pinconf_set_drive_strength(struct sh_pfc * pfc,unsigned int pin,u16 strength)683 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
684 unsigned int pin, u16 strength)
685 {
686 unsigned int offset;
687 unsigned int size;
688 unsigned int step;
689 void __iomem *reg;
690 u32 val;
691
692 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
693 if (!reg)
694 return -EINVAL;
695
696 step = size == 2 ? 6 : 3;
697
698 if (strength < step || strength > 24)
699 return -EINVAL;
700
701 /* Convert the value from mA based on a full drive strength value of
702 * 24mA. We can make the full value configurable later if needed.
703 */
704 strength = strength / step - 1;
705
706 val = sh_pfc_read_raw_reg(reg, 32);
707 val &= ~GENMASK(offset + 4 - 1, offset);
708 val |= strength << offset;
709
710 sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val);
711 sh_pfc_write_raw_reg(reg, 32, val);
712
713 return 0;
714 }
715
716 /* Check whether the requested parameter is supported for a pin. */
sh_pfc_pinconf_validate(struct sh_pfc * pfc,unsigned int _pin,unsigned int param)717 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
718 unsigned int param)
719 {
720 int idx = sh_pfc_get_pin_index(pfc, _pin);
721 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
722
723 switch (param) {
724 case PIN_CONFIG_BIAS_DISABLE:
725 return pin->configs &
726 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
727
728 case PIN_CONFIG_BIAS_PULL_UP:
729 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
730
731 case PIN_CONFIG_BIAS_PULL_DOWN:
732 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
733
734 case PIN_CONFIG_DRIVE_STRENGTH:
735 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
736
737 case PIN_CONFIG_POWER_SOURCE:
738 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
739
740 default:
741 return false;
742 }
743 }
744
sh_pfc_pinconf_set(struct sh_pfc_pinctrl * pmx,unsigned _pin,unsigned int param,unsigned int arg)745 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
746 unsigned int param, unsigned int arg)
747 {
748 struct sh_pfc *pfc = pmx->pfc;
749 void __iomem *pocctrl;
750 u32 addr, val;
751 int bit, ret;
752
753 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
754 return -ENOTSUPP;
755
756 switch (param) {
757 case PIN_CONFIG_BIAS_PULL_UP:
758 case PIN_CONFIG_BIAS_PULL_DOWN:
759 case PIN_CONFIG_BIAS_DISABLE:
760 if (!pfc->info->ops || !pfc->info->ops->set_bias)
761 return -ENOTSUPP;
762
763 pfc->info->ops->set_bias(pfc, _pin, param);
764
765 break;
766
767 case PIN_CONFIG_DRIVE_STRENGTH:
768 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
769 if (ret < 0)
770 return ret;
771
772 break;
773
774 case PIN_CONFIG_POWER_SOURCE:
775 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
776 return -ENOTSUPP;
777
778 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
779 if (bit < 0) {
780 printf("invalid pin %#x", _pin);
781 return bit;
782 }
783
784 if (arg != 1800 && arg != 3300)
785 return -EINVAL;
786
787 pocctrl = (void __iomem *)(uintptr_t)addr;
788
789 val = sh_pfc_read_raw_reg(pocctrl, 32);
790 if (arg == 3300)
791 val |= BIT(bit);
792 else
793 val &= ~BIT(bit);
794
795 sh_pfc_unlock_reg(pfc, addr, val);
796 sh_pfc_write_raw_reg(pocctrl, 32, val);
797
798 break;
799
800 default:
801 return -ENOTSUPP;
802 }
803
804 return 0;
805 }
806
sh_pfc_pinconf_pin_set(struct udevice * dev,unsigned int pin_selector,unsigned int param,unsigned int arg)807 static int sh_pfc_pinconf_pin_set(struct udevice *dev,
808 unsigned int pin_selector,
809 unsigned int param, unsigned int arg)
810 {
811 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
812 struct sh_pfc_pinctrl *pmx = &priv->pmx;
813 struct sh_pfc *pfc = &priv->pfc;
814 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
815
816 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
817
818 return 0;
819 }
820
sh_pfc_pinconf_group_set(struct udevice * dev,unsigned int group_selector,unsigned int param,unsigned int arg)821 static int sh_pfc_pinconf_group_set(struct udevice *dev,
822 unsigned int group_selector,
823 unsigned int param, unsigned int arg)
824 {
825 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
826 struct sh_pfc_pinctrl *pmx = &priv->pmx;
827 struct sh_pfc *pfc = &priv->pfc;
828 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
829 unsigned int i;
830
831 for (i = 0; i < grp->nr_pins; i++)
832 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
833
834 return 0;
835 }
836 #endif
837
838 static struct pinctrl_ops sh_pfc_pinctrl_ops = {
839 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
840 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
841 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
842 .get_group_name = sh_pfc_pinctrl_get_group_name,
843 .get_pin_muxing = sh_pfc_pinctrl_get_pin_muxing,
844 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
845 .get_function_name = sh_pfc_pinctrl_get_function_name,
846
847 #if CONFIG_IS_ENABLED(PINCONF)
848 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
849 .pinconf_params = sh_pfc_pinconf_params,
850 .pinconf_set = sh_pfc_pinconf_pin_set,
851 .pinconf_group_set = sh_pfc_pinconf_group_set,
852 #endif
853 .pinmux_set = sh_pfc_pinctrl_pin_set,
854 .pinmux_group_set = sh_pfc_pinctrl_group_set,
855 .set_state = pinctrl_generic_set_state,
856
857 .gpio_request_enable = sh_pfc_gpio_request_enable,
858 .gpio_disable_free = sh_pfc_gpio_disable_free,
859 };
860
sh_pfc_map_pins(struct sh_pfc * pfc,struct sh_pfc_pinctrl * pmx)861 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
862 {
863 unsigned int i;
864
865 /* Allocate and initialize the pins and configs arrays. */
866 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
867 GFP_KERNEL);
868 if (unlikely(!pmx->configs))
869 return -ENOMEM;
870
871 for (i = 0; i < pfc->info->nr_pins; ++i) {
872 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
873 cfg->type = PINMUX_TYPE_NONE;
874 cfg->name = "none";
875 }
876
877 return 0;
878 }
879
880
sh_pfc_pinctrl_probe(struct udevice * dev)881 static int sh_pfc_pinctrl_probe(struct udevice *dev)
882 {
883 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
884 enum sh_pfc_model model = dev_get_driver_data(dev);
885 fdt_addr_t base;
886
887 base = dev_read_addr(dev);
888 if (base == FDT_ADDR_T_NONE)
889 return -EINVAL;
890
891 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
892 if (!priv->pfc.regs)
893 return -ENOMEM;
894
895 #ifdef CONFIG_PINCTRL_PFC_R8A7790
896 if (model == SH_PFC_R8A7790)
897 priv->pfc.info = &r8a7790_pinmux_info;
898 #endif
899 #ifdef CONFIG_PINCTRL_PFC_R8A7791
900 if (model == SH_PFC_R8A7791)
901 priv->pfc.info = &r8a7791_pinmux_info;
902 #endif
903 #ifdef CONFIG_PINCTRL_PFC_R8A7792
904 if (model == SH_PFC_R8A7792)
905 priv->pfc.info = &r8a7792_pinmux_info;
906 #endif
907 #ifdef CONFIG_PINCTRL_PFC_R8A7793
908 if (model == SH_PFC_R8A7793)
909 priv->pfc.info = &r8a7793_pinmux_info;
910 #endif
911 #ifdef CONFIG_PINCTRL_PFC_R8A7794
912 if (model == SH_PFC_R8A7794)
913 priv->pfc.info = &r8a7794_pinmux_info;
914 #endif
915 #ifdef CONFIG_PINCTRL_PFC_R8A7795
916 if (model == SH_PFC_R8A7795)
917 priv->pfc.info = &r8a7795_pinmux_info;
918 #endif
919 #ifdef CONFIG_PINCTRL_PFC_R8A7796
920 if (model == SH_PFC_R8A7796)
921 priv->pfc.info = &r8a7796_pinmux_info;
922 #endif
923 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
924 if (model == SH_PFC_R8A774A1)
925 priv->pfc.info = &r8a774a1_pinmux_info;
926 #endif
927 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
928 if (model == SH_PFC_R8A774B1)
929 priv->pfc.info = &r8a774b1_pinmux_info;
930 #endif
931 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
932 if (model == SH_PFC_R8A774C0)
933 priv->pfc.info = &r8a774c0_pinmux_info;
934 #endif
935 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
936 if (model == SH_PFC_R8A774E1)
937 priv->pfc.info = &r8a774e1_pinmux_info;
938 #endif
939 #ifdef CONFIG_PINCTRL_PFC_R8A77965
940 if (model == SH_PFC_R8A77965)
941 priv->pfc.info = &r8a77965_pinmux_info;
942 #endif
943 #ifdef CONFIG_PINCTRL_PFC_R8A77970
944 if (model == SH_PFC_R8A77970)
945 priv->pfc.info = &r8a77970_pinmux_info;
946 #endif
947 #ifdef CONFIG_PINCTRL_PFC_R8A77980
948 if (model == SH_PFC_R8A77980)
949 priv->pfc.info = &r8a77980_pinmux_info;
950 #endif
951 #ifdef CONFIG_PINCTRL_PFC_R8A77990
952 if (model == SH_PFC_R8A77990)
953 priv->pfc.info = &r8a77990_pinmux_info;
954 #endif
955 #ifdef CONFIG_PINCTRL_PFC_R8A77995
956 if (model == SH_PFC_R8A77995)
957 priv->pfc.info = &r8a77995_pinmux_info;
958 #endif
959 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
960 if (model == SH_PFC_R8A779A0)
961 priv->pfc.info = &r8a779a0_pinmux_info;
962 #endif
963
964 priv->pmx.pfc = &priv->pfc;
965 sh_pfc_init_ranges(&priv->pfc);
966 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
967
968 return 0;
969 }
970
971 static const struct udevice_id sh_pfc_pinctrl_ids[] = {
972 #ifdef CONFIG_PINCTRL_PFC_R8A7790
973 {
974 .compatible = "renesas,pfc-r8a7790",
975 .data = SH_PFC_R8A7790,
976 },
977 #endif
978 #ifdef CONFIG_PINCTRL_PFC_R8A7791
979 {
980 .compatible = "renesas,pfc-r8a7791",
981 .data = SH_PFC_R8A7791,
982 },
983 #endif
984 #ifdef CONFIG_PINCTRL_PFC_R8A7792
985 {
986 .compatible = "renesas,pfc-r8a7792",
987 .data = SH_PFC_R8A7792,
988 },
989 #endif
990 #ifdef CONFIG_PINCTRL_PFC_R8A7793
991 {
992 .compatible = "renesas,pfc-r8a7793",
993 .data = SH_PFC_R8A7793,
994 },
995 #endif
996 #ifdef CONFIG_PINCTRL_PFC_R8A7794
997 {
998 .compatible = "renesas,pfc-r8a7794",
999 .data = SH_PFC_R8A7794,
1000 },
1001 #endif
1002 #ifdef CONFIG_PINCTRL_PFC_R8A7795
1003 {
1004 .compatible = "renesas,pfc-r8a7795",
1005 .data = SH_PFC_R8A7795,
1006 },
1007 #endif
1008 #ifdef CONFIG_PINCTRL_PFC_R8A7796
1009 {
1010 .compatible = "renesas,pfc-r8a7796",
1011 .data = SH_PFC_R8A7796,
1012 },
1013 #endif
1014 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
1015 {
1016 .compatible = "renesas,pfc-r8a774a1",
1017 .data = SH_PFC_R8A774A1,
1018 },
1019 #endif
1020 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
1021 {
1022 .compatible = "renesas,pfc-r8a774b1",
1023 .data = SH_PFC_R8A774B1,
1024 },
1025 #endif
1026 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
1027 {
1028 .compatible = "renesas,pfc-r8a774c0",
1029 .data = SH_PFC_R8A774C0,
1030 },
1031 #endif
1032 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
1033 {
1034 .compatible = "renesas,pfc-r8a774e1",
1035 .data = SH_PFC_R8A774E1,
1036 },
1037 #endif
1038 #ifdef CONFIG_PINCTRL_PFC_R8A77965
1039 {
1040 .compatible = "renesas,pfc-r8a77965",
1041 .data = SH_PFC_R8A77965,
1042 },
1043 #endif
1044 #ifdef CONFIG_PINCTRL_PFC_R8A77970
1045 {
1046 .compatible = "renesas,pfc-r8a77970",
1047 .data = SH_PFC_R8A77970,
1048 },
1049 #endif
1050 #ifdef CONFIG_PINCTRL_PFC_R8A77980
1051 {
1052 .compatible = "renesas,pfc-r8a77980",
1053 .data = SH_PFC_R8A77980,
1054 },
1055 #endif
1056 #ifdef CONFIG_PINCTRL_PFC_R8A77990
1057 {
1058 .compatible = "renesas,pfc-r8a77990",
1059 .data = SH_PFC_R8A77990,
1060 },
1061 #endif
1062 #ifdef CONFIG_PINCTRL_PFC_R8A77995
1063 {
1064 .compatible = "renesas,pfc-r8a77995",
1065 .data = SH_PFC_R8A77995,
1066 },
1067 #endif
1068 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
1069 {
1070 .compatible = "renesas,pfc-r8a779a0",
1071 .data = SH_PFC_R8A779A0,
1072 },
1073 #endif
1074
1075 { },
1076 };
1077
1078 U_BOOT_DRIVER(pinctrl_sh_pfc) = {
1079 .name = "sh_pfc_pinctrl",
1080 .id = UCLASS_PINCTRL,
1081 .of_match = sh_pfc_pinctrl_ids,
1082 .priv_auto = sizeof(struct sh_pfc_pinctrl_priv),
1083 .ops = &sh_pfc_pinctrl_ops,
1084 .probe = sh_pfc_pinctrl_probe,
1085 };
1086