1 /* ========================================================================== 2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ 3 * $Revision: #58 $ 4 * $Date: 2011/09/15 $ 5 * $Change: 1846647 $ 6 * 7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, 8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless 9 * otherwise expressly agreed to in writing between Synopsys and you. 10 * 11 * The Software IS NOT an item of Licensed Software or Licensed Product under 12 * any End User Software License Agreement or Agreement for Licensed Product 13 * with Synopsys or any supplement thereto. You are permitted to use and 14 * redistribute this Software in source and binary forms, with or without 15 * modification, provided that redistributions of source code must retain this 16 * notice. You may not view, use, disclose, copy or distribute this file or 17 * any information contained herein except pursuant to this license grant from 18 * Synopsys. If you do not agree with this notice, including the disclaimer 19 * below, then you are not authorized to use the Software. 20 * 21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 31 * DAMAGE. 32 * ========================================================================== */ 33 #if 1//ndef DWC_DEVICE_ONLY 34 #ifndef __DWC_HCD_H__ 35 #define __DWC_HCD_H__ 36 37 //#include "dwc_otg_os_dep.h" 38 #include "usb.h" 39 #include "dwc_otg_hcd_if.h" 40 #include "dwc_otg_core_if.h" 41 #include "dwc_list.h" 42 #include "dwc_otg_cil.h" 43 #undef DWC_HS_ELECT_TST 44 /** 45 * @file 46 * 47 * This file contains the structures, constants, and interfaces for 48 * the Host Contoller Driver (HCD). 49 * 50 * The Host Controller Driver (HCD) is responsible for translating requests 51 * from the USB Driver into the appropriate actions on the DWC_otg controller. 52 * It isolates the USBD from the specifics of the controller by providing an 53 * API to the USBD. 54 */ 55 56 struct dwc_otg_hcd_pipe_info { 57 uint8_t dev_addr; 58 uint8_t ep_num; 59 uint8_t pipe_type; 60 uint8_t pipe_dir; 61 uint16_t mps; 62 }; 63 64 struct dwc_otg_hcd_iso_packet_desc { 65 uint32_t offset; 66 uint32_t length; 67 uint32_t actual_length; 68 uint32_t status; 69 }; 70 71 struct dwc_otg_qtd; 72 73 struct dwc_otg_hcd_urb { 74 void *priv; 75 struct dwc_otg_qtd *qtd; 76 void *buf; 77 dwc_dma_t dma; 78 void *setup_packet; 79 dwc_dma_t setup_dma; 80 uint32_t length; 81 uint32_t actual_length; 82 uint32_t status; 83 uint32_t error_count; 84 uint32_t packet_count; 85 uint32_t flags; 86 uint16_t interval; 87 struct dwc_otg_hcd_pipe_info pipe_info; 88 struct dwc_otg_hcd_iso_packet_desc iso_descs[0]; 89 }; 90 91 extern _LONG_CALL_ 92 uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe); 93 94 extern _LONG_CALL_ 95 uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info 96 *pipe); 97 98 extern _LONG_CALL_ 99 uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe); 100 101 extern _LONG_CALL_ 102 uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info 103 *pipe); 104 105 extern _LONG_CALL_ 106 uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info 107 *pipe); 108 109 extern _LONG_CALL_ 110 uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info 111 *pipe); 112 113 extern _LONG_CALL_ 114 uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info 115 *pipe); 116 117 extern _LONG_CALL_ 118 uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info 119 *pipe); 120 121 extern _LONG_CALL_ 122 uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe); 123 124 extern _LONG_CALL_ 125 uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info 126 *pipe); 127 128 extern _LONG_CALL_ 129 void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe, 130 uint8_t devaddr, uint8_t ep_num, 131 uint8_t pipe_type, uint8_t pipe_dir, 132 uint16_t mps); 133 134 /** 135 * Phases for control transfers. 136 */ 137 typedef enum dwc_otg_control_phase { 138 DWC_OTG_CONTROL_SETUP, 139 DWC_OTG_CONTROL_DATA, 140 DWC_OTG_CONTROL_STATUS 141 } dwc_otg_control_phase_e; 142 143 /** Transaction types. */ 144 typedef enum dwc_otg_transaction_type { 145 DWC_OTG_TRANSACTION_NONE, 146 DWC_OTG_TRANSACTION_PERIODIC, 147 DWC_OTG_TRANSACTION_NON_PERIODIC, 148 DWC_OTG_TRANSACTION_ALL 149 } dwc_otg_transaction_type_e; 150 151 struct dwc_otg_qh; 152 153 /** 154 * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, 155 * interrupt, or isochronous transfer. A single QTD is created for each URB 156 * (of one of these types) submitted to the HCD. The transfer associated with 157 * a QTD may require one or multiple transactions. 158 * 159 * A QTD is linked to a Queue Head, which is entered in either the 160 * non-periodic or periodic schedule for execution. When a QTD is chosen for 161 * execution, some or all of its transactions may be executed. After 162 * execution, the state of the QTD is updated. The QTD may be retired if all 163 * its transactions are complete or if an error occurred. Otherwise, it 164 * remains in the schedule so more transactions can be executed later. 165 */ 166 typedef struct dwc_otg_qtd { 167 /** 168 * Determines the PID of the next data packet for the data phase of 169 * control transfers. Ignored for other transfer types.<br> 170 * One of the following values: 171 * - DWC_OTG_HC_PID_DATA0 172 * - DWC_OTG_HC_PID_DATA1 173 */ 174 uint8_t data_toggle; 175 176 /** Current phase for control transfers (Setup, Data, or Status). */ 177 dwc_otg_control_phase_e control_phase; 178 179 /** Keep track of the current split type 180 * for FS/LS endpoints on a HS Hub */ 181 uint8_t complete_split; 182 183 /** How many bytes transferred during SSPLIT OUT */ 184 uint32_t ssplit_out_xfer_count; 185 186 /** 187 * Holds the number of bus errors that have occurred for a transaction 188 * within this transfer. 189 */ 190 uint8_t error_count; 191 192 /** 193 * Index of the next frame descriptor for an isochronous transfer. A 194 * frame descriptor describes the buffer position and length of the 195 * data to be transferred in the next scheduled (micro)frame of an 196 * isochronous transfer. It also holds status for that transaction. 197 * The frame index starts at 0. 198 */ 199 uint16_t isoc_frame_index; 200 201 /** Position of the ISOC split on full/low speed */ 202 uint8_t isoc_split_pos; 203 204 /** Position of the ISOC split in the buffer for the current frame */ 205 uint16_t isoc_split_offset; 206 207 /** URB for this transfer */ 208 struct dwc_otg_hcd_urb *urb; 209 210 struct dwc_otg_qh *qh; 211 212 /** This list of QTDs */ 213 DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry; 214 215 /** Indicates if this QTD is currently processed by HW. */ 216 uint8_t in_process; 217 218 /** Number of DMA descriptors for this QTD */ 219 uint8_t n_desc; 220 221 /** 222 * Last activated frame(packet) index. 223 * Used in Descriptor DMA mode only. 224 */ 225 uint16_t isoc_frame_index_last; 226 227 } dwc_otg_qtd_t; 228 229 DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd); 230 231 /** 232 * A Queue Head (QH) holds the static characteristics of an endpoint and 233 * maintains a list of transfers (QTDs) for that endpoint. A QH structure may 234 * be entered in either the non-periodic or periodic schedule. 235 */ 236 typedef struct dwc_otg_qh { 237 /** 238 * Endpoint type. 239 * One of the following values: 240 * - UE_CONTROL 241 * - UE_BULK 242 * - UE_INTERRUPT 243 * - UE_ISOCHRONOUS 244 */ 245 uint8_t ep_type; 246 uint8_t ep_is_in; 247 248 /** wMaxPacketSize Field of Endpoint Descriptor. */ 249 uint16_t maxp; 250 251 /** 252 * Device speed. 253 * One of the following values: 254 * - DWC_OTG_EP_SPEED_LOW 255 * - DWC_OTG_EP_SPEED_FULL 256 * - DWC_OTG_EP_SPEED_HIGH 257 */ 258 uint8_t dev_speed; 259 260 /** 261 * Determines the PID of the next data packet for non-control 262 * transfers. Ignored for control transfers.<br> 263 * One of the following values: 264 * - DWC_OTG_HC_PID_DATA0 265 * - DWC_OTG_HC_PID_DATA1 266 */ 267 uint8_t data_toggle; 268 269 /** Ping state if 1. */ 270 uint8_t ping_state; 271 272 /** 273 * List of QTDs for this QH. 274 */ 275 struct dwc_otg_qtd_list qtd_list; 276 277 /** Host channel currently processing transfers for this QH. */ 278 struct dwc_hc *channel; 279 280 /** Full/low speed endpoint on high-speed hub requires split. */ 281 uint8_t do_split; 282 283 /** @name Periodic schedule information */ 284 /** @{ */ 285 286 /** Bandwidth in microseconds per (micro)frame. */ 287 uint16_t usecs; 288 289 /** Interval between transfers in (micro)frames. */ 290 uint16_t interval; 291 292 /** 293 * (micro)frame to initialize a periodic transfer. The transfer 294 * executes in the following (micro)frame. 295 */ 296 uint16_t sched_frame; 297 298 /** (micro)frame at which last start split was initialized. */ 299 uint16_t start_split_frame; 300 301 /** @} */ 302 303 /** 304 * Used instead of original buffer if 305 * it(physical address) is not dword-aligned. 306 */ 307 uint8_t *dw_align_buf; 308 dwc_dma_t dw_align_buf_dma; 309 310 /** Entry for QH in either the periodic or non-periodic schedule. */ 311 dwc_list_link_t qh_list_entry; 312 313 /** @name Descriptor DMA support */ 314 /** @{ */ 315 316 /** Descriptor List. */ 317 dwc_otg_host_dma_desc_t *desc_list; 318 319 /** Descriptor List physical address. */ 320 dwc_dma_t desc_list_dma; 321 322 /** 323 * Xfer Bytes array. 324 * Each element corresponds to a descriptor and indicates 325 * original XferSize size value for the descriptor. 326 */ 327 uint32_t *n_bytes; 328 329 /** Actual number of transfer descriptors in a list. */ 330 uint16_t ntd; 331 332 /** First activated isochronous transfer descriptor index. */ 333 uint8_t td_first; 334 /** Last activated isochronous transfer descriptor index. */ 335 uint8_t td_last; 336 337 /** @} */ 338 339 } dwc_otg_qh_t; 340 341 DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); 342 343 /** 344 * This structure holds the state of the HCD, including the non-periodic and 345 * periodic schedules. 346 */ 347 struct dwc_otg_hcd { 348 /** The DWC otg device pointer */ 349 struct dwc_otg_device *otg_dev; 350 /** DWC OTG Core Interface Layer */ 351 dwc_otg_core_if_t *core_if; 352 353 /** Function HCD driver callbacks */ 354 struct dwc_otg_hcd_function_ops *fops; 355 356 /** Internal DWC HCD Flags */ 357 volatile union dwc_otg_hcd_internal_flags { 358 uint32_t d32; 359 struct { 360 unsigned port_connect_status_change:1; 361 unsigned port_connect_status:1; 362 unsigned port_reset_change:1; 363 unsigned port_enable_change:1; 364 unsigned port_suspend_change:1; 365 unsigned port_over_current_change:1; 366 unsigned port_l1_change:1; 367 unsigned reserved:26; 368 } b; 369 } flags; 370 371 /** 372 * Inactive items in the non-periodic schedule. This is a list of 373 * Queue Heads. Transfers associated with these Queue Heads are not 374 * currently assigned to a host channel. 375 */ 376 dwc_list_link_t non_periodic_sched_inactive; 377 378 /** 379 * Active items in the non-periodic schedule. This is a list of 380 * Queue Heads. Transfers associated with these Queue Heads are 381 * currently assigned to a host channel. 382 */ 383 dwc_list_link_t non_periodic_sched_active; 384 385 /** 386 * Pointer to the next Queue Head to process in the active 387 * non-periodic schedule. 388 */ 389 dwc_list_link_t *non_periodic_qh_ptr; 390 391 /** 392 * Inactive items in the periodic schedule. This is a list of QHs for 393 * periodic transfers that are _not_ scheduled for the next frame. 394 * Each QH in the list has an interval counter that determines when it 395 * needs to be scheduled for execution. This scheduling mechanism 396 * allows only a simple calculation for periodic bandwidth used (i.e. 397 * must assume that all periodic transfers may need to execute in the 398 * same frame). However, it greatly simplifies scheduling and should 399 * be sufficient for the vast majority of OTG hosts, which need to 400 * connect to a small number of peripherals at one time. 401 * 402 * Items move from this list to periodic_sched_ready when the QH 403 * interval counter is 0 at SOF. 404 */ 405 dwc_list_link_t periodic_sched_inactive; 406 407 /** 408 * List of periodic QHs that are ready for execution in the next 409 * frame, but have not yet been assigned to host channels. 410 * 411 * Items move from this list to periodic_sched_assigned as host 412 * channels become available during the current frame. 413 */ 414 dwc_list_link_t periodic_sched_ready; 415 416 /** 417 * List of periodic QHs to be executed in the next frame that are 418 * assigned to host channels. 419 * 420 * Items move from this list to periodic_sched_queued as the 421 * transactions for the QH are queued to the DWC_otg controller. 422 */ 423 dwc_list_link_t periodic_sched_assigned; 424 425 /** 426 * List of periodic QHs that have been queued for execution. 427 * 428 * Items move from this list to either periodic_sched_inactive or 429 * periodic_sched_ready when the channel associated with the transfer 430 * is released. If the interval for the QH is 1, the item moves to 431 * periodic_sched_ready because it must be rescheduled for the next 432 * frame. Otherwise, the item moves to periodic_sched_inactive. 433 */ 434 dwc_list_link_t periodic_sched_queued; 435 436 /** 437 * Total bandwidth claimed so far for periodic transfers. This value 438 * is in microseconds per (micro)frame. The assumption is that all 439 * periodic transfers may occur in the same (micro)frame. 440 */ 441 uint16_t periodic_usecs; 442 443 /** 444 * Frame number read from the core at SOF. The value ranges from 0 to 445 * DWC_HFNUM_MAX_FRNUM. 446 */ 447 uint16_t frame_number; 448 449 /** 450 * Count of periodic QHs, if using several eps. For SOF enable/disable. 451 */ 452 uint16_t periodic_qh_count; 453 454 /** 455 * Free host channels in the controller. This is a list of 456 * dwc_hc_t items. 457 */ 458 struct hc_list free_hc_list; 459 /** 460 * Number of host channels assigned to periodic transfers. Currently 461 * assuming that there is a dedicated host channel for each periodic 462 * transaction and at least one host channel available for 463 * non-periodic transactions. 464 */ 465 int periodic_channels; 466 467 /** 468 * Number of host channels assigned to non-periodic transfers. 469 */ 470 int non_periodic_channels; 471 472 /** 473 * Array of pointers to the host channel descriptors. Allows accessing 474 * a host channel descriptor given the host channel number. This is 475 * useful in interrupt handlers. 476 */ 477 struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS]; 478 479 /** 480 * Buffer to use for any data received during the status phase of a 481 * control transfer. Normally no data is transferred during the status 482 * phase. This buffer is used as a bit bucket. 483 */ 484 uint8_t *status_buf; 485 486 /** 487 * DMA address for status_buf. 488 */ 489 dma_addr_t status_buf_dma; 490 #define DWC_OTG_HCD_STATUS_BUF_SIZE 64 491 492 /** 493 * Connection timer. An OTG host must display a message if the device 494 * does not connect. Started when the VBus power is turned on via 495 * sysfs attribute "buspower". 496 */ 497 dwc_timer_t *conn_timer; 498 499 /* Tasket to do a reset */ 500 //dwc_tasklet_t *reset_tasklet; 501 502 /* */ 503 dwc_spinlock_t *lock; 504 505 /** 506 * Private data that could be used by OS wrapper. 507 */ 508 void *priv; 509 510 uint8_t otg_port; 511 512 /** Frame List */ 513 uint32_t *frame_list; 514 515 /** Frame List DMA address */ 516 dma_addr_t frame_list_dma; 517 518 #ifdef OTGDEBUG 519 uint32_t frrem_samples; 520 uint64_t frrem_accum; 521 522 uint32_t hfnum_7_samples_a; 523 uint64_t hfnum_7_frrem_accum_a; 524 uint32_t hfnum_0_samples_a; 525 uint64_t hfnum_0_frrem_accum_a; 526 uint32_t hfnum_other_samples_a; 527 uint64_t hfnum_other_frrem_accum_a; 528 529 uint32_t hfnum_7_samples_b; 530 uint64_t hfnum_7_frrem_accum_b; 531 uint32_t hfnum_0_samples_b; 532 uint64_t hfnum_0_frrem_accum_b; 533 uint32_t hfnum_other_samples_b; 534 uint64_t hfnum_other_frrem_accum_b; 535 #endif 536 }; 537 538 /** @name Transaction Execution Functions */ 539 /** @{ */ 540 extern _LONG_CALL_ dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t 541 * hcd); 542 extern _LONG_CALL_ void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, 543 dwc_otg_transaction_type_e tr_type); 544 545 /** @} */ 546 547 /** @name Interrupt Handler Functions */ 548 /** @{ */ 549 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); 550 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd); 551 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * 552 dwc_otg_hcd); 553 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * 554 dwc_otg_hcd); 555 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * 556 dwc_otg_hcd); 557 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t * 558 dwc_otg_hcd); 559 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd); 560 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t * 561 dwc_otg_hcd); 562 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd); 563 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd); 564 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, 565 uint32_t num); 566 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd); 567 extern _LONG_CALL_ int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t * 568 dwc_otg_hcd); 569 /** @} */ 570 571 /** @name Schedule Queue Functions */ 572 /** @{ */ 573 574 /* Implemented in dwc_otg_hcd_queue.c */ 575 extern _LONG_CALL_ dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, 576 dwc_otg_hcd_urb_t * urb, int atomic_alloc); 577 extern _LONG_CALL_ void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); 578 extern _LONG_CALL_ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); 579 extern _LONG_CALL_ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); 580 extern _LONG_CALL_ void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, 581 int sched_csplit); 582 583 /** Remove and free a QH */ 584 extern _LONG_CALL_ 585 void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd, 586 dwc_otg_qh_t * qh); 587 588 /** Allocates memory for a QH structure. 589 * @return Returns the memory allocate or NULL on error. */ 590 extern _LONG_CALL_ 591 dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc); 592 593 extern _LONG_CALL_ dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, 594 int atomic_alloc); 595 extern _LONG_CALL_ void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb); 596 extern _LONG_CALL_ int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd, 597 dwc_otg_qh_t ** qh, int atomic_alloc); 598 599 /** Allocates memory for a QTD structure. 600 * @return Returns the memory allocate or NULL on error. */ 601 extern _LONG_CALL_ 602 dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc); 603 604 /** Frees the memory for a QTD structure. QTD should already be removed from 605 * list. 606 * @param qtd QTD to free.*/ 607 extern _LONG_CALL_ 608 void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd); 609 610 /** Removes a QTD from list. 611 * @param hcd HCD instance. 612 * @param qtd QTD to remove from list. 613 * @param qh QTD belongs to. 614 */ 615 extern _LONG_CALL_ 616 void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd, 617 dwc_otg_qtd_t * qtd, 618 dwc_otg_qh_t * qh); 619 620 /** Remove and free a QTD 621 * Need to disable IRQ and hold hcd lock while calling this function out of 622 * interrupt servicing chain */ 623 extern _LONG_CALL_ 624 void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd, 625 dwc_otg_qtd_t * qtd, 626 dwc_otg_qh_t * qh); 627 628 /** @} */ 629 630 /** @name Descriptor DMA Supporting Functions */ 631 /** @{ */ 632 633 extern _LONG_CALL_ void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); 634 extern _LONG_CALL_ void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, 635 dwc_hc_t * hc, 636 dwc_otg_hc_regs_t * hc_regs, 637 dwc_otg_halt_status_e halt_status); 638 639 extern _LONG_CALL_ int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); 640 extern _LONG_CALL_ void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); 641 extern _LONG_CALL_ void reset_tasklet_func(void *data); 642 643 /** @} */ 644 645 /** @name Internal Functions */ 646 /** @{ */ 647 extern _LONG_CALL_ dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb); 648 /** @} */ 649 650 #ifdef CONFIG_USB_DWC_OTG_LPM 651 extern _LONG_CALL_ int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, 652 uint8_t devaddr); 653 extern _LONG_CALL_ void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd); 654 #endif 655 656 /** Gets the QH that contains the list_head */ 657 #define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) 658 659 /** Gets the QTD that contains the list_head */ 660 #define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) 661 662 /** Check if QH is non-periodic */ 663 #define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \ 664 (_qh_ptr_->ep_type == UE_CONTROL)) 665 666 /** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ 667 #define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) 668 669 /** Packet size for any kind of endpoint descriptor */ 670 #define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 671 672 /** 673 * Returns true if _frame1 is less than or equal to _frame2. The comparison is 674 * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the 675 * frame number when the max frame number is reached. 676 */ 677 extern _LONG_CALL_ 678 int dwc_frame_num_le(uint16_t frame1, uint16_t frame2); 679 680 /** 681 * Returns true if _frame1 is greater than _frame2. The comparison is done 682 * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame 683 * number when the max frame number is reached. 684 */ 685 extern _LONG_CALL_ 686 int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2); 687 688 /** 689 * Increments _frame by the amount specified by _inc. The addition is done 690 * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. 691 */ 692 extern _LONG_CALL_ 693 uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc); 694 695 extern _LONG_CALL_ 696 uint16_t dwc_full_frame_num(uint16_t frame); 697 698 extern _LONG_CALL_ 699 uint16_t dwc_micro_frame_num(uint16_t frame); 700 701 extern _LONG_CALL_ void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, 702 dwc_otg_hc_regs_t * hc_regs, 703 dwc_otg_qtd_t * qtd); 704 705 extern _LONG_CALL_ void dwc_hcd_data_init(void); 706 #ifdef OTGDEBUG 707 /** 708 * Macro to sample the remaining PHY clocks left in the current frame. This 709 * may be used during debugging to determine the average time it takes to 710 * execute sections of code. There are two possible sample points, "a" and 711 * "b", so the _letter argument must be one of these values. 712 * 713 * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For 714 * example, "cat /sys/devices/lm0/hcd_frrem". 715 */ 716 #define dwc_sample_frrem(_hcd, _qh, _letter) \ 717 { \ 718 hfnum_data_t hfnum; \ 719 dwc_otg_qtd_t *qtd; \ 720 qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ 721 if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ 722 hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ 723 switch (hfnum.b.frnum & 0x7) { \ 724 case 7: \ 725 _hcd->hfnum_7_samples_##_letter++; \ 726 _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ 727 break; \ 728 case 0: \ 729 _hcd->hfnum_0_samples_##_letter++; \ 730 _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ 731 break; \ 732 default: \ 733 _hcd->hfnum_other_samples_##_letter++; \ 734 _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ 735 break; \ 736 } \ 737 } \ 738 } 739 #else 740 #define dwc_sample_frrem(_hcd, _qh, _letter) 741 #endif 742 #endif 743 #endif /* DWC_DEVICE_ONLY */ 744