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/arm-trusted-firmware-2.8.0/lib/compiler-rt/builtins/
A Dint_math.h23 #define __has_builtin(x) 0 argument
38 #define crt_isfinite(x) _finite((x)) argument
39 #define crt_isinf(x) !_finite((x)) argument
40 #define crt_isnan(x) _isnan((x)) argument
56 #define crt_isinf(x) __builtin_isinf((x)) argument
71 #define crt_fabs(x) fabs((x)) argument
72 #define crt_fabsf(x) fabsf((x)) argument
73 #define crt_fabsl(x) fabs((x)) argument
75 #define crt_fabs(x) __builtin_fabs((x)) argument
81 #define crt_fmaxl(x, y) __max((x), (y)) argument
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/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/D3/
A Dpfc_init_d3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) argument
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) argument
314 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) argument
315 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) argument
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/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/H3/
A Dpfc_init_h3_v1.c166 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
172 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
173 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
277 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
278 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
279 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) argument
285 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) argument
309 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) argument
310 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) argument
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A Dpfc_init_h3_v2.c168 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
173 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
174 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
175 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
279 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
280 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
281 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) argument
287 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) argument
311 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) argument
312 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) argument
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/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/M3N/
A Dpfc_init_m3n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
283 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) argument
289 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) argument
313 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) argument
314 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) argument
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/arm-trusted-firmware-2.8.0/drivers/renesas/rzg/pfc/G2H/
A Dpfc_init_g2h.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
283 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) argument
289 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) argument
313 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) argument
314 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) argument
[all …]
/arm-trusted-firmware-2.8.0/drivers/renesas/rzg/pfc/G2N/
A Dpfc_init_g2n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U) argument
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U) argument
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U) argument
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U) argument
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
281 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
282 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
[all …]
/arm-trusted-firmware-2.8.0/drivers/renesas/rcar/pfc/M3/
A Dpfc_init_m3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) argument
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) argument
314 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) argument
315 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) argument
[all …]
/arm-trusted-firmware-2.8.0/drivers/renesas/rzg/pfc/G2M/
A Dpfc_init_g2m.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U) argument
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U) argument
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U) argument
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U) argument
282 #define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U) argument
283 #define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U) argument
284 #define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U) argument
290 #define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U) argument
314 #define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U) argument
315 #define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U) argument
[all …]
/arm-trusted-firmware-2.8.0/include/lib/libc/
A Dendian.h45 #define bswap16(x) __bswap16(x) argument
46 #define bswap32(x) __bswap32(x) argument
47 #define bswap64(x) __bswap64(x) argument
54 #define htobe16(x) bswap16((x)) argument
55 #define htobe32(x) bswap32((x)) argument
56 #define htobe64(x) bswap64((x)) argument
61 #define be16toh(x) bswap16((x)) argument
62 #define be32toh(x) bswap32((x)) argument
63 #define be64toh(x) bswap64((x)) argument
71 #define htole16(x) bswap16((x)) argument
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A Dcdefs.h16 #define __aligned(x) __attribute__((__aligned__(x))) argument
17 #define __section(x) __attribute__((__section__(x))) argument
35 #define __STRING(x) #x argument
36 #define __XSTRING(x) __STRING(x) argument
/arm-trusted-firmware-2.8.0/plat/intel/soc/common/drivers/qspi/
A Dcadence_qspi.h25 #define CAD_QSPI_BANK_ADDR(x) ((x) >> 24) argument
34 #define CAD_QSPI_CFG_CS(x) (((x) << 11)) argument
44 #define CAD_QSPI_DELAY_CSSOT(x) (((x) & 0xff) << 0) argument
45 #define CAD_QSPI_DELAY_CSEOT(x) (((x) & 0xff) << 8) argument
47 #define CAD_QSPI_DELAY_CSDA(x) (((x) & 0xff) << 24) argument
50 #define CAD_QSPI_DEVSZ_ADDR_BYTES(x) ((x) << 0) argument
51 #define CAD_QSPI_DEVSZ_BYTES_PER_PAGE(x) ((x) << 4) argument
56 #define CAD_QSPI_DEV_OPCODE(x) (((x) & 0xff) << 0) argument
97 #define CAD_QSPI_SELCLKPHASE(x) (((x) & 1) << 2) argument
98 #define CAD_QSPI_SELCLKPOL(x) (((x) & 1) << 1) argument
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/arm-trusted-firmware-2.8.0/include/lib/libc/aarch32/
A Dendian_.h68 #define __ntohl(x) ((uint32_t)(x)) argument
69 #define __ntohs(x) ((uint16_t)(x)) argument
70 #define __htonl(x) ((uint32_t)(x)) argument
71 #define __htons(x) ((uint16_t)(x)) argument
75 #define __ntohl(x) (__bswap32(x)) argument
121 #define __bswap32_constant(x) \ argument
127 #define __bswap16_constant(x) \ argument
131 #define __bswap16(x) \ argument
136 #define __bswap32(x) \ argument
142 #define __bswap16(x) __bswap16_var(x) argument
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/arm-trusted-firmware-2.8.0/include/lib/libfdt/
A Dlibfdt_env.h29 #define EXTRACT_BYTE(x, n) ((unsigned long long)((uint8_t *)&x)[n]) argument
30 #define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1)) argument
31 #define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \ argument
33 #define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \ argument
38 static inline uint16_t fdt16_to_cpu(fdt16_t x) in fdt16_to_cpu()
42 static inline fdt16_t cpu_to_fdt16(uint16_t x) in cpu_to_fdt16()
47 static inline uint32_t fdt32_to_cpu(fdt32_t x) in fdt32_to_cpu()
51 static inline fdt32_t cpu_to_fdt32(uint32_t x) in cpu_to_fdt32()
56 static inline uint64_t fdt64_to_cpu(fdt64_t x) in fdt64_to_cpu()
60 static inline fdt64_t cpu_to_fdt64(uint64_t x) in cpu_to_fdt64()
/arm-trusted-firmware-2.8.0/include/lib/libc/aarch64/
A Dendian_.h63 #define __ntohl(x) (__bswap32(x)) argument
64 #define __ntohs(x) (__bswap16(x)) argument
65 #define __htonl(x) (__bswap32(x)) argument
66 #define __htons(x) (__bswap16(x)) argument
69 __bswap64(uint64_t x) in __bswap64()
103 #define __bswap32_constant(x) \ argument
109 #define __bswap16_constant(x) \ argument
113 #define __bswap16(x) \ argument
118 #define __bswap32(x) \ argument
124 #define __bswap16(x) __bswap16_var(x) argument
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/arm-trusted-firmware-2.8.0/plat/intel/soc/stratix10/include/
A Ds10_clock_manager.h22 #define ALT_CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) argument
23 #define ALT_CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) argument
24 #define ALT_CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00000200) >> 9) argument
46 #define ALT_CLKMGR_MAINPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) argument
48 #define ALT_CLKMGR_MAINPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
50 #define ALT_CLKMGR_MAINPLL_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000000ff) argument
51 #define ALT_CLKMGR_MAINPLL_VCOCALIB_MSCNT_SET(x) (((x) << 9) & 0x0001fe00) argument
53 #define ALT_CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) argument
80 #define ALT_CLKMGR_PERPLL_FDBCK_MDIV(x) (((x) & 0xff000000) >> 24) argument
83 #define ALT_CLKMGR_PERPLL_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
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A Ds10_memory_controller.h21 #define S10_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) argument
37 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) argument
38 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) argument
39 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) argument
40 #define IOHMC_DRAMADDRW_BANK_GRP_ADDR_WIDTH(x) (((x) & 0x0000c000) >> 14) argument
41 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) argument
43 #define S10_MPFE_DDR(x) (0xf8000000 + x) argument
56 #define S10_MPFE_DDR_MAIN_SCHED_DDRCONF_SET(x) (((x) << 0) & 0x0000001f) argument
64 #define S10_MPFE_HMC_ADP(x) (0xf8011000 + (x)) argument
68 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) argument
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/arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/
A Dimx8m_csu.h26 #define CSLx_REG(x) (IMX_CSU_BASE + ((x) / 2) * 4) argument
27 #define CSLx_LOCK(x) ((0x1 << (((x) % 2) * 16 + 8))) argument
28 #define CSLx_CFG(x, n) ((x) << (((n) % 2) * 16)) argument
30 #define CSU_HP_REG(x) (IMX_CSU_BASE + ((x) / 16) * 4 + 0x200) argument
31 #define CSU_HP_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) argument
32 #define CSU_HP_CFG(x, n) ((x) << (((n) % 16) * 2)) argument
34 #define CSU_SA_REG(x) (IMX_CSU_BASE + 0x218) argument
35 #define CSU_SA_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) argument
36 #define CSU_SA_CFG(x, n) ((x) << (((n) % 16) * 2)) argument
39 #define CSU_HPCONTROL_LOCK(x) ((0x1 << (((x) % 16) * 2 + 1))) argument
[all …]
/arm-trusted-firmware-2.8.0/plat/intel/soc/agilex/include/
A Dagilex_memory_controller.h23 #define AGX_MPFE_IOHMC_CALTIMING9_ACT_TO_ACT(x) (((x) & 0x000000ff) >> 0) argument
38 #define IOHMC_DRAMADDRW_COL_ADDR_WIDTH(x) (((x) & 0x0000001f) >> 0) argument
39 #define IOHMC_DRAMADDRW_ROW_ADDR_WIDTH(x) (((x) & 0x000003e0) >> 5) argument
40 #define IOHMC_DRAMADDRW_CS_ADDR_WIDTH(x) (((x) & 0x00070000) >> 16) argument
42 #define IOHMC_DRAMADDRW_BANK_ADDR_WIDTH(x) (((x) & 0x00003c00) >> 10) argument
44 #define AGX_MPFE_DDR(x) (0xf8000000 + x) argument
65 #define AGX_MPFE_HMC_ADP(x) (0xf8011000 + (x)) argument
69 #define HMC_ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x00000003) >> 0) argument
99 #define ADP_DDRIOCTRL_IO_SIZE(x) (((x) & 0x3) >> 0) argument
105 #define AGX_MPFE_IOHMC_REG_DRAMTIMING0_CFG_TCL(x) (((x) & 0x7f) >> 0) argument
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A Dagilex_clock_manager.h80 #define CLKMGR_STAT_BUSY(x) (((x) & 0x00000001) >> 0) argument
81 #define CLKMGR_STAT_MAINPLLLOCKED(x) (((x) & 0x00000100) >> 8) argument
82 #define CLKMGR_STAT_PERPLLLOCKED(x) (((x) & 0x00010000) >> 16) argument
93 #define CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(x) (((x) << 0) & 0x0000ffff) argument
99 #define CLKMGR_PSRC(x) (((x) & 0x00030000) >> 16) argument
107 #define CLKMGR_PLLM_MDIV(x) ((x) & 0x000003ff) argument
111 #define CLKMGR_PLLGLOB_REFCLKDIV(x) (((x) & 0x00003f00) >> 8) argument
112 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) argument
113 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) argument
115 #define CLKMGR_VCOCALIB_HSCNT_SET(x) (((x) << 0) & 0x000003ff) argument
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/arm-trusted-firmware-2.8.0/plat/intel/soc/common/drivers/ccu/
A Dncore_ccu.h77 #define DIRECTORY_UNIT(x, reg) (NCORE_CCU_DIR(reg)\ argument
79 #define COH_AGENT_UNIT(x, reg) (NCORE_CCU_CAI(reg)\ argument
85 #define CSUIDR_NUM_CMI(x) (((x) & 0x3f000000) >> 24) argument
86 #define CSUIDR_NUM_DIR(x) (((x) & 0x003f0000) >> 16) argument
87 #define CSUIDR_NUM_NCB(x) (((x) & 0x00003f00) >> 8) argument
88 #define CSUIDR_NUM_CAI(x) (((x) & 0x0000007f) >> 0) argument
90 #define CSIDR_NUM_SF(x) (((x) & 0x007c0000) >> 18) argument
92 #define SNOOP_FILTER_ID(x) (((x) << 16)) argument
94 #define CACHING_AGENT_BIT(x) (((x) & 0x08000) >> 15) argument
95 #define CACHING_AGENT_TYPE(x) (((x) & 0xf0000) >> 16) argument
/arm-trusted-firmware-2.8.0/drivers/nxp/flexspi/nor/
A Dfspi.h163 #define FSPI_MCR0_RXCLKSRC(x) ((x) << 4) argument
164 #define FSPI_MCR0_END_CFG(x) ((x) << 2) argument
183 #define FSPI_MCR1_AHB_TIMEOUT(x) (x) argument
276 #define FSPI_FLSHXCR1_TCSS(x) (x) argument
300 #define FSPI_IPCR1_IDATSZ(x) (x) argument
333 #define FSPI_IPRXFCR_WMRK(x) ((x) << 2) argument
347 #define FSPI_STS0_DLPHB(x) ((x) << 8) argument
348 #define FSPI_STS0_DLPHA(x) ((x) << 4) argument
357 #define FSPI_STS1_AHB_ERRID(x) (x) argument
366 #define FSPI_IPRXFSTS_FILL(x) (x) argument
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/arm-trusted-firmware-2.8.0/include/lib/libc/sys/
A Dcdefs.h49 #define __has_attribute(x) 0 argument
55 #define __has_feature(x) 0 argument
58 #define __has_include(x) 0 argument
61 #define __has_builtin(x) 0 argument
167 #define __CONCAT(x,y) x/**/y argument
168 #define __STRING(x) "x" argument
226 #define __alloc_size(x) argument
227 #define __alloc_size2(n, x) argument
232 #define __alloc_align(x) argument
339 #define __min_size(x) (x) argument
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/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t210/drivers/se/
A Dse_private.h53 #define SE_STATUS(x) \ argument
85 #define SE_CONFIG_ENC_ALG(x) \ argument
93 #define SE_CONFIG_DEC_ALG(x) \ argument
107 #define SE_CONFIG_DST(x) \ argument
127 #define SE_CONFIG_ENC_MODE(x)\ argument
147 #define SE_CONFIG_DEC_MODE(x)\ argument
303 #define SE_OPERATION(x) \ argument
429 #define SE_TZRAM_OP_BUSY(x) \ argument
437 #define SE_TZRAM_OP_REQ(x) \ argument
448 #define SE_INT_OP_DONE(x) \ argument
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/arm-trusted-firmware-2.8.0/include/drivers/st/
A Dstm32mp_ram.h13 #define PARAM(x, y) \ argument
20 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) argument
21 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) argument

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