1STMicroelectronics STM32MP1 2=========================== 3 4STM32MP1 is a microprocessor designed by STMicroelectronics 5based on Arm Cortex-A7. 6It is an Armv7-A platform, using dedicated code from TF-A. 7More information can be found on `STM32MP1 Series`_ page. 8 9 10STM32MP1 Versions 11----------------- 12 13There are 2 variants for STM32MP1: STM32MP13 and STM32MP15 14 15STM32MP13 Versions 16~~~~~~~~~~~~~~~~~~ 17The STM32MP13 series is available in 3 different lines which are pin-to-pin compatible: 18 19- STM32MP131: Single Cortex-A7 core 20- STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1 21- STM32MP135: STM32MP133 + DCMIPP, LTDC 22 23Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: 24 25- A Cortex-A7 @ 650 MHz 26- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz 27- D Cortex-A7 @ 900 MHz 28- F Secure Boot + HW Crypto + Cortex-A7 @ 900 MHz 29 30STM32MP15 Versions 31~~~~~~~~~~~~~~~~~~ 32The STM32MP15 series is available in 3 different lines which are pin-to-pin compatible: 33 34- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD 35- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD 36- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz 37 38Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option: 39 40- A Basic + Cortex-A7 @ 650 MHz 41- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz 42- D Basic + Cortex-A7 @ 800 MHz 43- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz 44 45The `STM32MP1 part number codification`_ page gives more information about part numbers. 46 47Design 48------ 49The STM32MP1 resets in the ROM code of the Cortex-A7. 50The primary boot core (core 0) executes the boot sequence while 51secondary boot core (core 1) is kept in a holding pen loop. 52The ROM code boot sequence loads the TF-A binary image from boot device 53to embedded SRAM. 54 55The TF-A image must be properly formatted with a STM32 header structure 56for ROM code is able to load this image. 57Tool stm32image can be used to prepend this header to the generated TF-A binary. 58 59Boot with FIP 60~~~~~~~~~~~~~ 61The use of FIP is now the recommended way to boot STM32MP1 platform. 62Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are 63inside the FIP binary: BL32 (SP_min or OP-TEE), U-Boot and their respective 64device tree blobs. 65 66 67Memory mapping 68~~~~~~~~~~~~~~ 69 70:: 71 72 0x00000000 +-----------------+ 73 | | ROM 74 0x00020000 +-----------------+ 75 | | 76 | ... | 77 | | 78 0x2FFC0000 +-----------------+ \ 79 | BL32 DTB | | 80 0x2FFC5000 +-----------------+ | 81 | BL32 | | 82 0x2FFDF000 +-----------------+ | 83 | ... | | 84 0x2FFE3000 +-----------------+ | 85 | BL2 DTB | | Embedded SRAM 86 0x2FFEA000 +-----------------+ | 87 | BL2 | | 88 0x2FFFF000 +-----------------+ | 89 | SCMI mailbox | | 90 0x30000000 +-----------------+ / 91 | | 92 | ... | 93 | | 94 0x40000000 +-----------------+ 95 | | 96 | | Devices 97 | | 98 0xC0000000 +-----------------+ \ 99 | | | 100 0xC0100000 +-----------------+ | 101 | BL33 | | Non-secure RAM (DDR) 102 | ... | | 103 | | | 104 0xFFFFFFFF +-----------------+ / 105 106 107Boot sequence 108~~~~~~~~~~~~~ 109 110ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot) 111 112or if Op-TEE is used: 113 114ROM code -> BL2 (compiled with BL2_AT_EL3) -> OP-TEE -> BL33 (U-Boot) 115 116 117Build Instructions 118------------------ 119Boot media(s) supported by BL2 must be specified in the build command. 120Available storage medias are: 121 122- ``STM32MP_SDMMC`` 123- ``STM32MP_EMMC`` 124- ``STM32MP_RAW_NAND`` 125- ``STM32MP_SPI_NAND`` 126- ``STM32MP_SPI_NOR`` 127 128Serial boot devices: 129 130- ``STM32MP_UART_PROGRAMMER`` 131- ``STM32MP_USB_PROGRAMMER`` 132 133 134Other configuration flags: 135 136- | ``DTB_FILE_NAME``: to precise board device-tree blob to be used. 137 | Default: stm32mp157c-ev1.dtb 138- | ``DWL_BUFFER_BASE``: the 'serial boot' load address of FIP, 139 | default location (end of the first 128MB) is used when absent 140- | ``STM32MP_EARLY_CONSOLE``: to enable early traces before clock driver is setup. 141 | Default: 0 (disabled) 142- | ``STM32MP_RECONFIGURE_CONSOLE``: to re-configure crash console (especially after BL2). 143 | Default: 0 (disabled) 144- | ``STM32MP_UART_BAUDRATE``: to select UART baud rate. 145 | Default: 115200 146- | ``STM32_TF_VERSION``: to manage BL2 monotonic counter. 147 | Default: 0 148- | ``STM32MP13``: to select STM32MP13 variant configuration. 149 | Default: 0 150- | ``STM32MP15``: to select STM32MP15 variant configuration. 151 | Default: 1 152 153 154Boot with FIP 155~~~~~~~~~~~~~ 156You need to build BL2, BL32 (SP_min or OP-TEE) and BL33 (U-Boot) before building FIP binary. 157 158U-Boot 159______ 160 161.. code:: bash 162 163 cd <u-boot_directory> 164 make stm32mp15_trusted_defconfig 165 make DEVICE_TREE=stm32mp157c-ev1 all 166 167OP-TEE (optional) 168_________________ 169 170.. code:: bash 171 172 cd <optee_directory> 173 make CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm PLATFORM=stm32mp1 \ 174 CFG_EMBED_DTB_SOURCE_FILE=stm32mp157c-ev1.dts 175 176 177TF-A BL32 (SP_min) 178__________________ 179If you choose not to use OP-TEE, you can use TF-A SP_min. 180To build TF-A BL32, and its device tree file: 181 182.. code:: bash 183 184 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ 185 AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-ev1.dtb bl32 dtbs 186 187TF-A BL2 188________ 189To build TF-A BL2 with its STM32 header for SD-card boot: 190 191.. code:: bash 192 193 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ 194 DTB_FILE_NAME=stm32mp157c-ev1.dtb STM32MP_SDMMC=1 195 196For other boot devices, you have to replace STM32MP_SDMMC in the previous command 197with the desired device flag. 198 199This BL2 is independent of the BL32 used (SP_min or OP-TEE) 200 201 202FIP 203___ 204With BL32 SP_min: 205 206.. code:: bash 207 208 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ 209 AARCH32_SP=sp_min \ 210 DTB_FILE_NAME=stm32mp157c-ev1.dtb \ 211 BL33=<u-boot_directory>/u-boot-nodtb.bin \ 212 BL33_CFG=<u-boot_directory>/u-boot.dtb \ 213 fip 214 215With OP-TEE: 216 217.. code:: bash 218 219 make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 \ 220 AARCH32_SP=optee \ 221 DTB_FILE_NAME=stm32mp157c-ev1.dtb \ 222 BL33=<u-boot_directory>/u-boot-nodtb.bin \ 223 BL33_CFG=<u-boot_directory>/u-boot.dtb \ 224 BL32=<optee_directory>/tee-header_v2.bin \ 225 BL32_EXTRA1=<optee_directory>/tee-pager_v2.bin 226 BL32_EXTRA2=<optee_directory>/tee-pageable_v2.bin 227 fip 228 229Trusted Boot Board 230__________________ 231 232.. code:: shell 233 234 tools/cert_create/cert_create -n --rot-key "build/stm32mp1/debug/rot_key.pem" \ 235 --tfw-nvctr 0 \ 236 --ntfw-nvctr 0 \ 237 --key-alg ecdsa --hash-alg sha256 \ 238 --trusted-key-cert build/stm32mp1/cert_images/trusted-key-cert.key-crt \ 239 --tos-fw <optee_directory>/tee-header_v2.bin \ 240 --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ 241 --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ 242 --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \ 243 --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \ 244 --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ 245 --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ 246 --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \ 247 --hw-config <u-boot_directory>/u-boot.dtb \ 248 --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \ 249 --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt 250 251 tools/fiptool/fiptool create --tos-fw <optee_directory>/tee-header_v2.bin \ 252 --tos-fw-extra1 <optee_directory>/tee-pager_v2.bin \ 253 --tos-fw-extra2 <optee_directory>/tee-pageable_v2.bin \ 254 --nt-fw <u-boot_directory>/u-boot-nodtb.bin \ 255 --hw-config <u-boot_directory>/u-boot.dtb \ 256 --fw-config build/stm32mp1/debug/fdts/fw-config.dtb \ 257 --tos-fw-cert build/stm32mp1/cert_images/tee-header_v2.bin.crt \ 258 --tos-fw-key-cert build/stm32mp1/cert_images/tee-header_v2.bin.key-crt \ 259 --nt-fw-cert build/stm32mp1/cert_images/u-boot.bin.crt \ 260 --nt-fw-key-cert build/stm32mp1/cert_images/u-boot.bin.key-crt \ 261 --stm32mp-cfg-cert build/stm32mp1/cert_images/stm32mp_cfg_cert.crt stm32mp1.fip 262 263 264 265Populate SD-card 266---------------- 267 268Boot with FIP 269~~~~~~~~~~~~~ 270The SD-card has to be formatted with GPT. 271It should contain at least those partitions: 272 273- fsbl: to copy the tf-a-stm32mp157c-ev1.stm32 binary (BL2) 274- fip: which contains the FIP binary 275 276Usually, two copies of fsbl are used (fsbl1 and fsbl2) instead of one partition fsbl. 277 278 279.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html 280.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification 281