1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019-2021 Toradex AG 4 */ 5 6/dts-v1/; 7#include <dt-bindings/gpio/gpio.h> 8#include "imx6ull.dtsi" 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 reg_module_3v3: regulator-module-3v3 { 16 compatible = "regulator-fixed"; 17 regulator-always-on; 18 regulator-name = "+V3.3"; 19 regulator-min-microvolt = <3300000>; 20 regulator-max-microvolt = <3300000>; 21 }; 22 23 reg_module_3v3_avdd: regulator-module-3v3-avdd { 24 compatible = "regulator-fixed"; 25 regulator-always-on; 26 regulator-name = "+V3.3_AVDD_AUDIO"; 27 regulator-min-microvolt = <3300000>; 28 regulator-max-microvolt = <3300000>; 29 }; 30 31 reg_5v0: regulator-5v0 { 32 compatible = "regulator-fixed"; 33 regulator-name = "5V"; 34 regulator-min-microvolt = <5000000>; 35 regulator-max-microvolt = <5000000>; 36 }; 37 38 reg_sd1_vmmc: regulator-sd1-vmmc { 39 compatible = "regulator-gpio"; 40 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 43 regulator-always-on; 44 regulator-name = "+V3.3_1.8_SD"; 45 regulator-min-microvolt = <1800000>; 46 regulator-max-microvolt = <3300000>; 47 states = <1800000 0x1 3300000 0x0>; 48 vin-supply = <®_module_3v3>; 49 }; 50 51 reg_usbh_vbus: regulator-usbh-vbus { 52 compatible = "regulator-fixed"; 53 pinctrl-names = "default"; 54 pinctrl-0 = <&pinctrl_usbh_reg>; 55 regulator-name = "VCC_USB[1-4]"; 56 regulator-min-microvolt = <5000000>; 57 regulator-max-microvolt = <5000000>; 58 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */ 59 vin-supply = <®_5v0>; 60 }; 61}; 62 63&adc1 { 64 num-channels = <10>; 65 vref-supply = <®_module_3v3_avdd>; 66}; 67 68/* Colibri SPI */ 69&ecspi1 { 70 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 73}; 74 75/* Ethernet */ 76&fec2 { 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_enet2>; 79 phy-mode = "rmii"; 80 phy-handle = <ðphy1>; 81 status = "okay"; 82 83 mdio { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 ethphy1: ethernet-phy@2 { 88 compatible = "ethernet-phy-ieee802.3-c22"; 89 max-speed = <100>; 90 reg = <2>; 91 }; 92 }; 93}; 94 95/* 96 * I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board) 97 */ 98&i2c1 { 99 pinctrl-names = "default", "gpio"; 100 pinctrl-0 = <&pinctrl_i2c1>; 101 pinctrl-1 = <&pinctrl_i2c1_gpio>; 102 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 103 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 104 status = "okay"; 105}; 106 107/* 108 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and 109 * touch screen controller 110 */ 111&i2c2 { 112 pinctrl-names = "default", "gpio"; 113 pinctrl-0 = <&pinctrl_i2c2>; 114 pinctrl-1 = <&pinctrl_i2c2_gpio>; 115 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 116 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 117 status = "okay"; 118 119 ad7879@2c { 120 compatible = "adi,ad7879-1"; 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 123 reg = <0x2c>; 124 interrupt-parent = <&gpio5>; 125 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 126 touchscreen-max-pressure = <4096>; 127 adi,resistance-plate-x = <120>; 128 adi,first-conversion-delay = /bits/ 8 <3>; 129 adi,acquisition-time = /bits/ 8 <1>; 130 adi,median-filter-size = /bits/ 8 <2>; 131 adi,averaging = /bits/ 8 <1>; 132 adi,conversion-interval = /bits/ 8 <255>; 133 }; 134}; 135 136/* PWM <A> */ 137&pwm4 { 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_pwm4>; 140 #pwm-cells = <3>; 141}; 142 143/* PWM <B> */ 144&pwm5 { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_pwm5>; 147 #pwm-cells = <3>; 148}; 149 150/* PWM <C> */ 151&pwm6 { 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_pwm6>; 154 #pwm-cells = <3>; 155}; 156 157/* PWM <D> */ 158&pwm7 { 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_pwm7>; 161 #pwm-cells = <3>; 162}; 163 164&sdma { 165 status = "okay"; 166}; 167 168&snvs_pwrkey { 169 status = "disabled"; 170}; 171 172/* Colibri UART_A */ 173&uart1 { 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 176 uart-has-rtscts; 177 fsl,dte-mode; 178 status = "okay"; 179}; 180 181/* Colibri UART_B */ 182&uart2 { 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_uart2>; 185 uart-has-rtscts; 186 fsl,dte-mode; 187}; 188 189/* Colibri UART_C */ 190&uart5 { 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_uart5>; 193 fsl,dte-mode; 194}; 195 196/* Colibri USBC */ 197&usbotg1 { 198 dr_mode = "host"; 199 srp-disable; 200 hnp-disable; 201 adp-disable; 202 status = "okay"; 203}; 204 205/* Colibri USBH */ 206&usbotg2 { 207 dr_mode = "host"; 208 vbus-supply = <®_usbh_vbus>; 209 status = "okay"; 210}; 211 212/* Colibri MMC */ 213&usdhc1 { 214 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 215 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 216 assigned-clock-rates = <0>, <198000000>; 217 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */ 218 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 219 pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; 220 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 221 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 222 vmmc-supply = <®_sd1_vmmc>; 223 status = "okay"; 224}; 225 226&iomuxc { 227 pinctrl_can_int: canint-grp { 228 fsl,pins = < 229 /* SODIMM 73 */ 230 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 231 >; 232 }; 233 234 pinctrl_enet2: enet2-grp { 235 fsl,pins = < 236 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 237 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 238 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 239 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 240 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 241 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 242 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 243 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 244 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 245 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 246 >; 247 }; 248 249 pinctrl_ecspi1_cs: ecspi1-cs-grp { 250 fsl,pins = < 251 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 252 >; 253 }; 254 255 pinctrl_ecspi1: ecspi1-grp { 256 fsl,pins = < 257 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 258 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 259 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 260 >; 261 }; 262 263 pinctrl_flexcan2: flexcan2-grp { 264 fsl,pins = < 265 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 266 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 267 >; 268 }; 269 270 pinctrl_gpio_bl_on: gpio-bl-on-grp { 271 fsl,pins = < 272 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0 273 >; 274 }; 275 276 pinctrl_gpio1: gpio1-grp { 277 fsl,pins = < 278 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ 279 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ 280 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */ 281 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */ 282 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */ 283 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */ 284 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */ 285 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */ 286 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */ 287 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */ 288 >; 289 }; 290 291 pinctrl_gpio2: gpio2-grp { /* Camera */ 292 fsl,pins = < 293 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */ 294 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */ 295 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */ 296 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */ 297 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */ 298 >; 299 }; 300 301 pinctrl_gpio3: gpio3-grp { /* CAN2 */ 302 fsl,pins = < 303 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */ 304 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */ 305 >; 306 }; 307 308 pinctrl_gpio4: gpio4-grp { 309 fsl,pins = < 310 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */ 311 >; 312 }; 313 314 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ 315 fsl,pins = < 316 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */ 317 >; 318 }; 319 320 pinctrl_gpio6: gpio6-grp { /* Wifi pins */ 321 fsl,pins = < 322 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */ 323 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */ 324 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */ 325 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */ 326 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */ 327 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */ 328 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */ 329 >; 330 }; 331 332 pinctrl_i2c1: i2c1-grp { 333 fsl,pins = < 334 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 335 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 336 >; 337 }; 338 339 pinctrl_i2c1_gpio: i2c1-gpio-grp { 340 fsl,pins = < 341 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 342 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 343 >; 344 }; 345 346 pinctrl_i2c2: i2c2-grp { 347 fsl,pins = < 348 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 349 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 350 >; 351 }; 352 353 pinctrl_i2c2_gpio: i2c2-gpio-grp { 354 fsl,pins = < 355 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 356 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 357 >; 358 }; 359 360 pinctrl_lcdif_dat: lcdif-dat-grp { 361 fsl,pins = < 362 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 363 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 364 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 365 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 366 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 367 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 368 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 369 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 370 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 371 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 372 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 373 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 374 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 375 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 376 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 377 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 378 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 379 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 380 >; 381 }; 382 383 pinctrl_lcdif_ctrl: lcdif-ctrl-grp { 384 fsl,pins = < 385 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 386 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 387 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 388 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 389 >; 390 }; 391 392 pinctrl_pwm4: pwm4-grp { 393 fsl,pins = < 394 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 395 >; 396 }; 397 398 pinctrl_pwm5: pwm5-grp { 399 fsl,pins = < 400 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 401 >; 402 }; 403 404 pinctrl_pwm6: pwm6-grp { 405 fsl,pins = < 406 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 407 >; 408 }; 409 410 pinctrl_pwm7: pwm7-grp { 411 fsl,pins = < 412 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 413 >; 414 }; 415 416 pinctrl_uart1: uart1-grp { 417 fsl,pins = < 418 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 419 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 420 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 421 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 422 >; 423 }; 424 425 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ 426 fsl,pins = < 427 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */ 428 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */ 429 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */ 430 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */ 431 >; 432 }; 433 434 pinctrl_uart2: uart2-grp { 435 fsl,pins = < 436 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 437 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 438 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 439 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 440 >; 441 }; 442 pinctrl_uart5: uart5-grp { 443 fsl,pins = < 444 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 445 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 446 >; 447 }; 448 449 pinctrl_usbh_reg: gpio-usbh-reg { 450 fsl,pins = < 451 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */ 452 >; 453 }; 454 455 pinctrl_usdhc1: usdhc1-grp { 456 fsl,pins = < 457 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 458 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 459 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 460 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 461 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 462 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 463 >; 464 }; 465 466 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 467 fsl,pins = < 468 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 469 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 470 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 471 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 472 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 473 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 474 >; 475 }; 476 477 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 478 fsl,pins = < 479 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 480 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 481 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 482 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 483 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 484 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 485 >; 486 }; 487 488 pinctrl_usdhc2: usdhc2-grp { 489 fsl,pins = < 490 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 491 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 492 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 493 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 494 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 495 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 496 497 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14 498 >; 499 }; 500}; 501 502&iomuxc_snvs { 503 pinctrl_snvs_gpio1: snvs-gpio1-grp { 504 fsl,pins = < 505 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */ 506 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */ 507 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */ 508 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */ 509 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */ 510 >; 511 }; 512 513 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ 514 fsl,pins = < 515 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */ 516 >; 517 }; 518 519 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ 520 fsl,pins = < 521 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */ 522 >; 523 }; 524 525 pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ 526 fsl,pins = < 527 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 528 >; 529 }; 530 531 pinctrl_snvs_reg_sd: snvs-reg-sd-grp { 532 fsl,pins = < 533 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 534 >; 535 }; 536 537 pinctrl_snvs_usbc_det: snvs-usbc-det-grp { 538 fsl,pins = < 539 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 540 >; 541 }; 542 543 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { 544 fsl,pins = < 545 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0 546 >; 547 }; 548 549 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { 550 fsl,pins = < 551 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */ 552 >; 553 }; 554 555 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { 556 fsl,pins = < 557 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 558 >; 559 }; 560}; 561