1/*
2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_makalu.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table CORTEX_MAKALU_BHB_LOOP_COUNT, cortex_makalu
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29func check_errata_cve_2022_23960
30#if WORKAROUND_CVE_2022_23960
31	mov     x0, #ERRATA_APPLIES
32#else
33	mov     x0, #ERRATA_MISSING
34#endif
35	ret
36endfunc check_errata_cve_2022_23960
37
38func cortex_makalu_reset_func
39	/* Disable speculative loads */
40	msr	SSBS, xzr
41
42#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
43	/*
44	 * The Cortex Makalu generic vectors are overridden to apply errata
45	 * mitigation on exception entry from lower ELs.
46	 */
47        adr	x0, wa_cve_vbar_cortex_makalu
48        msr	vbar_el3, x0
49#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
50
51	isb
52	ret
53endfunc cortex_makalu_reset_func
54
55	/* ----------------------------------------------------
56	 * HW will do the cache maintenance while powering down
57	 * ----------------------------------------------------
58	 */
59func cortex_makalu_core_pwr_dwn
60	/* ---------------------------------------------------
61	 * Enable CPU power down bit in power control register
62	 * ---------------------------------------------------
63	 */
64	mrs	x0, CORTEX_MAKALU_CPUPWRCTLR_EL1
65	orr	x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
66	msr	CORTEX_MAKALU_CPUPWRCTLR_EL1, x0
67	isb
68	ret
69endfunc cortex_makalu_core_pwr_dwn
70
71#if REPORT_ERRATA
72/*
73 * Errata printing function for Cortex Makalu. Must follow AAPCS.
74 */
75func cortex_makalu_errata_report
76	stp	x8, x30, [sp, #-16]!
77
78	bl	cpu_get_rev_var
79	mov	x8, x0
80
81	/*
82	 * Report all errata. The revision-variant information is passed to
83	 * checking functions of each errata.
84	 */
85	report_errata WORKAROUND_CVE_2022_23960, cortex_makalu, cve_2022_23960
86
87	ldp     x8, x30, [sp], #16
88	ret
89endfunc cortex_makalu_errata_report
90#endif
91
92	/* ---------------------------------------------
93	 * This function provides Cortex Makalu-specific
94	 * register information for crash reporting.
95	 * It needs to return with x6 pointing to
96	 * a list of register names in ascii and
97	 * x8 - x15 having values of registers to be
98	 * reported.
99	 * ---------------------------------------------
100	 */
101.section .rodata.cortex_makalu_regs, "aS"
102cortex_makalu_regs:  /* The ascii list of register names to be reported */
103	.asciz	"cpuectlr_el1", ""
104
105func cortex_makalu_cpu_reg_dump
106	adr	x6, cortex_makalu_regs
107	mrs	x8, CORTEX_MAKALU_CPUECTLR_EL1
108	ret
109endfunc cortex_makalu_cpu_reg_dump
110
111declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \
112	cortex_makalu_reset_func, \
113	cortex_makalu_core_pwr_dwn
114