1/*
2 * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_a76ae.h>
11#include <cpu_macros.S>
12#include "wa_cve_2022_23960_bhb_vector.S"
13
14/* Hardware handled coherency */
15#if HW_ASSISTED_COHERENCY == 0
16#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled"
17#endif
18
19/* 64-bit only core */
20#if CTX_INCLUDE_AARCH32_REGS == 1
21#error "Cortex-A76AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
22#endif
23
24#if WORKAROUND_CVE_2022_23960
25	wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
26#endif /* WORKAROUND_CVE_2022_23960 */
27
28func check_errata_cve_2022_23960
29#if WORKAROUND_CVE_2022_23960
30	mov	x0, #ERRATA_APPLIES
31#else
32	mov	x0, #ERRATA_MISSING
33#endif /* WORKAROUND_CVE_2022_23960 */
34	ret
35endfunc check_errata_cve_2022_23960
36
37	/* --------------------------------------------
38	 * The CPU Ops reset function for Cortex-A76AE.
39	 * Shall clobber: x0-x19
40	 * --------------------------------------------
41	 */
42func cortex_a76ae_reset_func
43#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
44	/*
45	 * The Cortex-A76ae generic vectors are overridden to apply errata
46	 * mitigation on exception entry from lower ELs.
47	 */
48	adr	x0, wa_cve_vbar_cortex_a76ae
49	msr	vbar_el3, x0
50	isb
51#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
52
53	ret
54endfunc cortex_a76ae_reset_func
55
56	/* ----------------------------------------------------
57	 * HW will do the cache maintenance while powering down
58	 * ----------------------------------------------------
59	 */
60func cortex_a76ae_core_pwr_dwn
61	/* ---------------------------------------------------
62	 * Enable CPU power down bit in power control register
63	 * ---------------------------------------------------
64	 */
65	mrs	x0, CORTEX_A76AE_CPUPWRCTLR_EL1
66	orr	x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
67	msr	CORTEX_A76AE_CPUPWRCTLR_EL1, x0
68	isb
69	ret
70endfunc cortex_a76ae_core_pwr_dwn
71
72#if REPORT_ERRATA
73/*
74 * Errata printing function for Cortex-A76AE. Must follow AAPCS.
75 */
76func cortex_a76ae_errata_report
77	stp	x8, x30, [sp, #-16]!
78
79	bl	cpu_get_rev_var
80	mov	x8, x0
81
82	/*
83	 * Report all errata. The revision-variant information is passed to
84	 * checking functions of each errata.
85	 */
86	report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960
87
88	ldp	x8, x30, [sp], #16
89	ret
90endfunc cortex_a76ae_errata_report
91#endif	/* REPORT_ERRATA */
92
93	/* ---------------------------------------------
94	 * This function provides cortex_a76ae specific
95	 * register information for crash reporting.
96	 * It needs to return with x6 pointing to
97	 * a list of register names in ascii and
98	 * x8 - x15 having values of registers to be
99	 * reported.
100	 * ---------------------------------------------
101	 */
102.section .rodata.cortex_a76ae_regs, "aS"
103cortex_a76ae_regs:  /* The ASCII list of register names to be reported */
104	.asciz	"cpuectlr_el1", ""
105
106func cortex_a76ae_cpu_reg_dump
107	adr	x6, cortex_a76ae_regs
108	mrs	x8, CORTEX_A76AE_CPUECTLR_EL1
109	ret
110endfunc cortex_a76ae_cpu_reg_dump
111
112declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, cortex_a76ae_reset_func, \
113	cortex_a76ae_core_pwr_dwn
114