1/*
2 * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <common/bl_common.h>
10#include <cortex_x3.h>
11#include <cpu_macros.S>
12#include <plat_macros.S>
13#include "wa_cve_2022_23960_bhb_vector.S"
14
15/* Hardware handled coherency */
16#if HW_ASSISTED_COHERENCY == 0
17#error "Cortex-X3 must be compiled with HW_ASSISTED_COHERENCY enabled"
18#endif
19
20/* 64-bit only core */
21#if CTX_INCLUDE_AARCH32_REGS == 1
22#error "Cortex-X3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
23#endif
24
25#if WORKAROUND_CVE_2022_23960
26	wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
27#endif /* WORKAROUND_CVE_2022_23960 */
28
29	/* ----------------------------------------------------
30	 * HW will do the cache maintenance while powering down
31	 * ----------------------------------------------------
32	 */
33func cortex_x3_core_pwr_dwn
34#if ERRATA_X3_2313909
35	mov	x15, x30
36	bl	cpu_get_rev_var
37	bl	errata_cortex_x3_2313909_wa
38	mov	x30, x15
39#endif /* ERRATA_X3_2313909 */
40
41	/* ---------------------------------------------------
42	 * Enable CPU power down bit in power control register
43	 * ---------------------------------------------------
44	 */
45	mrs	x0, CORTEX_X3_CPUPWRCTLR_EL1
46	orr	x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
47	msr	CORTEX_X3_CPUPWRCTLR_EL1, x0
48	isb
49	ret
50endfunc cortex_x3_core_pwr_dwn
51
52func check_errata_cve_2022_23960
53#if WORKAROUND_CVE_2022_23960
54	mov	x0, #ERRATA_APPLIES
55#else
56	mov	x0, #ERRATA_MISSING
57#endif
58	ret
59endfunc check_errata_cve_2022_23960
60
61func cortex_x3_reset_func
62	/* Disable speculative loads */
63	msr	SSBS, xzr
64
65#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
66	/*
67	 * The Cortex-X3 generic vectors are overridden to apply
68	 * errata mitigation on exception entry from lower ELs.
69         */
70	adr	x0, wa_cve_vbar_cortex_x3
71	msr	vbar_el3, x0
72#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
73
74	isb
75	ret
76endfunc cortex_x3_reset_func
77
78/* ----------------------------------------------------------------------
79 * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
80 * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
81 * Inputs:
82 * x0: variant[4:7] and revision[0:3] of current cpu.
83 * Shall clobber: x0-x1, x17
84 * ----------------------------------------------------------------------
85 */
86func errata_cortex_x3_2313909_wa
87	/* Check revision. */
88	mov	x17, x30
89	bl	check_errata_2313909
90	cbz	x0, 1f
91
92	/* Set bit 36 in ACTLR2_EL1 */
93	mrs	x1, CORTEX_X3_CPUACTLR2_EL1
94	orr	x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
95	msr	CORTEX_X3_CPUACTLR2_EL1, x1
961:
97	ret	x17
98endfunc errata_cortex_x3_2313909_wa
99
100func check_errata_2313909
101	/* Applies to r0p0 and r1p0 */
102	mov	x1, #0x10
103	b	cpu_rev_var_ls
104endfunc check_errata_2313909
105
106#if REPORT_ERRATA
107	/*
108	 * Errata printing function for Cortex-X3. Must follow AAPCS.
109	 */
110func cortex_x3_errata_report
111	stp	x8, x30, [sp, #-16]!
112
113	bl	cpu_get_rev_var
114	mov	x8, x0
115
116	/*
117	 * Report all errata. The revision-variant information is passed to
118	 * checking functions of each errata.
119	 */
120	report_errata ERRATA_X3_2313909, cortex_x3, 2313909
121	report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
122
123	ldp	x8, x30, [sp], #16
124	ret
125endfunc cortex_x3_errata_report
126#endif
127
128	/* ---------------------------------------------
129	 * This function provides Cortex-X3-
130	 * specific register information for crash
131	 * reporting. It needs to return with x6
132	 * pointing to a list of register names in ascii
133	 * and x8 - x15 having values of registers to be
134	 * reported.
135	 * ---------------------------------------------
136	 */
137.section .rodata.cortex_x3_regs, "aS"
138cortex_x3_regs:  /* The ascii list of register names to be reported */
139	.asciz	"cpuectlr_el1", ""
140
141func cortex_x3_cpu_reg_dump
142	adr	x6, cortex_x3_regs
143	mrs	x8, CORTEX_X3_CPUECTLR_EL1
144	ret
145endfunc cortex_x3_cpu_reg_dump
146
147declare_cpu_ops cortex_x3, CORTEX_X3_MIDR, \
148	cortex_x3_reset_func, \
149	cortex_x3_core_pwr_dwn
150