1 /* 2 * Arm SCP/MCP Software 3 * Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 * Description: 8 * SCP PIK registers 9 */ 10 11 #ifndef MORELLO_PIK_SCP_H 12 #define MORELLO_PIK_SCP_H 13 14 #include <fwk_macros.h> 15 16 #include <stdint.h> 17 18 /*! 19 * \brief SCP PIK register definitions 20 */ 21 struct pik_scp_reg { 22 uint8_t RESERVED0[0x10 - 0x0]; 23 FWK_RW uint32_t RESET_SYNDROME; 24 uint8_t RESERVED1[0x20 - 0x14]; 25 FWK_RW uint32_t SURVIVAL_RESET_STATUS; 26 uint8_t RESERVED2[0x30 - 0x24]; 27 FWK_RW uint32_t MCP_SEC_CTRL; 28 FWK_RW uint32_t ADDR_TRANS; 29 FWK_RW uint32_t DBG_ADDR_TRANS; 30 uint8_t RESERVED3[0x40 - 0x3C]; 31 FWK_RW uint32_t WS1_TIMER_MATCH; 32 FWK_RW uint32_t WS1_TIMER_EN; 33 uint8_t RESERVED4[0x200 - 0x48]; 34 FWK_R uint32_t SS_RESET_STATUS; 35 FWK_W uint32_t SS_RESET_SET; 36 FWK_W uint32_t SS_RESET_CLR; 37 uint8_t RESERVED5[0x810 - 0x20C]; 38 FWK_RW uint32_t CORECLK_CTRL; 39 FWK_RW uint32_t CORECLK_DIV1; 40 uint8_t RESERVED6[0x820 - 0x818]; 41 FWK_RW uint32_t ACLK_CTRL; 42 FWK_RW uint32_t ACLK_DIV1; 43 uint8_t RESERVED7[0x830 - 0x828]; 44 FWK_RW uint32_t SYNCCLK_CTRL; 45 FWK_RW uint32_t SYNCCLK_DIV1; 46 uint8_t RESERVED8[0xA10 - 0x838]; 47 FWK_R uint32_t PLL_STATUS[17]; 48 uint8_t RESERVED9[0xA60 - 0xA54]; 49 FWK_R uint32_t CONS_MMUTCU_INT_STATUS; 50 FWK_R uint32_t CONS_MMUTBU_INT_STATUS0; 51 FWK_R uint32_t CONS_MMUTBU_INT_STATUS1; 52 uint8_t RESERVED10[0xB00 - 0xA6C]; 53 FWK_R uint32_t MHU_NS_INT_STATUS; 54 FWK_R uint32_t MHU_S_INT_STATUS; 55 uint8_t RESERVED11[0xB20 - 0xB08]; 56 FWK_R uint32_t CPU_PPU_INT_STATUS[8]; 57 FWK_R uint32_t CLUS_PPU_INT_STATUS; 58 uint8_t RESERVED12[0xB60 - 0xB44]; 59 FWK_R uint32_t TIMER_INT_STATUS[8]; 60 FWK_R uint32_t CPU_PLL_LOCK_STATUS[8]; 61 uint8_t RESERVED13[0xBC0 - 0xBA0]; 62 FWK_R uint32_t CPU_PLL_UNLOCK_STATUS[8]; 63 uint8_t RESERVED14[0xBF0 - 0xBE0]; 64 FWK_R uint32_t CLUSTER_PLL_LOCK_STATUS; 65 FWK_R uint32_t CLUSTER_PLL_UNLOCK_STATUS; 66 uint8_t RESERVED15[0xC00 - 0xBF8]; 67 FWK_R uint32_t CLUS_FAULT_INT_STATUS; 68 uint8_t RESERVED16[0xC30 - 0xC04]; 69 FWK_R uint32_t CLUSTER_ECCERR_INT_STATUS; 70 uint8_t RESERVED17[0xD00 - 0xC34]; 71 FWK_R uint32_t DMC0_4_INT_STATUS; 72 FWK_R uint32_t DMC1_5_INT_STATUS; 73 FWK_R uint32_t DMC2_6_INT_STATUS; 74 FWK_R uint32_t DMC3_7_INT_STATUS; 75 uint8_t RESERVED18[0xFC0 - 0xD10]; 76 FWK_R uint32_t PCL_CFG; 77 uint8_t RESERVED19[0xFD0 - 0xFC4]; 78 FWK_R uint32_t PID4; 79 FWK_R uint32_t PID5; 80 FWK_R uint32_t PID6; 81 FWK_R uint32_t PID7; 82 FWK_R uint32_t PID0; 83 FWK_R uint32_t PID1; 84 FWK_R uint32_t PID2; 85 FWK_R uint32_t PID3; 86 FWK_R uint32_t ID0; 87 FWK_R uint32_t ID1; 88 FWK_R uint32_t ID2; 89 FWK_R uint32_t ID3; 90 }; 91 92 #endif /* MORELLO_PIK_SCP_H */ 93