1 /*
2 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <platform_def.h>
9
10 #include <common/debug.h>
11 #include <common/interrupt_props.h>
12 #include <drivers/arm/gicv3.h>
13 #include <lib/utils.h>
14 #include <plat/arm/common/plat_arm.h>
15 #include <plat/common/platform.h>
16
17 /******************************************************************************
18 * The following functions are defined as weak to allow a platform to override
19 * the way the GICv3 driver is initialised and used.
20 *****************************************************************************/
21 #pragma weak plat_arm_gic_driver_init
22 #pragma weak plat_arm_gic_init
23 #pragma weak plat_arm_gic_cpuif_enable
24 #pragma weak plat_arm_gic_cpuif_disable
25 #pragma weak plat_arm_gic_pcpu_init
26 #pragma weak plat_arm_gic_redistif_on
27 #pragma weak plat_arm_gic_redistif_off
28
29 /* The GICv3 driver only needs to be initialized in EL3 */
30 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
31
32 /* Default GICR base address to be used for GICR probe. */
33 static const uintptr_t gicr_base_addrs[2] = {
34 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
35 0U /* Zero Termination */
36 };
37
38 /* List of zero terminated GICR frame addresses which CPUs will probe */
39 static const uintptr_t *gicr_frames = gicr_base_addrs;
40
41 static const interrupt_prop_t arm_interrupt_props[] = {
42 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
43 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
44 };
45
46 /*
47 * We save and restore the GICv3 context on system suspend. Allocate the
48 * data in the designated EL3 Secure carve-out memory. The `used` attribute
49 * is used to prevent the compiler from removing the gicv3 contexts.
50 */
51 static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram") __used;
52 static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram") __used;
53
54 /* Define accessor function to get reference to the GICv3 context */
55 DEFINE_LOAD_SYM_ADDR(rdist_ctx)
DEFINE_LOAD_SYM_ADDR(dist_ctx)56 DEFINE_LOAD_SYM_ADDR(dist_ctx)
57
58 /*
59 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
60 * to core position.
61 *
62 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
63 * values read from GICR_TYPER don't have an MT field. To reuse the same
64 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
65 * that read from GICR_TYPER.
66 *
67 * Assumptions:
68 *
69 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
70 * - No CPUs implemented in the system use affinity level 3.
71 */
72 static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
73 {
74 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
75 return plat_arm_calc_core_pos(mpidr);
76 }
77
78 static const gicv3_driver_data_t arm_gic_data __unused = {
79 .gicd_base = PLAT_ARM_GICD_BASE,
80 .gicr_base = 0U,
81 .interrupt_props = arm_interrupt_props,
82 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
83 .rdistif_num = PLATFORM_CORE_COUNT,
84 .rdistif_base_addrs = rdistif_base_addrs,
85 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
86 };
87
88 /*
89 * By default, gicr_frames will be pointing to gicr_base_addrs. If
90 * the platform supports a non-contiguous GICR frames (GICR frames located
91 * at uneven offset), plat_arm_override_gicr_frames function can be used by
92 * such platform to override the gicr_frames.
93 */
plat_arm_override_gicr_frames(const uintptr_t * plat_gicr_frames)94 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames)
95 {
96 assert(plat_gicr_frames != NULL);
97 gicr_frames = plat_gicr_frames;
98 }
99
plat_arm_gic_driver_init(void)100 void __init plat_arm_gic_driver_init(void)
101 {
102 /*
103 * The GICv3 driver is initialized in EL3 and does not need
104 * to be initialized again in SEL1. This is because the S-EL1
105 * can use GIC system registers to manage interrupts and does
106 * not need GIC interface base addresses to be configured.
107 */
108 #if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
109 (defined(__aarch64__) && defined(IMAGE_BL31))
110 gicv3_driver_init(&arm_gic_data);
111
112 if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) {
113 ERROR("No GICR base frame found for Primary CPU\n");
114 panic();
115 }
116 #endif
117 }
118
119 /******************************************************************************
120 * ARM common helper to initialize the GIC. Only invoked by BL31
121 *****************************************************************************/
plat_arm_gic_init(void)122 void __init plat_arm_gic_init(void)
123 {
124 gicv3_distif_init();
125 gicv3_rdistif_init(plat_my_core_pos());
126 gicv3_cpuif_enable(plat_my_core_pos());
127 }
128
129 /******************************************************************************
130 * ARM common helper to enable the GIC CPU interface
131 *****************************************************************************/
plat_arm_gic_cpuif_enable(void)132 void plat_arm_gic_cpuif_enable(void)
133 {
134 gicv3_cpuif_enable(plat_my_core_pos());
135 }
136
137 /******************************************************************************
138 * ARM common helper to disable the GIC CPU interface
139 *****************************************************************************/
plat_arm_gic_cpuif_disable(void)140 void plat_arm_gic_cpuif_disable(void)
141 {
142 gicv3_cpuif_disable(plat_my_core_pos());
143 }
144
145 /******************************************************************************
146 * ARM common helper function to iterate over all GICR frames and discover the
147 * corresponding per-cpu redistributor frame as well as initialize the
148 * corresponding interface in GICv3.
149 *****************************************************************************/
plat_arm_gic_pcpu_init(void)150 void plat_arm_gic_pcpu_init(void)
151 {
152 int result;
153 const uintptr_t *plat_gicr_frames = gicr_frames;
154
155 do {
156 result = gicv3_rdistif_probe(*plat_gicr_frames);
157
158 /* If the probe is successful, no need to proceed further */
159 if (result == 0)
160 break;
161
162 plat_gicr_frames++;
163 } while (*plat_gicr_frames != 0U);
164
165 if (result == -1) {
166 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
167 panic();
168 }
169 gicv3_rdistif_init(plat_my_core_pos());
170 }
171
172 /******************************************************************************
173 * ARM common helpers to power GIC redistributor interface
174 *****************************************************************************/
plat_arm_gic_redistif_on(void)175 void plat_arm_gic_redistif_on(void)
176 {
177 gicv3_rdistif_on(plat_my_core_pos());
178 }
179
plat_arm_gic_redistif_off(void)180 void plat_arm_gic_redistif_off(void)
181 {
182 gicv3_rdistif_off(plat_my_core_pos());
183 }
184
185 /******************************************************************************
186 * ARM common helper to save & restore the GICv3 on resume from system suspend
187 *****************************************************************************/
plat_arm_gic_save(void)188 void plat_arm_gic_save(void)
189 {
190 gicv3_redist_ctx_t * const rdist_context =
191 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
192 gicv3_dist_ctx_t * const dist_context =
193 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
194
195 /*
196 * If an ITS is available, save its context before
197 * the Redistributor using:
198 * gicv3_its_save_disable(gits_base, &its_ctx[i])
199 * Additionally, an implementation-defined sequence may
200 * be required to save the whole ITS state.
201 */
202
203 /*
204 * Save the GIC Redistributors and ITS contexts before the
205 * Distributor context. As we only handle SYSTEM SUSPEND API,
206 * we only need to save the context of the CPU that is issuing
207 * the SYSTEM SUSPEND call, i.e. the current CPU.
208 */
209 gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
210
211 /* Save the GIC Distributor context */
212 gicv3_distif_save(dist_context);
213
214 /*
215 * From here, all the components of the GIC can be safely powered down
216 * as long as there is an alternate way to handle wakeup interrupt
217 * sources.
218 */
219 }
220
plat_arm_gic_resume(void)221 void plat_arm_gic_resume(void)
222 {
223 const gicv3_redist_ctx_t *rdist_context =
224 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
225 const gicv3_dist_ctx_t *dist_context =
226 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
227
228 /* Restore the GIC Distributor context */
229 gicv3_distif_init_restore(dist_context);
230
231 /*
232 * Restore the GIC Redistributor and ITS contexts after the
233 * Distributor context. As we only handle SYSTEM SUSPEND API,
234 * we only need to restore the context of the CPU that issued
235 * the SYSTEM SUSPEND call.
236 */
237 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
238
239 /*
240 * If an ITS is available, restore its context after
241 * the Redistributor using:
242 * gicv3_its_restore(gits_base, &its_ctx[i])
243 * An implementation-defined sequence may be required to
244 * restore the whole ITS state. The ITS must also be
245 * re-enabled after this sequence has been executed.
246 */
247 }
248