1 /* 2 * Copyright (c) 2015 Brian Swetland 3 * 4 * Use of this source code is governed by a MIT-style 5 * license that can be found in the LICENSE file or at 6 * https://opensource.org/licenses/MIT 7 */ 8 9 #pragma once 10 11 #define UART0_BASE 0x40081000 12 #define UART1_BASE 0x40082000 13 #define UART2_BASE 0x400C1000 14 #define UART3_BASE 0x400C2000 15 16 #define REG_RBR 0x00 // RO Recv Buffer (DLAB==0) 17 #define REG_THR 0x00 // WO Xmit Holding (DLAB==0) 18 #define REG_IER 0x04 // RW Interrupt Enable (DLAB==0) 19 #define REG_DLL 0x00 // RW Divisor Latch LSB (DLAB==1) 20 #define REG_DLM 0x04 // RW Divisor Latch MSB (DLAB==1) 21 #define REG_IIR 0x08 // RO Interrupt ID 22 #define REG_FCR 0x08 // WO Fifo Control 23 #define REG_LCR 0x0C // RW Line Control 24 #define REG_MCR 0x10 // RW Modem Control (UART1 only) 25 #define REG_LSR 0x14 // RO Line Status 26 #define REG_MSR 0x18 // RO Modem Status (UART1 only) 27 #define REG_SCR 0x1C // RW Scratcpad (no hw use) 28 #define REG_ACR 0x20 // RW Auto-baud Control 29 #define REG_ICR 0x24 // RW IrDA Control 30 #define REG_FDR 0x28 // RW Fractional Divider 31 #define REG_OSR 0x2C // RW Oversampling (REG0/2/3 only) 32 33 #define IER_RBRIE (1 << 0) // enable receive data avail 34 #define IER_THREIE (1 << 1) // enable THRE irq 35 #define IER_RXIE (1 << 2) // enable RX Line Status IRQs 36 37 #define IIR_INTSTATUS (1 << 0) // 0=IRQ Pending 38 #define IIR_INTID_MASK (3 << 1) 39 #define IIR_INTID_RLS (3 << 1) // Receive Line Status 40 // Cleared on LSR Read 41 #define IIR_INTID_RDA (2 << 1) // Receive Data Available 42 // Cleared when FIFO < trigger level 43 #define IIR_INTID_CTI (6 << 1) // Character Timeout 44 // data in FIFO, and 3.5-4.5 char times idle 45 #define IIR_INTID_THRE (1 << 1) // Transmit Holding Register Empty 46 #define IIR_INTID_NONE (0 << 1) 47 48 #define FCR_FIFOEN (1 << 0) // enable FIFO 49 #define FCR_RXFIFORES (1 << 1) // RX FIFO reset 50 #define FCR_TXFIFORES (1 << 2) // TX FIFO reset 51 #define FCR_DMAMODE (1 << 3) // select DMA mode 52 #define FCR_RX_TRIG_1 (0 << 6) // RX Trigger at 1 byte 53 #define FCR_RX_TRIG_4 (1 << 6) // RX Trigger at 4 bytes 54 #define FCR_RX_TRIG_8 (2 << 6) // RX Trigger at 8 bytes 55 #define FCR_RX_TRIG_14 (3 << 6) // RX Trigger at 14 bytes 56 57 #define LCR_WLS_5 (0 << 0) // 5bit character 58 #define LCR_WLS_6 (1 << 0) // 6bit character 59 #define LCR_WLS_7 (2 << 0) // 7bit character 60 #define LCR_WLS_8 (3 << 0) // 8bit character 61 #define LCR_SBS_1 (0 << 2) // 1 stop bit 62 #define LCR_SBS_2 (1 << 2) // 2 stop bits 63 #define LCR_PE (1 << 3) // parity enable 64 #define LCR_PS_ODD (0 << 4) // odd parity 65 #define LCR_PS_EVEN (1 << 4) // even parity 66 #define LCR_PS_HIGH (2 << 4) // always-1 parity 67 #define LCR_PS_LOW (3 << 4) // always-0 parity 68 #define LCR_BC (1 << 6) // enable break transmission 69 #define LCR_DLAB (1 << 7) // enable access to divisor latches 70 71 #define LSR_RDR (1 << 0) // receiver data ready 72 #define LSR_OE (1 << 1) // overrun error (fifo was full, character lost) 73 #define LSR_PE (1 << 2) // parity error (top of fifo) 74 #define LSR_FE (1 << 3) // framing error (top of fifo) 75 #define LSR_BI (1 << 4) // break interrupt 76 #define LSR_THRE (1 << 5) // transmit holding register empty 77 #define LSR_TEMT (1 << 6) // transmitter empty 78 #define LSR_RXFE (1 << 7) // error in RX FIFO 79 #define LSR_TXERR (1 << 8) // NACK received in smart card mode 80 81 #define FDR_DIVADDVAL(n) ((n) & 0xF) 82 #define FDR_MULVAL(n) (((n) & 0xF) << 4) 83 84 // baud rate selection: 85 // 86 // PCLK / ( 16 * ( 256 * DLM + DLL ) * ( 1 + ( DivAddVal / MulVal ) ) 87 // 88 // 1 <= MulVal <= 15 DivAddVal == 0 -> Disables Frac Divider 89 // 0 <= DivAddVal <= 14 90 // DivAddVal < MulVal 91 92 93 #define OSR_OSFRAC(n) (((n) & 0x3) << 1) // fractional part 94 #define OSR_OSINT(n) (((n) & 0xF) << 4) // integer part - 1 95 96 // oversampling rate = OsInt + 1 + ( 1/8 * OsFrac) (default is 16) 97 98 99