1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #ifndef _R819XU_PHYREG_H 8 #define _R819XU_PHYREG_H 9 10 11 #define RF_DATA 0x1d4 12 13 #define rPMAC_Reset 0x100 14 #define rPMAC_TxStart 0x104 15 #define rPMAC_TxLegacySIG 0x108 16 #define rPMAC_TxHTSIG1 0x10c 17 #define rPMAC_TxHTSIG2 0x110 18 #define rPMAC_PHYDebug 0x114 19 #define rPMAC_TxPacketNum 0x118 20 #define rPMAC_TxIdle 0x11c 21 #define rPMAC_TxMACHeader0 0x120 22 #define rPMAC_TxMACHeader1 0x124 23 #define rPMAC_TxMACHeader2 0x128 24 #define rPMAC_TxMACHeader3 0x12c 25 #define rPMAC_TxMACHeader4 0x130 26 #define rPMAC_TxMACHeader5 0x134 27 #define rPMAC_TxDataType 0x138 28 #define rPMAC_TxRandomSeed 0x13c 29 #define rPMAC_CCKPLCPPreamble 0x140 30 #define rPMAC_CCKPLCPHeader 0x144 31 #define rPMAC_CCKCRC16 0x148 32 #define rPMAC_OFDMRxCRC32OK 0x170 33 #define rPMAC_OFDMRxCRC32Er 0x174 34 #define rPMAC_OFDMRxParityEr 0x178 35 #define rPMAC_OFDMRxCRC8Er 0x17c 36 #define rPMAC_CCKCRxRC16Er 0x180 37 #define rPMAC_CCKCRxRC32Er 0x184 38 #define rPMAC_CCKCRxRC32OK 0x188 39 #define rPMAC_TxStatus 0x18c 40 41 #define MCS_TXAGC 0x340 42 #define CCK_TXAGC 0x348 43 44 /* Mac block on/off control register */ 45 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 46 #define rFPGA0_TxInfo 0x804 47 #define rFPGA0_PSDFunction 0x808 48 #define rFPGA0_TxGainStage 0x80c 49 #define rFPGA0_RFTiming1 0x810 50 #define rFPGA0_RFTiming2 0x814 51 #define rFPGA0_XA_HSSIParameter1 0x820 52 #define rFPGA0_XA_HSSIParameter2 0x824 53 #define rFPGA0_XB_HSSIParameter1 0x828 54 #define rFPGA0_XB_HSSIParameter2 0x82c 55 #define rFPGA0_XC_HSSIParameter1 0x830 56 #define rFPGA0_XC_HSSIParameter2 0x834 57 #define rFPGA0_XD_HSSIParameter1 0x838 58 #define rFPGA0_XD_HSSIParameter2 0x83c 59 #define rFPGA0_XA_LSSIParameter 0x840 60 #define rFPGA0_XB_LSSIParameter 0x844 61 #define rFPGA0_XC_LSSIParameter 0x848 62 #define rFPGA0_XD_LSSIParameter 0x84c 63 #define rFPGA0_RFWakeUpParameter 0x850 64 #define rFPGA0_RFSleepUpParameter 0x854 65 #define rFPGA0_XAB_SwitchControl 0x858 66 #define rFPGA0_XCD_SwitchControl 0x85c 67 #define rFPGA0_XA_RFInterfaceOE 0x860 68 #define rFPGA0_XB_RFInterfaceOE 0x864 69 #define rFPGA0_XC_RFInterfaceOE 0x868 70 #define rFPGA0_XD_RFInterfaceOE 0x86c 71 #define rFPGA0_XAB_RFInterfaceSW 0x870 72 #define rFPGA0_XCD_RFInterfaceSW 0x874 73 #define rFPGA0_XAB_RFParameter 0x878 74 #define rFPGA0_XCD_RFParameter 0x87c 75 #define rFPGA0_AnalogParameter1 0x880 76 #define rFPGA0_AnalogParameter2 0x884 77 #define rFPGA0_AnalogParameter3 0x888 78 #define rFPGA0_AnalogParameter4 0x88c 79 #define rFPGA0_XA_LSSIReadBack 0x8a0 80 #define rFPGA0_XB_LSSIReadBack 0x8a4 81 #define rFPGA0_XC_LSSIReadBack 0x8a8 82 #define rFPGA0_XD_LSSIReadBack 0x8ac 83 #define rFPGA0_PSDReport 0x8b4 84 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 85 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 86 87 /* Page 9 - RF mode & OFDM TxSC */ 88 #define rFPGA1_RFMOD 0x900 89 #define rFPGA1_TxBlock 0x904 90 #define rFPGA1_DebugSelect 0x908 91 #define rFPGA1_TxInfo 0x90c 92 93 #define rCCK0_System 0xa00 94 #define rCCK0_AFESetting 0xa04 95 #define rCCK0_CCA 0xa08 96 /* AGC default value, saturation level */ 97 #define rCCK0_RxAGC1 0xa0c 98 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 99 #define rCCK0_RxHP 0xa14 100 /* Timing recovery & channel estimation threshold */ 101 #define rCCK0_DSPParameter1 0xa18 102 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 103 #define rCCK0_TxFilter1 0xa20 104 #define rCCK0_TxFilter2 0xa24 105 #define rCCK0_DebugPort 0xa28 /* Debug port and TX filter 3 */ 106 #define rCCK0_FalseAlarmReport 0xa2c 107 #define rCCK0_TRSSIReport 0xa50 108 #define rCCK0_RxReport 0xa54 109 #define rCCK0_FACounterLower 0xa5c 110 #define rCCK0_FACounterUpper 0xa58 111 112 #define rOFDM0_LSTF 0xc00 113 #define rOFDM0_TRxPathEnable 0xc04 114 #define rOFDM0_TRMuxPar 0xc08 115 #define rOFDM0_TRSWIsolation 0xc0c 116 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 117 #define rOFDM0_XARxAFE 0xc10 118 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 119 #define rOFDM0_XBRxAFE 0xc18 120 #define rOFDM0_XBRxIQImbalance 0xc1c 121 #define rOFDM0_XCRxAFE 0xc20 122 #define rOFDM0_XCRxIQImbalance 0xc24 123 #define rOFDM0_XDRxAFE 0xc28 124 #define rOFDM0_XDRxIQImbalance 0xc2c 125 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ 126 #define rOFDM0_RxDetector2 0xc34 /* SBD */ 127 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync */ 128 /* PD, SBD, Frame Sync & Short-GI */ 129 #define rOFDM0_RxDetector4 0xc3c 130 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 131 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 132 #define rOFDM0_CCADropThreshold 0xc48 133 #define rOFDM0_ECCAThreshold 0xc4c /* Energy CCA */ 134 #define rOFDM0_XAAGCCore1 0xc50 135 #define rOFDM0_XAAGCCore2 0xc54 136 #define rOFDM0_XBAGCCore1 0xc58 137 #define rOFDM0_XBAGCCore2 0xc5c 138 #define rOFDM0_XCAGCCore1 0xc60 139 #define rOFDM0_XCAGCCore2 0xc64 140 #define rOFDM0_XDAGCCore1 0xc68 141 #define rOFDM0_XDAGCCore2 0xc6c 142 #define rOFDM0_AGCParameter1 0xc70 143 #define rOFDM0_AGCParameter2 0xc74 144 #define rOFDM0_AGCRSSITable 0xc78 145 #define rOFDM0_HTSTFAGC 0xc7c 146 #define rOFDM0_XATxIQImbalance 0xc80 147 #define rOFDM0_XATxAFE 0xc84 148 #define rOFDM0_XBTxIQImbalance 0xc88 149 #define rOFDM0_XBTxAFE 0xc8c 150 #define rOFDM0_XCTxIQImbalance 0xc90 151 #define rOFDM0_XCTxAFE 0xc94 152 #define rOFDM0_XDTxIQImbalance 0xc98 153 #define rOFDM0_XDTxAFE 0xc9c 154 #define rOFDM0_RxHPParameter 0xce0 155 #define rOFDM0_TxPseudoNoiseWgt 0xce4 156 #define rOFDM0_FrameSync 0xcf0 157 #define rOFDM0_DFSReport 0xcf4 158 #define rOFDM0_TxCoeff1 0xca4 159 #define rOFDM0_TxCoeff2 0xca8 160 #define rOFDM0_TxCoeff3 0xcac 161 #define rOFDM0_TxCoeff4 0xcb0 162 #define rOFDM0_TxCoeff5 0xcb4 163 #define rOFDM0_TxCoeff6 0xcb8 164 165 166 #define rOFDM1_LSTF 0xd00 167 #define rOFDM1_TRxPathEnable 0xd04 168 #define rOFDM1_CFO 0xd08 169 #define rOFDM1_CSI1 0xd10 170 #define rOFDM1_SBD 0xd14 171 #define rOFDM1_CSI2 0xd18 172 #define rOFDM1_CFOTracking 0xd2c 173 #define rOFDM1_TRxMesaure1 0xd34 174 #define rOFDM1_IntfDet 0xd3c 175 #define rOFDM1_PseudoNoiseStateAB 0xd50 176 #define rOFDM1_PseudoNoiseStateCD 0xd54 177 #define rOFDM1_RxPseudoNoiseWgt 0xd58 178 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 179 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 180 #define rOFDM_PHYCounter3 0xda8 /* MCS not supported */ 181 #define rOFDM_ShortCFOAB 0xdac 182 #define rOFDM_ShortCFOCD 0xdb0 183 #define rOFDM_LongCFOAB 0xdb4 184 #define rOFDM_LongCFOCD 0xdb8 185 #define rOFDM_TailCFOAB 0xdbc 186 #define rOFDM_TailCFOCD 0xdc0 187 #define rOFDM_PWMeasure1 0xdc4 188 #define rOFDM_PWMeasure2 0xdc8 189 #define rOFDM_BWReport 0xdcc 190 #define rOFDM_AGCReport 0xdd0 191 #define rOFDM_RxSNR 0xdd4 192 #define rOFDM_RxEVMCSI 0xdd8 193 #define rOFDM_SIGReport 0xddc 194 195 #define rTxAGC_Rate18_06 0xe00 196 #define rTxAGC_Rate54_24 0xe04 197 #define rTxAGC_CCK_Mcs32 0xe08 198 #define rTxAGC_Mcs03_Mcs00 0xe10 199 #define rTxAGC_Mcs07_Mcs04 0xe14 200 #define rTxAGC_Mcs11_Mcs08 0xe18 201 #define rTxAGC_Mcs15_Mcs12 0xe1c 202 203 204 #define rZebra1_HSSIEnable 0x0 205 #define rZebra1_TRxEnable1 0x1 206 #define rZebra1_TRxEnable2 0x2 207 #define rZebra1_AGC 0x4 208 #define rZebra1_ChargePump 0x5 209 #define rZebra1_Channel 0x7 210 #define rZebra1_TxGain 0x8 211 #define rZebra1_TxLPF 0x9 212 #define rZebra1_RxLPF 0xb 213 #define rZebra1_RxHPFCorner 0xc 214 215 /* Zebra 4 */ 216 #define rGlobalCtrl 0 217 #define rRTL8256_TxLPF 19 218 #define rRTL8256_RxLPF 11 219 220 /* RTL8258 */ 221 #define rRTL8258_TxLPF 0x11 222 #define rRTL8258_RxLPF 0x13 223 #define rRTL8258_RSSILPF 0xa 224 225 /* Bit Mask - Page 1*/ 226 #define bBBResetB 0x100 227 #define bGlobalResetB 0x200 228 #define bOFDMTxStart 0x4 229 #define bCCKTxStart 0x8 230 #define bCRC32Debug 0x100 231 #define bPMACLoopback 0x10 232 #define bTxLSIG 0xffffff 233 #define bOFDMTxRate 0xf 234 #define bOFDMTxReserved 0x10 235 #define bOFDMTxLength 0x1ffe0 236 #define bOFDMTxParity 0x20000 237 #define bTxHTSIG1 0xffffff 238 #define bTxHTMCSRate 0x7f 239 #define bTxHTBW 0x80 240 #define bTxHTLength 0xffff00 241 #define bTxHTSIG2 0xffffff 242 #define bTxHTSmoothing 0x1 243 #define bTxHTSounding 0x2 244 #define bTxHTReserved 0x4 245 #define bTxHTAggreation 0x8 246 #define bTxHTSTBC 0x30 247 #define bTxHTAdvanceCoding 0x40 248 #define bTxHTShortGI 0x80 249 #define bTxHTNumberHT_LTF 0x300 250 #define bTxHTCRC8 0x3fc00 251 #define bCounterReset 0x10000 252 #define bNumOfOFDMTx 0xffff 253 #define bNumOfCCKTx 0xffff0000 254 #define bTxIdleInterval 0xffff 255 #define bOFDMService 0xffff0000 256 #define bTxMACHeader 0xffffffff 257 #define bTxDataInit 0xff 258 #define bTxHTMode 0x100 259 #define bTxDataType 0x30000 260 #define bTxRandomSeed 0xffffffff 261 #define bCCKTxPreamble 0x1 262 #define bCCKTxSFD 0xffff0000 263 #define bCCKTxSIG 0xff 264 #define bCCKTxService 0xff00 265 #define bCCKLengthExt 0x8000 266 #define bCCKTxLength 0xffff0000 267 #define bCCKTxCRC16 0xffff 268 #define bCCKTxStatus 0x1 269 #define bOFDMTxStatus 0x2 270 /* Bit Mask - Page 8 */ 271 #define bRFMOD 0x1 272 #define bJapanMode 0x2 273 #define bCCKTxSC 0x30 274 #define bCCKEn 0x1000000 275 #define bOFDMEn 0x2000000 276 #define bOFDMRxADCPhase 0x10000 277 #define bOFDMTxDACPhase 0x40000 278 #define bXATxAGC 0x3f 279 #define bXBTxAGC 0xf00 280 #define bXCTxAGC 0xf000 281 #define bXDTxAGC 0xf0000 282 #define bPAStart 0xf0000000 283 #define bTRStart 0x00f00000 284 #define bRFStart 0x0000f000 285 #define bBBStart 0x000000f0 286 #define bBBCCKStart 0x0000000f 287 /* Bit Mask - rFPGA0_RFTiming2 */ 288 #define bPAEnd 0xf 289 #define bTREnd 0x0f000000 290 #define bRFEnd 0x000f0000 291 /* T2R */ 292 #define bCCAMask 0x000000f0 293 #define bR2RCCAMask 0x00000f00 294 #define bHSSI_R2TDelay 0xf8000000 295 #define bHSSI_T2RDelay 0xf80000 296 /* Channel gain at continue TX. */ 297 #define bContTxHSSI 0x400 298 #define bIGFromCCK 0x200 299 #define bAGCAddress 0x3f 300 #define bRxHPTx 0x7000 301 #define bRxHPT2R 0x38000 302 #define bRxHPCCKIni 0xc0000 303 #define bAGCTxCode 0xc00000 304 #define bAGCRxCode 0x300000 305 #define b3WireDataLength 0x800 306 #define b3WireAddressLength 0x400 307 #define b3WireRFPowerDown 0x1 308 /*#define bHWSISelect 0x8 */ 309 #define b5GPAPEPolarity 0x40000000 310 #define b2GPAPEPolarity 0x80000000 311 #define bRFSW_TxDefaultAnt 0x3 312 #define bRFSW_TxOptionAnt 0x30 313 #define bRFSW_RxDefaultAnt 0x300 314 #define bRFSW_RxOptionAnt 0x3000 315 #define bRFSI_3WireData 0x1 316 #define bRFSI_3WireClock 0x2 317 #define bRFSI_3WireLoad 0x4 318 #define bRFSI_3WireRW 0x8 319 /* 3-wire total control */ 320 #define bRFSI_3Wire 0xf 321 #define bRFSI_RFENV 0x10 322 #define bRFSI_TRSW 0x20 323 #define bRFSI_TRSWB 0x40 324 #define bRFSI_ANTSW 0x100 325 #define bRFSI_ANTSWB 0x200 326 #define bRFSI_PAPE 0x400 327 #define bRFSI_PAPE5G 0x800 328 #define bBandSelect 0x1 329 #define bHTSIG2_GI 0x80 330 #define bHTSIG2_Smoothing 0x01 331 #define bHTSIG2_Sounding 0x02 332 #define bHTSIG2_Aggreaton 0x08 333 #define bHTSIG2_STBC 0x30 334 #define bHTSIG2_AdvCoding 0x40 335 #define bHTSIG2_NumOfHTLTF 0x300 336 #define bHTSIG2_CRC8 0x3fc 337 #define bHTSIG1_MCS 0x7f 338 #define bHTSIG1_BandWidth 0x80 339 #define bHTSIG1_HTLength 0xffff 340 #define bLSIG_Rate 0xf 341 #define bLSIG_Reserved 0x10 342 #define bLSIG_Length 0x1fffe 343 #define bLSIG_Parity 0x20 344 #define bCCKRxPhase 0x4 345 #define bLSSIReadAddress 0x3f000000 /* LSSI "read" address */ 346 #define bLSSIReadEdge 0x80000000 /* LSSI "read" edge signal */ 347 #define bLSSIReadBackData 0xfff 348 #define bLSSIReadOKFlag 0x1000 349 #define bCCKSampleRate 0x8 /* 0: 44 MHz, 1: 88MHz */ 350 351 #define bRegulator0Standby 0x1 352 #define bRegulatorPLLStandby 0x2 353 #define bRegulator1Standby 0x4 354 #define bPLLPowerUp 0x8 355 #define bDPLLPowerUp 0x10 356 #define bDA10PowerUp 0x20 357 #define bAD7PowerUp 0x200 358 #define bDA6PowerUp 0x2000 359 #define bXtalPowerUp 0x4000 360 #define b40MDClkPowerUP 0x8000 361 #define bDA6DebugMode 0x20000 362 #define bDA6Swing 0x380000 363 #define bADClkPhase 0x4000000 364 #define b80MClkDelay 0x18000000 365 #define bAFEWatchDogEnable 0x20000000 366 #define bXtalCap 0x0f000000 367 #define bXtalCap01 0xc0000000 368 #define bXtalCap23 0x3 369 #define bXtalCap92x 0x0f000000 370 #define bIntDifClkEnable 0x400 371 #define bExtSigClkEnable 0x800 372 #define bBandgapMbiasPowerUp 0x10000 373 #define bAD11SHGain 0xc0000 374 #define bAD11InputRange 0x700000 375 #define bAD11OPCurrent 0x3800000 376 #define bIPathLoopback 0x4000000 377 #define bQPathLoopback 0x8000000 378 #define bAFELoopback 0x10000000 379 #define bDA10Swing 0x7e0 380 #define bDA10Reverse 0x800 381 #define bDAClkSource 0x1000 382 #define bAD7InputRange 0x6000 383 #define bAD7Gain 0x38000 384 #define bAD7OutputCMMode 0x40000 385 #define bAD7InputCMMode 0x380000 386 #define bAD7Current 0xc00000 387 #define bRegulatorAdjust 0x7000000 388 #define bAD11PowerUpAtTx 0x1 389 #define bDA10PSAtTx 0x10 390 #define bAD11PowerUpAtRx 0x100 391 #define bDA10PSAtRx 0x1000 392 393 #define bCCKRxAGCFormat 0x200 394 395 #define bPSDFFTSamplepPoint 0xc000 396 #define bPSDAverageNum 0x3000 397 #define bIQPathControl 0xc00 398 #define bPSDFreq 0x3ff 399 #define bPSDAntennaPath 0x30 400 #define bPSDIQSwitch 0x40 401 #define bPSDRxTrigger 0x400000 402 #define bPSDTxTrigger 0x80000000 403 #define bPSDSineToneScale 0x7f000000 404 #define bPSDReport 0xffff 405 406 /* Page 8 */ 407 #define bOFDMTxSC 0x30000000 408 #define bCCKTxOn 0x1 409 #define bOFDMTxOn 0x2 410 /* Reset debug page and also HWord, LWord */ 411 #define bDebugPage 0xfff 412 /* Reset debug page and LWord */ 413 #define bDebugItem 0xff 414 #define bAntL 0x10 415 #define bAntNonHT 0x100 416 #define bAntHT1 0x1000 417 #define bAntHT2 0x10000 418 #define bAntHT1S1 0x100000 419 #define bAntNonHTS1 0x1000000 420 421 /* Page a */ 422 #define bCCKBBMode 0x3 423 #define bCCKTxPowerSaving 0x80 424 #define bCCKRxPowerSaving 0x40 425 #define bCCKSideBand 0x10 426 #define bCCKScramble 0x8 427 #define bCCKAntDiversity 0x8000 428 #define bCCKCarrierRecovery 0x4000 429 #define bCCKTxRate 0x3000 430 #define bCCKDCCancel 0x0800 431 #define bCCKISICancel 0x0400 432 #define bCCKMatchFilter 0x0200 433 #define bCCKEqualizer 0x0100 434 #define bCCKPreambleDetect 0x800000 435 #define bCCKFastFalseCCA 0x400000 436 #define bCCKChEstStart 0x300000 437 #define bCCKCCACount 0x080000 438 #define bCCKcs_lim 0x070000 439 #define bCCKBistMode 0x80000000 440 #define bCCKCCAMask 0x40000000 441 #define bCCKTxDACPhase 0x4 442 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 443 #define bCCKr_cp_mode0 0x0100 444 #define bCCKTxDCOffset 0xf0 445 #define bCCKRxDCOffset 0xf 446 #define bCCKCCAMode 0xc000 447 #define bCCKFalseCS_lim 0x3f00 448 #define bCCKCS_ratio 0xc00000 449 #define bCCKCorgBit_sel 0x300000 450 #define bCCKPD_lim 0x0f0000 451 #define bCCKNewCCA 0x80000000 452 #define bCCKRxHPofIG 0x8000 453 #define bCCKRxIG 0x7f00 454 #define bCCKLNAPolarity 0x800000 455 #define bCCKRx1stGain 0x7f0000 456 /* CCK Rx Initial gain polarity */ 457 #define bCCKRFExtend 0x20000000 458 #define bCCKRxAGCSatLevel 0x1f000000 459 #define bCCKRxAGCSatCount 0xe0 460 /* AGCSAmp_dly */ 461 #define bCCKRxRFSettle 0x1f 462 #define bCCKFixedRxAGC 0x8000 463 /*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */ 464 #define bCCKAntennaPolarity 0x2000 465 #define bCCKTxFilterType 0x0c00 466 #define bCCKRxAGCReportType 0x0300 467 #define bCCKRxDAGCEn 0x80000000 468 #define bCCKRxDAGCPeriod 0x20000000 469 #define bCCKRxDAGCSatLevel 0x1f000000 470 #define bCCKTimingRecovery 0x800000 471 #define bCCKTxC0 0x3f0000 472 #define bCCKTxC1 0x3f000000 473 #define bCCKTxC2 0x3f 474 #define bCCKTxC3 0x3f00 475 #define bCCKTxC4 0x3f0000 476 #define bCCKTxC5 0x3f000000 477 #define bCCKTxC6 0x3f 478 #define bCCKTxC7 0x3f00 479 #define bCCKDebugPort 0xff0000 480 #define bCCKDACDebug 0x0f000000 481 #define bCCKFalseAlarmEnable 0x8000 482 #define bCCKFalseAlarmRead 0x4000 483 #define bCCKTRSSI 0x7f 484 #define bCCKRxAGCReport 0xfe 485 #define bCCKRxReport_AntSel 0x80000000 486 #define bCCKRxReport_MFOff 0x40000000 487 #define bCCKRxRxReport_SQLoss 0x20000000 488 #define bCCKRxReport_Pktloss 0x10000000 489 #define bCCKRxReport_Lockedbit 0x08000000 490 #define bCCKRxReport_RateError 0x04000000 491 #define bCCKRxReport_RxRate 0x03000000 492 #define bCCKRxFACounterLower 0xff 493 #define bCCKRxFACounterUpper 0xff000000 494 #define bCCKRxHPAGCStart 0xe000 495 #define bCCKRxHPAGCFinal 0x1c00 496 497 #define bCCKRxFalseAlarmEnable 0x8000 498 #define bCCKFACounterFreeze 0x4000 499 500 #define bCCKTxPathSel 0x10000000 501 #define bCCKDefaultRxPath 0xc000000 502 #define bCCKOptionRxPath 0x3000000 503 504 /* Page c */ 505 #define bNumOfSTF 0x3 506 #define bShift_L 0xc0 507 #define bGI_TH 0xc 508 #define bRxPathA 0x1 509 #define bRxPathB 0x2 510 #define bRxPathC 0x4 511 #define bRxPathD 0x8 512 #define bTxPathA 0x1 513 #define bTxPathB 0x2 514 #define bTxPathC 0x4 515 #define bTxPathD 0x8 516 #define bTRSSIFreq 0x200 517 #define bADCBackoff 0x3000 518 #define bDFIRBackoff 0xc000 519 #define bTRSSILatchPhase 0x10000 520 #define bRxIDCOffset 0xff 521 #define bRxQDCOffset 0xff00 522 #define bRxDFIRMode 0x1800000 523 #define bRxDCNFType 0xe000000 524 #define bRXIQImb_A 0x3ff 525 #define bRXIQImb_B 0xfc00 526 #define bRXIQImb_C 0x3f0000 527 #define bRXIQImb_D 0xffc00000 528 #define bDC_dc_Notch 0x60000 529 #define bRxNBINotch 0x1f000000 530 #define bPD_TH 0xf 531 #define bPD_TH_Opt2 0xc000 532 #define bPWED_TH 0x700 533 #define bIfMF_Win_L 0x800 534 #define bPD_Option 0x1000 535 #define bMF_Win_L 0xe000 536 #define bBW_Search_L 0x30000 537 #define bwin_enh_L 0xc0000 538 #define bBW_TH 0x700000 539 #define bED_TH2 0x3800000 540 #define bBW_option 0x4000000 541 #define bRatio_TH 0x18000000 542 #define bWindow_L 0xe0000000 543 #define bSBD_Option 0x1 544 #define bFrame_TH 0x1c 545 #define bFS_Option 0x60 546 #define bDC_Slope_check 0x80 547 #define bFGuard_Counter_DC_L 0xe00 548 #define bFrame_Weight_Short 0x7000 549 #define bSub_Tune 0xe00000 550 #define bFrame_DC_Length 0xe000000 551 #define bSBD_start_offset 0x30000000 552 #define bFrame_TH_2 0x7 553 #define bFrame_GI2_TH 0x38 554 #define bGI2_Sync_en 0x40 555 #define bSarch_Short_Early 0x300 556 #define bSarch_Short_Late 0xc00 557 #define bSarch_GI2_Late 0x70000 558 #define bCFOAntSum 0x1 559 #define bCFOAcc 0x2 560 #define bCFOStartOffset 0xc 561 #define bCFOLookBack 0x70 562 #define bCFOSumWeight 0x80 563 #define bDAGCEnable 0x10000 564 #define bTXIQImb_A 0x3ff 565 #define bTXIQImb_B 0xfc00 566 #define bTXIQImb_C 0x3f0000 567 #define bTXIQImb_D 0xffc00000 568 #define bTxIDCOffset 0xff 569 #define bTxQDCOffset 0xff00 570 #define bTxDFIRMode 0x10000 571 #define bTxPesudoNoiseOn 0x4000000 572 #define bTxPesudoNoise_A 0xff 573 #define bTxPesudoNoise_B 0xff00 574 #define bTxPesudoNoise_C 0xff0000 575 #define bTxPesudoNoise_D 0xff000000 576 #define bCCADropOption 0x20000 577 #define bCCADropThres 0xfff00000 578 #define bEDCCA_H 0xf 579 #define bEDCCA_L 0xf0 580 #define bLambda_ED 0x300 581 #define bRxInitialGain 0x7f 582 #define bRxAntDivEn 0x80 583 #define bRxAGCAddressForLNA 0x7f00 584 #define bRxHighPowerFlow 0x8000 585 #define bRxAGCFreezeThres 0xc0000 586 #define bRxFreezeStep_AGC1 0x300000 587 #define bRxFreezeStep_AGC2 0xc00000 588 #define bRxFreezeStep_AGC3 0x3000000 589 #define bRxFreezeStep_AGC0 0xc000000 590 #define bRxRssi_Cmp_En 0x10000000 591 #define bRxQuickAGCEn 0x20000000 592 #define bRxAGCFreezeThresMode 0x40000000 593 #define bRxOverFlowCheckType 0x80000000 594 #define bRxAGCShift 0x7f 595 #define bTRSW_Tri_Only 0x80 596 #define bPowerThres 0x300 597 #define bRxAGCEn 0x1 598 #define bRxAGCTogetherEn 0x2 599 #define bRxAGCMin 0x4 600 #define bRxHP_Ini 0x7 601 #define bRxHP_TRLNA 0x70 602 #define bRxHP_RSSI 0x700 603 #define bRxHP_BBP1 0x7000 604 #define bRxHP_BBP2 0x70000 605 #define bRxHP_BBP3 0x700000 606 /* The threshold for high power */ 607 #define bRSSI_H 0x7f0000 608 /* The threshold for ant diversity */ 609 #define bRSSI_Gen 0x7f000000 610 #define bRxSettle_TRSW 0x7 611 #define bRxSettle_LNA 0x38 612 #define bRxSettle_RSSI 0x1c0 613 #define bRxSettle_BBP 0xe00 614 #define bRxSettle_RxHP 0x7000 615 #define bRxSettle_AntSW_RSSI 0x38000 616 #define bRxSettle_AntSW 0xc0000 617 #define bRxProcessTime_DAGC 0x300000 618 #define bRxSettle_HSSI 0x400000 619 #define bRxProcessTime_BBPPW 0x800000 620 #define bRxAntennaPowerShift 0x3000000 621 #define bRSSITableSelect 0xc000000 622 #define bRxHP_Final 0x7000000 623 #define bRxHTSettle_BBP 0x7 624 #define bRxHTSettle_HSSI 0x8 625 #define bRxHTSettle_RxHP 0x70 626 #define bRxHTSettle_BBPPW 0x80 627 #define bRxHTSettle_Idle 0x300 628 #define bRxHTSettle_Reserved 0x1c00 629 #define bRxHTRxHPEn 0x8000 630 #define bRxHTAGCFreezeThres 0x30000 631 #define bRxHTAGCTogetherEn 0x40000 632 #define bRxHTAGCMin 0x80000 633 #define bRxHTAGCEn 0x100000 634 #define bRxHTDAGCEn 0x200000 635 #define bRxHTRxHP_BBP 0x1c00000 636 #define bRxHTRxHP_Final 0xe0000000 637 #define bRxPWRatioTH 0x3 638 #define bRxPWRatioEn 0x4 639 #define bRxMFHold 0x3800 640 #define bRxPD_Delay_TH1 0x38 641 #define bRxPD_Delay_TH2 0x1c0 642 #define bRxPD_DC_COUNT_MAX 0x600 643 /*#define bRxMF_Hold 0x3800*/ 644 #define bRxPD_Delay_TH 0x8000 645 #define bRxProcess_Delay 0xf0000 646 #define bRxSearchrange_GI2_Early 0x700000 647 #define bRxFrame_Guard_Counter_L 0x3800000 648 #define bRxSGI_Guard_L 0xc000000 649 #define bRxSGI_Search_L 0x30000000 650 #define bRxSGI_TH 0xc0000000 651 #define bDFSCnt0 0xff 652 #define bDFSCnt1 0xff00 653 #define bDFSFlag 0xf0000 654 655 #define bMFWeightSum 0x300000 656 #define bMinIdxTH 0x7f000000 657 658 #define bDAFormat 0x40000 659 660 #define bTxChEmuEnable 0x01000000 661 662 #define bTRSWIsolation_A 0x7f 663 #define bTRSWIsolation_B 0x7f00 664 #define bTRSWIsolation_C 0x7f0000 665 #define bTRSWIsolation_D 0x7f000000 666 667 #define bExtLNAGain 0x7c00 668 669 /* Page d */ 670 #define bSTBCEn 0x4 671 #define bAntennaMapping 0x10 672 #define bNss 0x20 673 #define bCFOAntSumD 0x200 674 #define bPHYCounterReset 0x8000000 675 #define bCFOReportGet 0x4000000 676 #define bOFDMContinueTx 0x10000000 677 #define bOFDMSingleCarrier 0x20000000 678 #define bOFDMSingleTone 0x40000000 679 /* #define bRxPath1 0x01 680 * #define bRxPath2 0x02 681 * #define bRxPath3 0x04 682 * #define bRxPath4 0x08 683 * #define bTxPath1 0x10 684 * #define bTxPath2 0x20 685 */ 686 #define bHTDetect 0x100 687 #define bCFOEn 0x10000 688 #define bCFOValue 0xfff00000 689 #define bSigTone_Re 0x3f 690 #define bSigTone_Im 0x7f00 691 #define bCounter_CCA 0xffff 692 #define bCounter_ParityFail 0xffff0000 693 #define bCounter_RateIllegal 0xffff 694 #define bCounter_CRC8Fail 0xffff0000 695 #define bCounter_MCSNoSupport 0xffff 696 #define bCounter_FastSync 0xffff 697 #define bShortCFO 0xfff 698 #define bShortCFOTLength 12 /* total */ 699 #define bShortCFOFLength 11 /* fraction */ 700 #define bLongCFO 0x7ff 701 #define bLongCFOTLength 11 702 #define bLongCFOFLength 11 703 #define bTailCFO 0x1fff 704 #define bTailCFOTLength 13 705 #define bTailCFOFLength 12 706 707 #define bmax_en_pwdB 0xffff 708 #define bCC_power_dB 0xffff0000 709 #define bnoise_pwdB 0xffff 710 #define bPowerMeasTLength 10 711 #define bPowerMeasFLength 3 712 #define bRx_HT_BW 0x1 713 #define bRxSC 0x6 714 #define bRx_HT 0x8 715 716 #define bNB_intf_det_on 0x1 717 #define bIntf_win_len_cfg 0x30 718 #define bNB_Intf_TH_cfg 0x1c0 719 720 #define bRFGain 0x3f 721 #define bTableSel 0x40 722 #define bTRSW 0x80 723 724 #define bRxSNR_A 0xff 725 #define bRxSNR_B 0xff00 726 #define bRxSNR_C 0xff0000 727 #define bRxSNR_D 0xff000000 728 #define bSNREVMTLength 8 729 #define bSNREVMFLength 1 730 731 #define bCSI1st 0xff 732 #define bCSI2nd 0xff00 733 #define bRxEVM1st 0xff0000 734 #define bRxEVM2nd 0xff000000 735 736 #define bSIGEVM 0xff 737 #define bPWDB 0xff00 738 #define bSGIEN 0x10000 739 740 #define bSFactorQAM1 0xf 741 #define bSFactorQAM2 0xf0 742 #define bSFactorQAM3 0xf00 743 #define bSFactorQAM4 0xf000 744 #define bSFactorQAM5 0xf0000 745 #define bSFactorQAM6 0xf0000 746 #define bSFactorQAM7 0xf00000 747 #define bSFactorQAM8 0xf000000 748 #define bSFactorQAM9 0xf0000000 749 #define bCSIScheme 0x100000 750 751 #define bNoiseLvlTopSet 0x3 752 #define bChSmooth 0x4 753 #define bChSmoothCfg1 0x38 754 #define bChSmoothCfg2 0x1c0 755 #define bChSmoothCfg3 0xe00 756 #define bChSmoothCfg4 0x7000 757 #define bMRCMode 0x800000 758 #define bTHEVMCfg 0x7000000 759 760 #define bLoopFitType 0x1 761 #define bUpdCFO 0x40 762 #define bUpdCFOOffData 0x80 763 #define bAdvUpdCFO 0x100 764 #define bAdvTimeCtrl 0x800 765 #define bUpdClko 0x1000 766 #define bFC 0x6000 767 #define bTrackingMode 0x8000 768 #define bPhCmpEnable 0x10000 769 #define bUpdClkoLTF 0x20000 770 #define bComChCFO 0x40000 771 #define bCSIEstiMode 0x80000 772 #define bAdvUpdEqz 0x100000 773 #define bUChCfg 0x7000000 774 #define bUpdEqz 0x8000000 775 776 /* Page e */ 777 #define bTxAGCRate18_06 0x7f7f7f7f 778 #define bTxAGCRate54_24 0x7f7f7f7f 779 #define bTxAGCRateMCS32 0x7f 780 #define bTxAGCRateCCK 0x7f00 781 #define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 782 #define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 783 #define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 784 #define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 785 786 #define bRxPesudoNoiseOn 0x20000000 /* Rx Pseduo noise */ 787 #define bRxPesudoNoise_A 0xff 788 #define bRxPesudoNoise_B 0xff00 789 #define bRxPesudoNoise_C 0xff0000 790 #define bRxPesudoNoise_D 0xff000000 791 #define bPesudoNoiseState_A 0xffff 792 #define bPesudoNoiseState_B 0xffff0000 793 #define bPesudoNoiseState_C 0xffff 794 #define bPesudoNoiseState_D 0xffff0000 795 796 /* RF Zebra 1 */ 797 #define bZebra1_HSSIEnable 0x8 798 #define bZebra1_TRxControl 0xc00 799 #define bZebra1_TRxGainSetting 0x07f 800 #define bZebra1_RxCorner 0xc00 801 #define bZebra1_TxChargePump 0x38 802 #define bZebra1_RxChargePump 0x7 803 #define bZebra1_ChannelNum 0xf80 804 #define bZebra1_TxLPFBW 0x400 805 #define bZebra1_RxLPFBW 0x600 806 807 /* Zebra4 */ 808 #define bRTL8256RegModeCtrl1 0x100 809 #define bRTL8256RegModeCtrl0 0x40 810 #define bRTL8256_TxLPFBW 0x18 811 #define bRTL8256_RxLPFBW 0x600 812 813 /* RTL8258 */ 814 #define bRTL8258_TxLPFBW 0xc 815 #define bRTL8258_RxLPFBW 0xc00 816 #define bRTL8258_RSSILPFBW 0xc0 817 818 /* byte enable for sb_write */ 819 #define bByte0 0x1 820 #define bByte1 0x2 821 #define bByte2 0x4 822 #define bByte3 0x8 823 #define bWord0 0x3 824 #define bWord1 0xc 825 #define bDWord 0xf 826 827 /* for PutRegsetting & GetRegSetting BitMask */ 828 #define bMaskByte0 0xff 829 #define bMaskByte1 0xff00 830 #define bMaskByte2 0xff0000 831 #define bMaskByte3 0xff000000 832 #define bMaskHWord 0xffff0000 833 #define bMaskLWord 0x0000ffff 834 #define bMaskDWord 0xffffffff 835 836 /* for PutRFRegsetting & GetRFRegSetting BitMask */ 837 #define bMask12Bits 0xfff 838 839 #define bEnable 0x1 840 #define bDisable 0x0 841 842 #define LeftAntenna 0x0 843 #define RightAntenna 0x1 844 845 #define tCheckTxStatus 500 /* 500 ms */ 846 #define tUpdateRxCounter 100 /* 100 ms */ 847 848 #define rateCCK 0 849 #define rateOFDM 1 850 #define rateHT 2 851 852 #define bPMAC_End 0x1ff /* define Register-End */ 853 #define bFPGAPHY0_End 0x8ff 854 #define bFPGAPHY1_End 0x9ff 855 #define bCCKPHY0_End 0xaff 856 #define bOFDMPHY0_End 0xcff 857 #define bOFDMPHY1_End 0xdff 858 859 860 #define bPMACControl 0x0 861 #define bWMACControl 0x1 862 #define bWNICControl 0x2 863 864 #define PathA 0x0 865 #define PathB 0x1 866 #define PathC 0x2 867 #define PathD 0x3 868 869 #define rRTL8256RxMixerPole 0xb 870 #define bZebraRxMixerPole 0x6 871 #define rRTL8256TxBBOPBias 0x9 872 #define bRTL8256TxBBOPBias 0x400 873 #define rRTL8256TxBBBW 19 874 #define bRTL8256TxBBBW 0x18 875 876 #endif 877