1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_cortex.h
4 * @author MCD Application Team
5 * @brief Header file of CORTEX LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL CORTEX driver contains a set of generic APIs that can be
12 used by user:
13 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
14 functions
15 (+) Low power mode configuration (SCB register of Cortex-MCU)
16 (+) API to access to MCU info (CPUID register)
17
18 @endverbatim
19 ******************************************************************************
20 * @attention
21 *
22 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
23 *
24 * Redistribution and use in source and binary forms, with or without modification,
25 * are permitted provided that the following conditions are met:
26 * 1. Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.
28 * 2. Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials provided with the distribution.
31 * 3. Neither the name of STMicroelectronics nor the names of its contributors
32 * may be used to endorse or promote products derived from this software
33 * without specific prior written permission.
34 *
35 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
36 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
38 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
41 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
42 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
43 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 *
46 ******************************************************************************
47 */
48
49 /* Define to prevent recursive inclusion -------------------------------------*/
50 #ifndef __STM32F0xx_LL_CORTEX_H
51 #define __STM32F0xx_LL_CORTEX_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif
56
57 /* Includes ------------------------------------------------------------------*/
58 #include "stm32f0xx.h"
59
60 /** @addtogroup STM32F0xx_LL_Driver
61 * @{
62 */
63
64 /** @defgroup CORTEX_LL CORTEX
65 * @{
66 */
67
68 /* Private types -------------------------------------------------------------*/
69 /* Private variables ---------------------------------------------------------*/
70
71 /* Private constants ---------------------------------------------------------*/
72
73 /* Private macros ------------------------------------------------------------*/
74
75 /* Exported types ------------------------------------------------------------*/
76 /* Exported constants --------------------------------------------------------*/
77 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
78 * @{
79 */
80
81 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
82 * @{
83 */
84 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
85 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
86 /**
87 * @}
88 */
89
90 /**
91 * @}
92 */
93
94 /* Exported macro ------------------------------------------------------------*/
95
96 /* Exported functions --------------------------------------------------------*/
97 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
98 * @{
99 */
100
101 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
102 * @{
103 */
104
105 /**
106 * @brief This function checks if the Systick counter flag is active or not.
107 * @note It can be used in timeout function on application side.
108 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
109 * @retval State of bit (1 or 0).
110 */
LL_SYSTICK_IsActiveCounterFlag(void)111 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
112 {
113 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
114 }
115
116 /**
117 * @brief Configures the SysTick clock source
118 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
119 * @param Source This parameter can be one of the following values:
120 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
121 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
122 * @retval None
123 */
LL_SYSTICK_SetClkSource(uint32_t Source)124 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
125 {
126 if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
127 {
128 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
129 }
130 else
131 {
132 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
133 }
134 }
135
136 /**
137 * @brief Get the SysTick clock source
138 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
139 * @retval Returned value can be one of the following values:
140 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
141 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
142 */
LL_SYSTICK_GetClkSource(void)143 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
144 {
145 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
146 }
147
148 /**
149 * @brief Enable SysTick exception request
150 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
151 * @retval None
152 */
LL_SYSTICK_EnableIT(void)153 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
154 {
155 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
156 }
157
158 /**
159 * @brief Disable SysTick exception request
160 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
161 * @retval None
162 */
LL_SYSTICK_DisableIT(void)163 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
164 {
165 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
166 }
167
168 /**
169 * @brief Checks if the SYSTICK interrupt is enabled or disabled.
170 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
171 * @retval State of bit (1 or 0).
172 */
LL_SYSTICK_IsEnabledIT(void)173 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
174 {
175 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
176 }
177
178 /**
179 * @}
180 */
181
182 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
183 * @{
184 */
185
186 /**
187 * @brief Processor uses sleep as its low power mode
188 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
189 * @retval None
190 */
LL_LPM_EnableSleep(void)191 __STATIC_INLINE void LL_LPM_EnableSleep(void)
192 {
193 /* Clear SLEEPDEEP bit of Cortex System Control Register */
194 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
195 }
196
197 /**
198 * @brief Processor uses deep sleep as its low power mode
199 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
200 * @retval None
201 */
LL_LPM_EnableDeepSleep(void)202 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
203 {
204 /* Set SLEEPDEEP bit of Cortex System Control Register */
205 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
206 }
207
208 /**
209 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
210 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
211 * empty main application.
212 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
213 * @retval None
214 */
LL_LPM_EnableSleepOnExit(void)215 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
216 {
217 /* Set SLEEPONEXIT bit of Cortex System Control Register */
218 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
219 }
220
221 /**
222 * @brief Do not sleep when returning to Thread mode.
223 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
224 * @retval None
225 */
LL_LPM_DisableSleepOnExit(void)226 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
227 {
228 /* Clear SLEEPONEXIT bit of Cortex System Control Register */
229 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
230 }
231
232 /**
233 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
234 * processor.
235 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
236 * @retval None
237 */
LL_LPM_EnableEventOnPend(void)238 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
239 {
240 /* Set SEVEONPEND bit of Cortex System Control Register */
241 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
242 }
243
244 /**
245 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
246 * excluded
247 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
248 * @retval None
249 */
LL_LPM_DisableEventOnPend(void)250 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
251 {
252 /* Clear SEVEONPEND bit of Cortex System Control Register */
253 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
254 }
255
256 /**
257 * @}
258 */
259
260 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
261 * @{
262 */
263
264 /**
265 * @brief Get Implementer code
266 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
267 * @retval Value should be equal to 0x41 for ARM
268 */
LL_CPUID_GetImplementer(void)269 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
270 {
271 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
272 }
273
274 /**
275 * @brief Get Variant number (The r value in the rnpn product revision identifier)
276 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
277 * @retval Value between 0 and 255 (0x0: revision 0)
278 */
LL_CPUID_GetVariant(void)279 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
280 {
281 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
282 }
283
284 /**
285 * @brief Get Architecture number
286 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
287 * @retval Value should be equal to 0xC for Cortex-M0 devices
288 */
LL_CPUID_GetArchitecture(void)289 __STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
290 {
291 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
292 }
293
294 /**
295 * @brief Get Part number
296 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
297 * @retval Value should be equal to 0xC20 for Cortex-M0
298 */
LL_CPUID_GetParNo(void)299 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
300 {
301 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
302 }
303
304 /**
305 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
306 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
307 * @retval Value between 0 and 255 (0x1: patch 1)
308 */
LL_CPUID_GetRevision(void)309 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
310 {
311 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
312 }
313
314 /**
315 * @}
316 */
317
318 /**
319 * @}
320 */
321
322 /**
323 * @}
324 */
325
326 /**
327 * @}
328 */
329
330 #ifdef __cplusplus
331 }
332 #endif
333
334 #endif /* __STM32F0xx_LL_CORTEX_H */
335
336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
337