1 /** 2 ****************************************************************************** 3 * @file stm32f10x_tim.h 4 * @author MCD Application Team 5 * @version V3.4.0 6 * @date 10/15/2010 7 * @brief This file contains all the functions prototypes for the TIM firmware 8 * library. 9 ****************************************************************************** 10 * @copy 11 * 12 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 * 19 * <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2> 20 */ 21 22 /* Define to prevent recursive inclusion -------------------------------------*/ 23 #ifndef __STM32F10x_TIM_H 24 #define __STM32F10x_TIM_H 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32f10x.h" 32 33 /** @addtogroup STM32F10x_StdPeriph_Driver 34 * @{ 35 */ 36 37 /** @addtogroup TIM 38 * @{ 39 */ 40 41 /** @defgroup TIM_Exported_Types 42 * @{ 43 */ 44 45 /** 46 * @brief TIM Time Base Init structure definition 47 * @note This sturcture is used with all TIMx except for TIM6 and TIM7. 48 */ 49 50 typedef struct 51 { 52 uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 53 This parameter can be a number between 0x0000 and 0xFFFF */ 54 55 uint16_t TIM_CounterMode; /*!< Specifies the counter mode. 56 This parameter can be a value of @ref TIM_Counter_Mode */ 57 58 uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active 59 Auto-Reload Register at the next update event. 60 This parameter must be a number between 0x0000 and 0xFFFF. */ 61 62 uint16_t TIM_ClockDivision; /*!< Specifies the clock division. 63 This parameter can be a value of @ref TIM_Clock_Division_CKD */ 64 65 uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 66 reaches zero, an update event is generated and counting restarts 67 from the RCR value (N). 68 This means in PWM mode that (N+1) corresponds to: 69 - the number of PWM periods in edge-aligned mode 70 - the number of half PWM period in center-aligned mode 71 This parameter must be a number between 0x00 and 0xFF. 72 @note This parameter is valid only for TIM1 and TIM8. */ 73 } TIM_TimeBaseInitTypeDef; 74 75 /** 76 * @brief TIM Output Compare Init structure definition 77 */ 78 79 typedef struct 80 { 81 uint16_t TIM_OCMode; /*!< Specifies the TIM mode. 82 This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ 83 84 uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. 85 This parameter can be a value of @ref TIM_Output_Compare_state */ 86 87 uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. 88 This parameter can be a value of @ref TIM_Output_Compare_N_state 89 @note This parameter is valid only for TIM1 and TIM8. */ 90 91 uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 92 This parameter can be a number between 0x0000 and 0xFFFF */ 93 94 uint16_t TIM_OCPolarity; /*!< Specifies the output polarity. 95 This parameter can be a value of @ref TIM_Output_Compare_Polarity */ 96 97 uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. 98 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity 99 @note This parameter is valid only for TIM1 and TIM8. */ 100 101 uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 102 This parameter can be a value of @ref TIM_Output_Compare_Idle_State 103 @note This parameter is valid only for TIM1 and TIM8. */ 104 105 uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 106 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State 107 @note This parameter is valid only for TIM1 and TIM8. */ 108 } TIM_OCInitTypeDef; 109 110 /** 111 * @brief TIM Input Capture Init structure definition 112 */ 113 114 typedef struct 115 { 116 117 uint16_t TIM_Channel; /*!< Specifies the TIM channel. 118 This parameter can be a value of @ref TIM_Channel */ 119 120 uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. 121 This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 122 123 uint16_t TIM_ICSelection; /*!< Specifies the input. 124 This parameter can be a value of @ref TIM_Input_Capture_Selection */ 125 126 uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. 127 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 128 129 uint16_t TIM_ICFilter; /*!< Specifies the input capture filter. 130 This parameter can be a number between 0x0 and 0xF */ 131 } TIM_ICInitTypeDef; 132 133 /** 134 * @brief BDTR structure definition 135 * @note This sturcture is used only with TIM1 and TIM8. 136 */ 137 138 typedef struct 139 { 140 141 uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. 142 This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ 143 144 uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. 145 This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ 146 147 uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. 148 This parameter can be a value of @ref Lock_level */ 149 150 uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the 151 switching-on of the outputs. 152 This parameter can be a number between 0x00 and 0xFF */ 153 154 uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. 155 This parameter can be a value of @ref Break_Input_enable_disable */ 156 157 uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 158 This parameter can be a value of @ref Break_Polarity */ 159 160 uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 161 This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ 162 } TIM_BDTRInitTypeDef; 163 164 /** @defgroup TIM_Exported_constants 165 * @{ 166 */ 167 168 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 169 ((PERIPH) == TIM2) || \ 170 ((PERIPH) == TIM3) || \ 171 ((PERIPH) == TIM4) || \ 172 ((PERIPH) == TIM5) || \ 173 ((PERIPH) == TIM6) || \ 174 ((PERIPH) == TIM7) || \ 175 ((PERIPH) == TIM8) || \ 176 ((PERIPH) == TIM9) || \ 177 ((PERIPH) == TIM10)|| \ 178 ((PERIPH) == TIM11)|| \ 179 ((PERIPH) == TIM12)|| \ 180 ((PERIPH) == TIM13)|| \ 181 ((PERIPH) == TIM14)|| \ 182 ((PERIPH) == TIM15)|| \ 183 ((PERIPH) == TIM16)|| \ 184 ((PERIPH) == TIM17)) 185 186 /* LIST1: TIM 1 and 8 */ 187 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 188 ((PERIPH) == TIM8)) 189 190 /* LIST2: TIM 1, 8, 15 16 and 17 */ 191 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 192 ((PERIPH) == TIM8) || \ 193 ((PERIPH) == TIM15)|| \ 194 ((PERIPH) == TIM16)|| \ 195 ((PERIPH) == TIM17)) 196 197 /* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ 198 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 199 ((PERIPH) == TIM2) || \ 200 ((PERIPH) == TIM3) || \ 201 ((PERIPH) == TIM4) || \ 202 ((PERIPH) == TIM5) || \ 203 ((PERIPH) == TIM8)) 204 205 /* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */ 206 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 207 ((PERIPH) == TIM2) || \ 208 ((PERIPH) == TIM3) || \ 209 ((PERIPH) == TIM4) || \ 210 ((PERIPH) == TIM5) || \ 211 ((PERIPH) == TIM8) || \ 212 ((PERIPH) == TIM15)|| \ 213 ((PERIPH) == TIM16)|| \ 214 ((PERIPH) == TIM17)) 215 216 /* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */ 217 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 218 ((PERIPH) == TIM2) || \ 219 ((PERIPH) == TIM3) || \ 220 ((PERIPH) == TIM4) || \ 221 ((PERIPH) == TIM5) || \ 222 ((PERIPH) == TIM8) || \ 223 ((PERIPH) == TIM15)) 224 225 /* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */ 226 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 227 ((PERIPH) == TIM2) || \ 228 ((PERIPH) == TIM3) || \ 229 ((PERIPH) == TIM4) || \ 230 ((PERIPH) == TIM5) || \ 231 ((PERIPH) == TIM8) || \ 232 ((PERIPH) == TIM9) || \ 233 ((PERIPH) == TIM12)|| \ 234 ((PERIPH) == TIM15)) 235 236 /* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */ 237 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 238 ((PERIPH) == TIM2) || \ 239 ((PERIPH) == TIM3) || \ 240 ((PERIPH) == TIM4) || \ 241 ((PERIPH) == TIM5) || \ 242 ((PERIPH) == TIM6) || \ 243 ((PERIPH) == TIM7) || \ 244 ((PERIPH) == TIM8) || \ 245 ((PERIPH) == TIM9) || \ 246 ((PERIPH) == TIM12)|| \ 247 ((PERIPH) == TIM15)) 248 249 /* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */ 250 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 251 ((PERIPH) == TIM2) || \ 252 ((PERIPH) == TIM3) || \ 253 ((PERIPH) == TIM4) || \ 254 ((PERIPH) == TIM5) || \ 255 ((PERIPH) == TIM8) || \ 256 ((PERIPH) == TIM9) || \ 257 ((PERIPH) == TIM10)|| \ 258 ((PERIPH) == TIM11)|| \ 259 ((PERIPH) == TIM12)|| \ 260 ((PERIPH) == TIM13)|| \ 261 ((PERIPH) == TIM14)|| \ 262 ((PERIPH) == TIM15)|| \ 263 ((PERIPH) == TIM16)|| \ 264 ((PERIPH) == TIM17)) 265 266 /* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */ 267 #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ 268 ((PERIPH) == TIM2) || \ 269 ((PERIPH) == TIM3) || \ 270 ((PERIPH) == TIM4) || \ 271 ((PERIPH) == TIM5) || \ 272 ((PERIPH) == TIM6) || \ 273 ((PERIPH) == TIM7) || \ 274 ((PERIPH) == TIM8) || \ 275 ((PERIPH) == TIM15)|| \ 276 ((PERIPH) == TIM16)|| \ 277 ((PERIPH) == TIM17)) 278 279 /** 280 * @} 281 */ 282 283 /** @defgroup TIM_Output_Compare_and_PWM_modes 284 * @{ 285 */ 286 287 #define TIM_OCMode_Timing ((uint16_t)0x0000) 288 #define TIM_OCMode_Active ((uint16_t)0x0010) 289 #define TIM_OCMode_Inactive ((uint16_t)0x0020) 290 #define TIM_OCMode_Toggle ((uint16_t)0x0030) 291 #define TIM_OCMode_PWM1 ((uint16_t)0x0060) 292 #define TIM_OCMode_PWM2 ((uint16_t)0x0070) 293 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \ 294 ((MODE) == TIM_OCMode_Active) || \ 295 ((MODE) == TIM_OCMode_Inactive) || \ 296 ((MODE) == TIM_OCMode_Toggle)|| \ 297 ((MODE) == TIM_OCMode_PWM1) || \ 298 ((MODE) == TIM_OCMode_PWM2)) 299 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \ 300 ((MODE) == TIM_OCMode_Active) || \ 301 ((MODE) == TIM_OCMode_Inactive) || \ 302 ((MODE) == TIM_OCMode_Toggle)|| \ 303 ((MODE) == TIM_OCMode_PWM1) || \ 304 ((MODE) == TIM_OCMode_PWM2) || \ 305 ((MODE) == TIM_ForcedAction_Active) || \ 306 ((MODE) == TIM_ForcedAction_InActive)) 307 /** 308 * @} 309 */ 310 311 /** @defgroup TIM_One_Pulse_Mode 312 * @{ 313 */ 314 315 #define TIM_OPMode_Single ((uint16_t)0x0008) 316 #define TIM_OPMode_Repetitive ((uint16_t)0x0000) 317 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \ 318 ((MODE) == TIM_OPMode_Repetitive)) 319 /** 320 * @} 321 */ 322 323 /** @defgroup TIM_Channel 324 * @{ 325 */ 326 327 #define TIM_Channel_1 ((uint16_t)0x0000) 328 #define TIM_Channel_2 ((uint16_t)0x0004) 329 #define TIM_Channel_3 ((uint16_t)0x0008) 330 #define TIM_Channel_4 ((uint16_t)0x000C) 331 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 332 ((CHANNEL) == TIM_Channel_2) || \ 333 ((CHANNEL) == TIM_Channel_3) || \ 334 ((CHANNEL) == TIM_Channel_4)) 335 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 336 ((CHANNEL) == TIM_Channel_2)) 337 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ 338 ((CHANNEL) == TIM_Channel_2) || \ 339 ((CHANNEL) == TIM_Channel_3)) 340 /** 341 * @} 342 */ 343 344 /** @defgroup TIM_Clock_Division_CKD 345 * @{ 346 */ 347 348 #define TIM_CKD_DIV1 ((uint16_t)0x0000) 349 #define TIM_CKD_DIV2 ((uint16_t)0x0100) 350 #define TIM_CKD_DIV4 ((uint16_t)0x0200) 351 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ 352 ((DIV) == TIM_CKD_DIV2) || \ 353 ((DIV) == TIM_CKD_DIV4)) 354 /** 355 * @} 356 */ 357 358 /** @defgroup TIM_Counter_Mode 359 * @{ 360 */ 361 362 #define TIM_CounterMode_Up ((uint16_t)0x0000) 363 #define TIM_CounterMode_Down ((uint16_t)0x0010) 364 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) 365 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) 366 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) 367 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \ 368 ((MODE) == TIM_CounterMode_Down) || \ 369 ((MODE) == TIM_CounterMode_CenterAligned1) || \ 370 ((MODE) == TIM_CounterMode_CenterAligned2) || \ 371 ((MODE) == TIM_CounterMode_CenterAligned3)) 372 /** 373 * @} 374 */ 375 376 /** @defgroup TIM_Output_Compare_Polarity 377 * @{ 378 */ 379 380 #define TIM_OCPolarity_High ((uint16_t)0x0000) 381 #define TIM_OCPolarity_Low ((uint16_t)0x0002) 382 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ 383 ((POLARITY) == TIM_OCPolarity_Low)) 384 /** 385 * @} 386 */ 387 388 /** @defgroup TIM_Output_Compare_N_Polarity 389 * @{ 390 */ 391 392 #define TIM_OCNPolarity_High ((uint16_t)0x0000) 393 #define TIM_OCNPolarity_Low ((uint16_t)0x0008) 394 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ 395 ((POLARITY) == TIM_OCNPolarity_Low)) 396 /** 397 * @} 398 */ 399 400 /** @defgroup TIM_Output_Compare_state 401 * @{ 402 */ 403 404 #define TIM_OutputState_Disable ((uint16_t)0x0000) 405 #define TIM_OutputState_Enable ((uint16_t)0x0001) 406 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ 407 ((STATE) == TIM_OutputState_Enable)) 408 /** 409 * @} 410 */ 411 412 /** @defgroup TIM_Output_Compare_N_state 413 * @{ 414 */ 415 416 #define TIM_OutputNState_Disable ((uint16_t)0x0000) 417 #define TIM_OutputNState_Enable ((uint16_t)0x0004) 418 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ 419 ((STATE) == TIM_OutputNState_Enable)) 420 /** 421 * @} 422 */ 423 424 /** @defgroup TIM_Capture_Compare_state 425 * @{ 426 */ 427 428 #define TIM_CCx_Enable ((uint16_t)0x0001) 429 #define TIM_CCx_Disable ((uint16_t)0x0000) 430 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \ 431 ((CCX) == TIM_CCx_Disable)) 432 /** 433 * @} 434 */ 435 436 /** @defgroup TIM_Capture_Compare_N_state 437 * @{ 438 */ 439 440 #define TIM_CCxN_Enable ((uint16_t)0x0004) 441 #define TIM_CCxN_Disable ((uint16_t)0x0000) 442 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \ 443 ((CCXN) == TIM_CCxN_Disable)) 444 /** 445 * @} 446 */ 447 448 /** @defgroup Break_Input_enable_disable 449 * @{ 450 */ 451 452 #define TIM_Break_Enable ((uint16_t)0x1000) 453 #define TIM_Break_Disable ((uint16_t)0x0000) 454 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \ 455 ((STATE) == TIM_Break_Disable)) 456 /** 457 * @} 458 */ 459 460 /** @defgroup Break_Polarity 461 * @{ 462 */ 463 464 #define TIM_BreakPolarity_Low ((uint16_t)0x0000) 465 #define TIM_BreakPolarity_High ((uint16_t)0x2000) 466 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \ 467 ((POLARITY) == TIM_BreakPolarity_High)) 468 /** 469 * @} 470 */ 471 472 /** @defgroup TIM_AOE_Bit_Set_Reset 473 * @{ 474 */ 475 476 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) 477 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) 478 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \ 479 ((STATE) == TIM_AutomaticOutput_Disable)) 480 /** 481 * @} 482 */ 483 484 /** @defgroup Lock_level 485 * @{ 486 */ 487 488 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000) 489 #define TIM_LOCKLevel_1 ((uint16_t)0x0100) 490 #define TIM_LOCKLevel_2 ((uint16_t)0x0200) 491 #define TIM_LOCKLevel_3 ((uint16_t)0x0300) 492 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ 493 ((LEVEL) == TIM_LOCKLevel_1) || \ 494 ((LEVEL) == TIM_LOCKLevel_2) || \ 495 ((LEVEL) == TIM_LOCKLevel_3)) 496 /** 497 * @} 498 */ 499 500 /** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state 501 * @{ 502 */ 503 504 #define TIM_OSSIState_Enable ((uint16_t)0x0400) 505 #define TIM_OSSIState_Disable ((uint16_t)0x0000) 506 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \ 507 ((STATE) == TIM_OSSIState_Disable)) 508 /** 509 * @} 510 */ 511 512 /** @defgroup OSSR_Off_State_Selection_for_Run_mode_state 513 * @{ 514 */ 515 516 #define TIM_OSSRState_Enable ((uint16_t)0x0800) 517 #define TIM_OSSRState_Disable ((uint16_t)0x0000) 518 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \ 519 ((STATE) == TIM_OSSRState_Disable)) 520 /** 521 * @} 522 */ 523 524 /** @defgroup TIM_Output_Compare_Idle_State 525 * @{ 526 */ 527 528 #define TIM_OCIdleState_Set ((uint16_t)0x0100) 529 #define TIM_OCIdleState_Reset ((uint16_t)0x0000) 530 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \ 531 ((STATE) == TIM_OCIdleState_Reset)) 532 /** 533 * @} 534 */ 535 536 /** @defgroup TIM_Output_Compare_N_Idle_State 537 * @{ 538 */ 539 540 #define TIM_OCNIdleState_Set ((uint16_t)0x0200) 541 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000) 542 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \ 543 ((STATE) == TIM_OCNIdleState_Reset)) 544 /** 545 * @} 546 */ 547 548 /** @defgroup TIM_Input_Capture_Polarity 549 * @{ 550 */ 551 552 #define TIM_ICPolarity_Rising ((uint16_t)0x0000) 553 #define TIM_ICPolarity_Falling ((uint16_t)0x0002) 554 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) 555 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 556 ((POLARITY) == TIM_ICPolarity_Falling)) 557 #define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \ 558 ((POLARITY) == TIM_ICPolarity_Falling)|| \ 559 ((POLARITY) == TIM_ICPolarity_BothEdge)) 560 /** 561 * @} 562 */ 563 564 /** @defgroup TIM_Input_Capture_Selection 565 * @{ 566 */ 567 568 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 569 connected to IC1, IC2, IC3 or IC4, respectively */ 570 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be 571 connected to IC2, IC1, IC4 or IC3, respectively. */ 572 #define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ 573 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \ 574 ((SELECTION) == TIM_ICSelection_IndirectTI) || \ 575 ((SELECTION) == TIM_ICSelection_TRC)) 576 /** 577 * @} 578 */ 579 580 /** @defgroup TIM_Input_Capture_Prescaler 581 * @{ 582 */ 583 584 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */ 585 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */ 586 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */ 587 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */ 588 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ 589 ((PRESCALER) == TIM_ICPSC_DIV2) || \ 590 ((PRESCALER) == TIM_ICPSC_DIV4) || \ 591 ((PRESCALER) == TIM_ICPSC_DIV8)) 592 /** 593 * @} 594 */ 595 596 /** @defgroup TIM_interrupt_sources 597 * @{ 598 */ 599 600 #define TIM_IT_Update ((uint16_t)0x0001) 601 #define TIM_IT_CC1 ((uint16_t)0x0002) 602 #define TIM_IT_CC2 ((uint16_t)0x0004) 603 #define TIM_IT_CC3 ((uint16_t)0x0008) 604 #define TIM_IT_CC4 ((uint16_t)0x0010) 605 #define TIM_IT_COM ((uint16_t)0x0020) 606 #define TIM_IT_Trigger ((uint16_t)0x0040) 607 #define TIM_IT_Break ((uint16_t)0x0080) 608 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000)) 609 610 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \ 611 ((IT) == TIM_IT_CC1) || \ 612 ((IT) == TIM_IT_CC2) || \ 613 ((IT) == TIM_IT_CC3) || \ 614 ((IT) == TIM_IT_CC4) || \ 615 ((IT) == TIM_IT_COM) || \ 616 ((IT) == TIM_IT_Trigger) || \ 617 ((IT) == TIM_IT_Break)) 618 /** 619 * @} 620 */ 621 622 /** @defgroup TIM_DMA_Base_address 623 * @{ 624 */ 625 626 #define TIM_DMABase_CR1 ((uint16_t)0x0000) 627 #define TIM_DMABase_CR2 ((uint16_t)0x0001) 628 #define TIM_DMABase_SMCR ((uint16_t)0x0002) 629 #define TIM_DMABase_DIER ((uint16_t)0x0003) 630 #define TIM_DMABase_SR ((uint16_t)0x0004) 631 #define TIM_DMABase_EGR ((uint16_t)0x0005) 632 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006) 633 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007) 634 #define TIM_DMABase_CCER ((uint16_t)0x0008) 635 #define TIM_DMABase_CNT ((uint16_t)0x0009) 636 #define TIM_DMABase_PSC ((uint16_t)0x000A) 637 #define TIM_DMABase_ARR ((uint16_t)0x000B) 638 #define TIM_DMABase_RCR ((uint16_t)0x000C) 639 #define TIM_DMABase_CCR1 ((uint16_t)0x000D) 640 #define TIM_DMABase_CCR2 ((uint16_t)0x000E) 641 #define TIM_DMABase_CCR3 ((uint16_t)0x000F) 642 #define TIM_DMABase_CCR4 ((uint16_t)0x0010) 643 #define TIM_DMABase_BDTR ((uint16_t)0x0011) 644 #define TIM_DMABase_DCR ((uint16_t)0x0012) 645 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ 646 ((BASE) == TIM_DMABase_CR2) || \ 647 ((BASE) == TIM_DMABase_SMCR) || \ 648 ((BASE) == TIM_DMABase_DIER) || \ 649 ((BASE) == TIM_DMABase_SR) || \ 650 ((BASE) == TIM_DMABase_EGR) || \ 651 ((BASE) == TIM_DMABase_CCMR1) || \ 652 ((BASE) == TIM_DMABase_CCMR2) || \ 653 ((BASE) == TIM_DMABase_CCER) || \ 654 ((BASE) == TIM_DMABase_CNT) || \ 655 ((BASE) == TIM_DMABase_PSC) || \ 656 ((BASE) == TIM_DMABase_ARR) || \ 657 ((BASE) == TIM_DMABase_RCR) || \ 658 ((BASE) == TIM_DMABase_CCR1) || \ 659 ((BASE) == TIM_DMABase_CCR2) || \ 660 ((BASE) == TIM_DMABase_CCR3) || \ 661 ((BASE) == TIM_DMABase_CCR4) || \ 662 ((BASE) == TIM_DMABase_BDTR) || \ 663 ((BASE) == TIM_DMABase_DCR)) 664 /** 665 * @} 666 */ 667 668 /** @defgroup TIM_DMA_Burst_Length 669 * @{ 670 */ 671 672 #define TIM_DMABurstLength_1Byte ((uint16_t)0x0000) 673 #define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100) 674 #define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200) 675 #define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300) 676 #define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400) 677 #define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500) 678 #define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600) 679 #define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700) 680 #define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800) 681 #define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900) 682 #define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00) 683 #define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00) 684 #define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00) 685 #define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00) 686 #define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00) 687 #define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00) 688 #define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000) 689 #define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100) 690 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \ 691 ((LENGTH) == TIM_DMABurstLength_2Bytes) || \ 692 ((LENGTH) == TIM_DMABurstLength_3Bytes) || \ 693 ((LENGTH) == TIM_DMABurstLength_4Bytes) || \ 694 ((LENGTH) == TIM_DMABurstLength_5Bytes) || \ 695 ((LENGTH) == TIM_DMABurstLength_6Bytes) || \ 696 ((LENGTH) == TIM_DMABurstLength_7Bytes) || \ 697 ((LENGTH) == TIM_DMABurstLength_8Bytes) || \ 698 ((LENGTH) == TIM_DMABurstLength_9Bytes) || \ 699 ((LENGTH) == TIM_DMABurstLength_10Bytes) || \ 700 ((LENGTH) == TIM_DMABurstLength_11Bytes) || \ 701 ((LENGTH) == TIM_DMABurstLength_12Bytes) || \ 702 ((LENGTH) == TIM_DMABurstLength_13Bytes) || \ 703 ((LENGTH) == TIM_DMABurstLength_14Bytes) || \ 704 ((LENGTH) == TIM_DMABurstLength_15Bytes) || \ 705 ((LENGTH) == TIM_DMABurstLength_16Bytes) || \ 706 ((LENGTH) == TIM_DMABurstLength_17Bytes) || \ 707 ((LENGTH) == TIM_DMABurstLength_18Bytes)) 708 /** 709 * @} 710 */ 711 712 /** @defgroup TIM_DMA_sources 713 * @{ 714 */ 715 716 #define TIM_DMA_Update ((uint16_t)0x0100) 717 #define TIM_DMA_CC1 ((uint16_t)0x0200) 718 #define TIM_DMA_CC2 ((uint16_t)0x0400) 719 #define TIM_DMA_CC3 ((uint16_t)0x0800) 720 #define TIM_DMA_CC4 ((uint16_t)0x1000) 721 #define TIM_DMA_COM ((uint16_t)0x2000) 722 #define TIM_DMA_Trigger ((uint16_t)0x4000) 723 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000)) 724 725 /** 726 * @} 727 */ 728 729 /** @defgroup TIM_External_Trigger_Prescaler 730 * @{ 731 */ 732 733 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) 734 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) 735 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) 736 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) 737 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \ 738 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ 739 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ 740 ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) 741 /** 742 * @} 743 */ 744 745 /** @defgroup TIM_Internal_Trigger_Selection 746 * @{ 747 */ 748 749 #define TIM_TS_ITR0 ((uint16_t)0x0000) 750 #define TIM_TS_ITR1 ((uint16_t)0x0010) 751 #define TIM_TS_ITR2 ((uint16_t)0x0020) 752 #define TIM_TS_ITR3 ((uint16_t)0x0030) 753 #define TIM_TS_TI1F_ED ((uint16_t)0x0040) 754 #define TIM_TS_TI1FP1 ((uint16_t)0x0050) 755 #define TIM_TS_TI2FP2 ((uint16_t)0x0060) 756 #define TIM_TS_ETRF ((uint16_t)0x0070) 757 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 758 ((SELECTION) == TIM_TS_ITR1) || \ 759 ((SELECTION) == TIM_TS_ITR2) || \ 760 ((SELECTION) == TIM_TS_ITR3) || \ 761 ((SELECTION) == TIM_TS_TI1F_ED) || \ 762 ((SELECTION) == TIM_TS_TI1FP1) || \ 763 ((SELECTION) == TIM_TS_TI2FP2) || \ 764 ((SELECTION) == TIM_TS_ETRF)) 765 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ 766 ((SELECTION) == TIM_TS_ITR1) || \ 767 ((SELECTION) == TIM_TS_ITR2) || \ 768 ((SELECTION) == TIM_TS_ITR3)) 769 /** 770 * @} 771 */ 772 773 /** @defgroup TIM_TIx_External_Clock_Source 774 * @{ 775 */ 776 777 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) 778 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) 779 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) 780 #define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \ 781 ((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \ 782 ((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED)) 783 /** 784 * @} 785 */ 786 787 /** @defgroup TIM_External_Trigger_Polarity 788 * @{ 789 */ 790 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) 791 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) 792 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \ 793 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) 794 /** 795 * @} 796 */ 797 798 /** @defgroup TIM_Prescaler_Reload_Mode 799 * @{ 800 */ 801 802 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000) 803 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) 804 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \ 805 ((RELOAD) == TIM_PSCReloadMode_Immediate)) 806 /** 807 * @} 808 */ 809 810 /** @defgroup TIM_Forced_Action 811 * @{ 812 */ 813 814 #define TIM_ForcedAction_Active ((uint16_t)0x0050) 815 #define TIM_ForcedAction_InActive ((uint16_t)0x0040) 816 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \ 817 ((ACTION) == TIM_ForcedAction_InActive)) 818 /** 819 * @} 820 */ 821 822 /** @defgroup TIM_Encoder_Mode 823 * @{ 824 */ 825 826 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001) 827 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002) 828 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003) 829 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \ 830 ((MODE) == TIM_EncoderMode_TI2) || \ 831 ((MODE) == TIM_EncoderMode_TI12)) 832 /** 833 * @} 834 */ 835 836 837 /** @defgroup TIM_Event_Source 838 * @{ 839 */ 840 841 #define TIM_EventSource_Update ((uint16_t)0x0001) 842 #define TIM_EventSource_CC1 ((uint16_t)0x0002) 843 #define TIM_EventSource_CC2 ((uint16_t)0x0004) 844 #define TIM_EventSource_CC3 ((uint16_t)0x0008) 845 #define TIM_EventSource_CC4 ((uint16_t)0x0010) 846 #define TIM_EventSource_COM ((uint16_t)0x0020) 847 #define TIM_EventSource_Trigger ((uint16_t)0x0040) 848 #define TIM_EventSource_Break ((uint16_t)0x0080) 849 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000)) 850 851 /** 852 * @} 853 */ 854 855 /** @defgroup TIM_Update_Source 856 * @{ 857 */ 858 859 #define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow 860 or the setting of UG bit, or an update generation 861 through the slave mode controller. */ 862 #define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */ 863 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \ 864 ((SOURCE) == TIM_UpdateSource_Regular)) 865 /** 866 * @} 867 */ 868 869 /** @defgroup TIM_Ouput_Compare_Preload_State 870 * @{ 871 */ 872 873 #define TIM_OCPreload_Enable ((uint16_t)0x0008) 874 #define TIM_OCPreload_Disable ((uint16_t)0x0000) 875 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \ 876 ((STATE) == TIM_OCPreload_Disable)) 877 /** 878 * @} 879 */ 880 881 /** @defgroup TIM_Ouput_Compare_Fast_State 882 * @{ 883 */ 884 885 #define TIM_OCFast_Enable ((uint16_t)0x0004) 886 #define TIM_OCFast_Disable ((uint16_t)0x0000) 887 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \ 888 ((STATE) == TIM_OCFast_Disable)) 889 890 /** 891 * @} 892 */ 893 894 /** @defgroup TIM_Ouput_Compare_Clear_State 895 * @{ 896 */ 897 898 #define TIM_OCClear_Enable ((uint16_t)0x0080) 899 #define TIM_OCClear_Disable ((uint16_t)0x0000) 900 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \ 901 ((STATE) == TIM_OCClear_Disable)) 902 /** 903 * @} 904 */ 905 906 /** @defgroup TIM_Trigger_Output_Source 907 * @{ 908 */ 909 910 #define TIM_TRGOSource_Reset ((uint16_t)0x0000) 911 #define TIM_TRGOSource_Enable ((uint16_t)0x0010) 912 #define TIM_TRGOSource_Update ((uint16_t)0x0020) 913 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030) 914 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) 915 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) 916 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) 917 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) 918 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \ 919 ((SOURCE) == TIM_TRGOSource_Enable) || \ 920 ((SOURCE) == TIM_TRGOSource_Update) || \ 921 ((SOURCE) == TIM_TRGOSource_OC1) || \ 922 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ 923 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ 924 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ 925 ((SOURCE) == TIM_TRGOSource_OC4Ref)) 926 /** 927 * @} 928 */ 929 930 /** @defgroup TIM_Slave_Mode 931 * @{ 932 */ 933 934 #define TIM_SlaveMode_Reset ((uint16_t)0x0004) 935 #define TIM_SlaveMode_Gated ((uint16_t)0x0005) 936 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006) 937 #define TIM_SlaveMode_External1 ((uint16_t)0x0007) 938 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \ 939 ((MODE) == TIM_SlaveMode_Gated) || \ 940 ((MODE) == TIM_SlaveMode_Trigger) || \ 941 ((MODE) == TIM_SlaveMode_External1)) 942 /** 943 * @} 944 */ 945 946 /** @defgroup TIM_Master_Slave_Mode 947 * @{ 948 */ 949 950 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) 951 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) 952 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \ 953 ((STATE) == TIM_MasterSlaveMode_Disable)) 954 /** 955 * @} 956 */ 957 958 /** @defgroup TIM_Flags 959 * @{ 960 */ 961 962 #define TIM_FLAG_Update ((uint16_t)0x0001) 963 #define TIM_FLAG_CC1 ((uint16_t)0x0002) 964 #define TIM_FLAG_CC2 ((uint16_t)0x0004) 965 #define TIM_FLAG_CC3 ((uint16_t)0x0008) 966 #define TIM_FLAG_CC4 ((uint16_t)0x0010) 967 #define TIM_FLAG_COM ((uint16_t)0x0020) 968 #define TIM_FLAG_Trigger ((uint16_t)0x0040) 969 #define TIM_FLAG_Break ((uint16_t)0x0080) 970 #define TIM_FLAG_CC1OF ((uint16_t)0x0200) 971 #define TIM_FLAG_CC2OF ((uint16_t)0x0400) 972 #define TIM_FLAG_CC3OF ((uint16_t)0x0800) 973 #define TIM_FLAG_CC4OF ((uint16_t)0x1000) 974 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \ 975 ((FLAG) == TIM_FLAG_CC1) || \ 976 ((FLAG) == TIM_FLAG_CC2) || \ 977 ((FLAG) == TIM_FLAG_CC3) || \ 978 ((FLAG) == TIM_FLAG_CC4) || \ 979 ((FLAG) == TIM_FLAG_COM) || \ 980 ((FLAG) == TIM_FLAG_Trigger) || \ 981 ((FLAG) == TIM_FLAG_Break) || \ 982 ((FLAG) == TIM_FLAG_CC1OF) || \ 983 ((FLAG) == TIM_FLAG_CC2OF) || \ 984 ((FLAG) == TIM_FLAG_CC3OF) || \ 985 ((FLAG) == TIM_FLAG_CC4OF)) 986 987 988 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000)) 989 /** 990 * @} 991 */ 992 993 /** @defgroup TIM_Input_Capture_Filer_Value 994 * @{ 995 */ 996 997 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 998 /** 999 * @} 1000 */ 1001 1002 /** @defgroup TIM_External_Trigger_Filter 1003 * @{ 1004 */ 1005 1006 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) 1007 /** 1008 * @} 1009 */ 1010 1011 /** 1012 * @} 1013 */ 1014 1015 /** @defgroup TIM_Exported_Macros 1016 * @{ 1017 */ 1018 1019 /** 1020 * @} 1021 */ 1022 1023 /** @defgroup TIM_Exported_Functions 1024 * @{ 1025 */ 1026 1027 void TIM_DeInit(TIM_TypeDef* TIMx); 1028 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 1029 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1030 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1031 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1032 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); 1033 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 1034 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); 1035 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); 1036 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); 1037 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); 1038 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); 1039 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); 1040 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); 1041 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); 1042 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); 1043 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); 1044 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); 1045 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); 1046 void TIM_InternalClockConfig(TIM_TypeDef* TIMx); 1047 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 1048 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 1049 uint16_t TIM_ICPolarity, uint16_t ICFilter); 1050 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 1051 uint16_t ExtTRGFilter); 1052 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 1053 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); 1054 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 1055 uint16_t ExtTRGFilter); 1056 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); 1057 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); 1058 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); 1059 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 1060 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); 1061 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1062 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1063 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1064 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); 1065 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 1066 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); 1067 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); 1068 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); 1069 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1070 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1071 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1072 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); 1073 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1074 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1075 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1076 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); 1077 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1078 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1079 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1080 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); 1081 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1082 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1083 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1084 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1085 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1086 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); 1087 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); 1088 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); 1089 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); 1090 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); 1091 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); 1092 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); 1093 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); 1094 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); 1095 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 1096 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 1097 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); 1098 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); 1099 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); 1100 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); 1101 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); 1102 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); 1103 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); 1104 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1105 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1106 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1107 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); 1108 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); 1109 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); 1110 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); 1111 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); 1112 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); 1113 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); 1114 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); 1115 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 1116 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); 1117 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1118 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); 1119 1120 #ifdef __cplusplus 1121 } 1122 #endif 1123 1124 #endif /*__STM32F10x_TIM_H */ 1125 /** 1126 * @} 1127 */ 1128 1129 /** 1130 * @} 1131 */ 1132 1133 /** 1134 * @} 1135 */ 1136 1137 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 1138