1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/power/xlnx-zynqmp-power.h> 17#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 18 19/ { 20 compatible = "xlnx,zynqmp"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 compatible = "arm,cortex-a53"; 30 device_type = "cpu"; 31 enable-method = "psci"; 32 operating-points-v2 = <&cpu_opp_table>; 33 reg = <0x0>; 34 cpu-idle-states = <&CPU_SLEEP_0>; 35 }; 36 37 cpu1: cpu@1 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 enable-method = "psci"; 41 reg = <0x1>; 42 operating-points-v2 = <&cpu_opp_table>; 43 cpu-idle-states = <&CPU_SLEEP_0>; 44 }; 45 46 cpu2: cpu@2 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 enable-method = "psci"; 50 reg = <0x2>; 51 operating-points-v2 = <&cpu_opp_table>; 52 cpu-idle-states = <&CPU_SLEEP_0>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 operating-points-v2 = <&cpu_opp_table>; 61 cpu-idle-states = <&CPU_SLEEP_0>; 62 }; 63 64 idle-states { 65 entry-method = "psci"; 66 67 CPU_SLEEP_0: cpu-sleep-0 { 68 compatible = "arm,idle-state"; 69 arm,psci-suspend-param = <0x40000000>; 70 local-timer-stop; 71 entry-latency-us = <300>; 72 exit-latency-us = <600>; 73 min-residency-us = <10000>; 74 }; 75 }; 76 }; 77 78 cpu_opp_table: cpu-opp-table { 79 compatible = "operating-points-v2"; 80 opp-shared; 81 opp00 { 82 opp-hz = /bits/ 64 <1199999988>; 83 opp-microvolt = <1000000>; 84 clock-latency-ns = <500000>; 85 }; 86 opp01 { 87 opp-hz = /bits/ 64 <599999994>; 88 opp-microvolt = <1000000>; 89 clock-latency-ns = <500000>; 90 }; 91 opp02 { 92 opp-hz = /bits/ 64 <399999996>; 93 opp-microvolt = <1000000>; 94 clock-latency-ns = <500000>; 95 }; 96 opp03 { 97 opp-hz = /bits/ 64 <299999997>; 98 opp-microvolt = <1000000>; 99 clock-latency-ns = <500000>; 100 }; 101 }; 102 103 zynqmp_ipi: zynqmp_ipi { 104 u-boot,dm-pre-reloc; 105 compatible = "xlnx,zynqmp-ipi-mailbox"; 106 interrupt-parent = <&gic>; 107 interrupts = <0 35 4>; 108 xlnx,ipi-id = <0>; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges; 112 113 ipi_mailbox_pmu1: mailbox@ff990400 { 114 u-boot,dm-pre-reloc; 115 reg = <0x0 0xff9905c0 0x0 0x20>, 116 <0x0 0xff9905e0 0x0 0x20>, 117 <0x0 0xff990e80 0x0 0x20>, 118 <0x0 0xff990ea0 0x0 0x20>; 119 reg-names = "local_request_region", 120 "local_response_region", 121 "remote_request_region", 122 "remote_response_region"; 123 #mbox-cells = <1>; 124 xlnx,ipi-id = <4>; 125 }; 126 }; 127 128 dcc: dcc { 129 compatible = "arm,dcc"; 130 status = "disabled"; 131 u-boot,dm-pre-reloc; 132 }; 133 134 pmu { 135 compatible = "arm,armv8-pmuv3"; 136 interrupt-parent = <&gic>; 137 interrupts = <0 143 4>, 138 <0 144 4>, 139 <0 145 4>, 140 <0 146 4>; 141 }; 142 143 psci { 144 compatible = "arm,psci-0.2"; 145 method = "smc"; 146 }; 147 148 firmware { 149 zynqmp_firmware: zynqmp-firmware { 150 compatible = "xlnx,zynqmp-firmware"; 151 #power-domain-cells = <1>; 152 method = "smc"; 153 u-boot,dm-pre-reloc; 154 155 zynqmp_power: zynqmp-power { 156 u-boot,dm-pre-reloc; 157 compatible = "xlnx,zynqmp-power"; 158 interrupt-parent = <&gic>; 159 interrupts = <0 35 4>; 160 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 161 mbox-names = "tx", "rx"; 162 }; 163 164 nvmem_firmware { 165 compatible = "xlnx,zynqmp-nvmem-fw"; 166 #address-cells = <1>; 167 #size-cells = <1>; 168 169 soc_revision: soc_revision@0 { 170 reg = <0x0 0x4>; 171 }; 172 }; 173 174 zynqmp_pcap: pcap { 175 compatible = "xlnx,zynqmp-pcap-fpga"; 176 clock-names = "ref_clk"; 177 }; 178 179 xlnx_aes: zynqmp-aes { 180 compatible = "xlnx,zynqmp-aes"; 181 }; 182 183 zynqmp_reset: reset-controller { 184 compatible = "xlnx,zynqmp-reset"; 185 #reset-cells = <1>; 186 }; 187 188 pinctrl0: pinctrl { 189 compatible = "xlnx,zynqmp-pinctrl"; 190 status = "disabled"; 191 }; 192 }; 193 }; 194 195 timer { 196 compatible = "arm,armv8-timer"; 197 interrupt-parent = <&gic>; 198 interrupts = <1 13 0xf08>, 199 <1 14 0xf08>, 200 <1 11 0xf08>, 201 <1 10 0xf08>; 202 }; 203 204 edac { 205 compatible = "arm,cortex-a53-edac"; 206 }; 207 208 fpga_full: fpga-full { 209 compatible = "fpga-region"; 210 fpga-mgr = <&zynqmp_pcap>; 211 #address-cells = <2>; 212 #size-cells = <2>; 213 ranges; 214 }; 215 216 amba: axi { 217 compatible = "simple-bus"; 218 u-boot,dm-pre-reloc; 219 #address-cells = <2>; 220 #size-cells = <2>; 221 ranges; 222 223 can0: can@ff060000 { 224 compatible = "xlnx,zynq-can-1.0"; 225 status = "disabled"; 226 clock-names = "can_clk", "pclk"; 227 reg = <0x0 0xff060000 0x0 0x1000>; 228 interrupts = <0 23 4>; 229 interrupt-parent = <&gic>; 230 tx-fifo-depth = <0x40>; 231 rx-fifo-depth = <0x40>; 232 power-domains = <&zynqmp_firmware PD_CAN_0>; 233 }; 234 235 can1: can@ff070000 { 236 compatible = "xlnx,zynq-can-1.0"; 237 status = "disabled"; 238 clock-names = "can_clk", "pclk"; 239 reg = <0x0 0xff070000 0x0 0x1000>; 240 interrupts = <0 24 4>; 241 interrupt-parent = <&gic>; 242 tx-fifo-depth = <0x40>; 243 rx-fifo-depth = <0x40>; 244 power-domains = <&zynqmp_firmware PD_CAN_1>; 245 }; 246 247 cci: cci@fd6e0000 { 248 compatible = "arm,cci-400"; 249 status = "disabled"; 250 reg = <0x0 0xfd6e0000 0x0 0x9000>; 251 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 252 #address-cells = <1>; 253 #size-cells = <1>; 254 255 pmu@9000 { 256 compatible = "arm,cci-400-pmu,r1"; 257 reg = <0x9000 0x5000>; 258 interrupt-parent = <&gic>; 259 interrupts = <0 123 4>, 260 <0 123 4>, 261 <0 123 4>, 262 <0 123 4>, 263 <0 123 4>; 264 }; 265 }; 266 267 /* GDMA */ 268 fpd_dma_chan1: dma@fd500000 { 269 status = "disabled"; 270 compatible = "xlnx,zynqmp-dma-1.0"; 271 reg = <0x0 0xfd500000 0x0 0x1000>; 272 interrupt-parent = <&gic>; 273 interrupts = <0 124 4>; 274 clock-names = "clk_main", "clk_apb"; 275 xlnx,bus-width = <128>; 276 #stream-id-cells = <1>; 277 iommus = <&smmu 0x14e8>; 278 power-domains = <&zynqmp_firmware PD_GDMA>; 279 }; 280 281 fpd_dma_chan2: dma@fd510000 { 282 status = "disabled"; 283 compatible = "xlnx,zynqmp-dma-1.0"; 284 reg = <0x0 0xfd510000 0x0 0x1000>; 285 interrupt-parent = <&gic>; 286 interrupts = <0 125 4>; 287 clock-names = "clk_main", "clk_apb"; 288 xlnx,bus-width = <128>; 289 #stream-id-cells = <1>; 290 iommus = <&smmu 0x14e9>; 291 power-domains = <&zynqmp_firmware PD_GDMA>; 292 }; 293 294 fpd_dma_chan3: dma@fd520000 { 295 status = "disabled"; 296 compatible = "xlnx,zynqmp-dma-1.0"; 297 reg = <0x0 0xfd520000 0x0 0x1000>; 298 interrupt-parent = <&gic>; 299 interrupts = <0 126 4>; 300 clock-names = "clk_main", "clk_apb"; 301 xlnx,bus-width = <128>; 302 #stream-id-cells = <1>; 303 iommus = <&smmu 0x14ea>; 304 power-domains = <&zynqmp_firmware PD_GDMA>; 305 }; 306 307 fpd_dma_chan4: dma@fd530000 { 308 status = "disabled"; 309 compatible = "xlnx,zynqmp-dma-1.0"; 310 reg = <0x0 0xfd530000 0x0 0x1000>; 311 interrupt-parent = <&gic>; 312 interrupts = <0 127 4>; 313 clock-names = "clk_main", "clk_apb"; 314 xlnx,bus-width = <128>; 315 #stream-id-cells = <1>; 316 iommus = <&smmu 0x14eb>; 317 power-domains = <&zynqmp_firmware PD_GDMA>; 318 }; 319 320 fpd_dma_chan5: dma@fd540000 { 321 status = "disabled"; 322 compatible = "xlnx,zynqmp-dma-1.0"; 323 reg = <0x0 0xfd540000 0x0 0x1000>; 324 interrupt-parent = <&gic>; 325 interrupts = <0 128 4>; 326 clock-names = "clk_main", "clk_apb"; 327 xlnx,bus-width = <128>; 328 #stream-id-cells = <1>; 329 iommus = <&smmu 0x14ec>; 330 power-domains = <&zynqmp_firmware PD_GDMA>; 331 }; 332 333 fpd_dma_chan6: dma@fd550000 { 334 status = "disabled"; 335 compatible = "xlnx,zynqmp-dma-1.0"; 336 reg = <0x0 0xfd550000 0x0 0x1000>; 337 interrupt-parent = <&gic>; 338 interrupts = <0 129 4>; 339 clock-names = "clk_main", "clk_apb"; 340 xlnx,bus-width = <128>; 341 #stream-id-cells = <1>; 342 iommus = <&smmu 0x14ed>; 343 power-domains = <&zynqmp_firmware PD_GDMA>; 344 }; 345 346 fpd_dma_chan7: dma@fd560000 { 347 status = "disabled"; 348 compatible = "xlnx,zynqmp-dma-1.0"; 349 reg = <0x0 0xfd560000 0x0 0x1000>; 350 interrupt-parent = <&gic>; 351 interrupts = <0 130 4>; 352 clock-names = "clk_main", "clk_apb"; 353 xlnx,bus-width = <128>; 354 #stream-id-cells = <1>; 355 iommus = <&smmu 0x14ee>; 356 power-domains = <&zynqmp_firmware PD_GDMA>; 357 }; 358 359 fpd_dma_chan8: dma@fd570000 { 360 status = "disabled"; 361 compatible = "xlnx,zynqmp-dma-1.0"; 362 reg = <0x0 0xfd570000 0x0 0x1000>; 363 interrupt-parent = <&gic>; 364 interrupts = <0 131 4>; 365 clock-names = "clk_main", "clk_apb"; 366 xlnx,bus-width = <128>; 367 #stream-id-cells = <1>; 368 iommus = <&smmu 0x14ef>; 369 power-domains = <&zynqmp_firmware PD_GDMA>; 370 }; 371 372 gic: interrupt-controller@f9010000 { 373 compatible = "arm,gic-400"; 374 #interrupt-cells = <3>; 375 reg = <0x0 0xf9010000 0x0 0x10000>, 376 <0x0 0xf9020000 0x0 0x20000>, 377 <0x0 0xf9040000 0x0 0x20000>, 378 <0x0 0xf9060000 0x0 0x20000>; 379 interrupt-controller; 380 interrupt-parent = <&gic>; 381 interrupts = <1 9 0xf04>; 382 }; 383 384 gpu: gpu@fd4b0000 { 385 status = "disabled"; 386 compatible = "arm,mali-400", "arm,mali-utgard"; 387 reg = <0x0 0xfd4b0000 0x0 0x10000>; 388 interrupt-parent = <&gic>; 389 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; 390 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; 391 clock-names = "gpu", "gpu_pp0", "gpu_pp1"; 392 power-domains = <&zynqmp_firmware PD_GPU>; 393 }; 394 395 /* LPDDMA default allows only secured access. inorder to enable 396 * These dma channels, Users should ensure that these dma 397 * Channels are allowed for non secure access. 398 */ 399 lpd_dma_chan1: dma@ffa80000 { 400 status = "disabled"; 401 compatible = "xlnx,zynqmp-dma-1.0"; 402 reg = <0x0 0xffa80000 0x0 0x1000>; 403 interrupt-parent = <&gic>; 404 interrupts = <0 77 4>; 405 clock-names = "clk_main", "clk_apb"; 406 xlnx,bus-width = <64>; 407 #stream-id-cells = <1>; 408 iommus = <&smmu 0x868>; 409 power-domains = <&zynqmp_firmware PD_ADMA>; 410 }; 411 412 lpd_dma_chan2: dma@ffa90000 { 413 status = "disabled"; 414 compatible = "xlnx,zynqmp-dma-1.0"; 415 reg = <0x0 0xffa90000 0x0 0x1000>; 416 interrupt-parent = <&gic>; 417 interrupts = <0 78 4>; 418 clock-names = "clk_main", "clk_apb"; 419 xlnx,bus-width = <64>; 420 #stream-id-cells = <1>; 421 iommus = <&smmu 0x869>; 422 power-domains = <&zynqmp_firmware PD_ADMA>; 423 }; 424 425 lpd_dma_chan3: dma@ffaa0000 { 426 status = "disabled"; 427 compatible = "xlnx,zynqmp-dma-1.0"; 428 reg = <0x0 0xffaa0000 0x0 0x1000>; 429 interrupt-parent = <&gic>; 430 interrupts = <0 79 4>; 431 clock-names = "clk_main", "clk_apb"; 432 xlnx,bus-width = <64>; 433 #stream-id-cells = <1>; 434 iommus = <&smmu 0x86a>; 435 power-domains = <&zynqmp_firmware PD_ADMA>; 436 }; 437 438 lpd_dma_chan4: dma@ffab0000 { 439 status = "disabled"; 440 compatible = "xlnx,zynqmp-dma-1.0"; 441 reg = <0x0 0xffab0000 0x0 0x1000>; 442 interrupt-parent = <&gic>; 443 interrupts = <0 80 4>; 444 clock-names = "clk_main", "clk_apb"; 445 xlnx,bus-width = <64>; 446 #stream-id-cells = <1>; 447 iommus = <&smmu 0x86b>; 448 power-domains = <&zynqmp_firmware PD_ADMA>; 449 }; 450 451 lpd_dma_chan5: dma@ffac0000 { 452 status = "disabled"; 453 compatible = "xlnx,zynqmp-dma-1.0"; 454 reg = <0x0 0xffac0000 0x0 0x1000>; 455 interrupt-parent = <&gic>; 456 interrupts = <0 81 4>; 457 clock-names = "clk_main", "clk_apb"; 458 xlnx,bus-width = <64>; 459 #stream-id-cells = <1>; 460 iommus = <&smmu 0x86c>; 461 power-domains = <&zynqmp_firmware PD_ADMA>; 462 }; 463 464 lpd_dma_chan6: dma@ffad0000 { 465 status = "disabled"; 466 compatible = "xlnx,zynqmp-dma-1.0"; 467 reg = <0x0 0xffad0000 0x0 0x1000>; 468 interrupt-parent = <&gic>; 469 interrupts = <0 82 4>; 470 clock-names = "clk_main", "clk_apb"; 471 xlnx,bus-width = <64>; 472 #stream-id-cells = <1>; 473 iommus = <&smmu 0x86d>; 474 power-domains = <&zynqmp_firmware PD_ADMA>; 475 }; 476 477 lpd_dma_chan7: dma@ffae0000 { 478 status = "disabled"; 479 compatible = "xlnx,zynqmp-dma-1.0"; 480 reg = <0x0 0xffae0000 0x0 0x1000>; 481 interrupt-parent = <&gic>; 482 interrupts = <0 83 4>; 483 clock-names = "clk_main", "clk_apb"; 484 xlnx,bus-width = <64>; 485 #stream-id-cells = <1>; 486 iommus = <&smmu 0x86e>; 487 power-domains = <&zynqmp_firmware PD_ADMA>; 488 }; 489 490 lpd_dma_chan8: dma@ffaf0000 { 491 status = "disabled"; 492 compatible = "xlnx,zynqmp-dma-1.0"; 493 reg = <0x0 0xffaf0000 0x0 0x1000>; 494 interrupt-parent = <&gic>; 495 interrupts = <0 84 4>; 496 clock-names = "clk_main", "clk_apb"; 497 xlnx,bus-width = <64>; 498 #stream-id-cells = <1>; 499 iommus = <&smmu 0x86f>; 500 power-domains = <&zynqmp_firmware PD_ADMA>; 501 }; 502 503 mc: memory-controller@fd070000 { 504 compatible = "xlnx,zynqmp-ddrc-2.40a"; 505 reg = <0x0 0xfd070000 0x0 0x30000>; 506 interrupt-parent = <&gic>; 507 interrupts = <0 112 4>; 508 }; 509 510 nand0: nand-controller@ff100000 { 511 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 512 status = "disabled"; 513 reg = <0x0 0xff100000 0x0 0x1000>; 514 clock-names = "controller", "bus"; 515 interrupt-parent = <&gic>; 516 interrupts = <0 14 4>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 #stream-id-cells = <1>; 520 iommus = <&smmu 0x872>; 521 power-domains = <&zynqmp_firmware PD_NAND>; 522 }; 523 524 gem0: ethernet@ff0b0000 { 525 compatible = "cdns,zynqmp-gem", "cdns,gem"; 526 status = "disabled"; 527 interrupt-parent = <&gic>; 528 interrupts = <0 57 4>, <0 57 4>; 529 reg = <0x0 0xff0b0000 0x0 0x1000>; 530 clock-names = "pclk", "hclk", "tx_clk"; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 #stream-id-cells = <1>; 534 iommus = <&smmu 0x874>; 535 power-domains = <&zynqmp_firmware PD_ETH_0>; 536 }; 537 538 gem1: ethernet@ff0c0000 { 539 compatible = "cdns,zynqmp-gem", "cdns,gem"; 540 status = "disabled"; 541 interrupt-parent = <&gic>; 542 interrupts = <0 59 4>, <0 59 4>; 543 reg = <0x0 0xff0c0000 0x0 0x1000>; 544 clock-names = "pclk", "hclk", "tx_clk"; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 #stream-id-cells = <1>; 548 iommus = <&smmu 0x875>; 549 power-domains = <&zynqmp_firmware PD_ETH_1>; 550 }; 551 552 gem2: ethernet@ff0d0000 { 553 compatible = "cdns,zynqmp-gem", "cdns,gem"; 554 status = "disabled"; 555 interrupt-parent = <&gic>; 556 interrupts = <0 61 4>, <0 61 4>; 557 reg = <0x0 0xff0d0000 0x0 0x1000>; 558 clock-names = "pclk", "hclk", "tx_clk"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 #stream-id-cells = <1>; 562 iommus = <&smmu 0x876>; 563 power-domains = <&zynqmp_firmware PD_ETH_2>; 564 }; 565 566 gem3: ethernet@ff0e0000 { 567 compatible = "cdns,zynqmp-gem", "cdns,gem"; 568 status = "disabled"; 569 interrupt-parent = <&gic>; 570 interrupts = <0 63 4>, <0 63 4>; 571 reg = <0x0 0xff0e0000 0x0 0x1000>; 572 clock-names = "pclk", "hclk", "tx_clk"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 #stream-id-cells = <1>; 576 iommus = <&smmu 0x877>; 577 power-domains = <&zynqmp_firmware PD_ETH_3>; 578 }; 579 580 gpio: gpio@ff0a0000 { 581 compatible = "xlnx,zynqmp-gpio-1.0"; 582 status = "disabled"; 583 #gpio-cells = <0x2>; 584 gpio-controller; 585 interrupt-parent = <&gic>; 586 interrupts = <0 16 4>; 587 interrupt-controller; 588 #interrupt-cells = <2>; 589 reg = <0x0 0xff0a0000 0x0 0x1000>; 590 power-domains = <&zynqmp_firmware PD_GPIO>; 591 }; 592 593 i2c0: i2c@ff020000 { 594 compatible = "cdns,i2c-r1p14"; 595 status = "disabled"; 596 interrupt-parent = <&gic>; 597 interrupts = <0 17 4>; 598 reg = <0x0 0xff020000 0x0 0x1000>; 599 #address-cells = <1>; 600 #size-cells = <0>; 601 power-domains = <&zynqmp_firmware PD_I2C_0>; 602 }; 603 604 i2c1: i2c@ff030000 { 605 compatible = "cdns,i2c-r1p14"; 606 status = "disabled"; 607 interrupt-parent = <&gic>; 608 interrupts = <0 18 4>; 609 reg = <0x0 0xff030000 0x0 0x1000>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 power-domains = <&zynqmp_firmware PD_I2C_1>; 613 }; 614 615 ocm: memory-controller@ff960000 { 616 compatible = "xlnx,zynqmp-ocmc-1.0"; 617 reg = <0x0 0xff960000 0x0 0x1000>; 618 interrupt-parent = <&gic>; 619 interrupts = <0 10 4>; 620 }; 621 622 pcie: pcie@fd0e0000 { 623 compatible = "xlnx,nwl-pcie-2.11"; 624 status = "disabled"; 625 #address-cells = <3>; 626 #size-cells = <2>; 627 #interrupt-cells = <1>; 628 msi-controller; 629 device_type = "pci"; 630 interrupt-parent = <&gic>; 631 interrupts = <0 118 4>, 632 <0 117 4>, 633 <0 116 4>, 634 <0 115 4>, /* MSI_1 [63...32] */ 635 <0 114 4>; /* MSI_0 [31...0] */ 636 interrupt-names = "misc", "dummy", "intx", 637 "msi1", "msi0"; 638 msi-parent = <&pcie>; 639 reg = <0x0 0xfd0e0000 0x0 0x1000>, 640 <0x0 0xfd480000 0x0 0x1000>, 641 <0x80 0x00000000 0x0 0x1000000>; 642 reg-names = "breg", "pcireg", "cfg"; 643 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 644 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 645 bus-range = <0x00 0xff>; 646 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 647 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 648 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 649 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 650 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 651 #stream-id-cells = <1>; 652 iommus = <&smmu 0x4d0>; 653 power-domains = <&zynqmp_firmware PD_PCIE>; 654 pcie_intc: legacy-interrupt-controller { 655 interrupt-controller; 656 #address-cells = <0>; 657 #interrupt-cells = <1>; 658 }; 659 }; 660 661 qspi: spi@ff0f0000 { 662 u-boot,dm-pre-reloc; 663 compatible = "xlnx,zynqmp-qspi-1.0"; 664 status = "disabled"; 665 clock-names = "ref_clk", "pclk"; 666 interrupts = <0 15 4>; 667 interrupt-parent = <&gic>; 668 num-cs = <1>; 669 reg = <0x0 0xff0f0000 0x0 0x1000>, 670 <0x0 0xc0000000 0x0 0x8000000>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 #stream-id-cells = <1>; 674 iommus = <&smmu 0x873>; 675 power-domains = <&zynqmp_firmware PD_QSPI>; 676 }; 677 678 psgtr: phy@fd400000 { 679 compatible = "xlnx,zynqmp-psgtr-v1.1"; 680 status = "disabled"; 681 reg = <0x0 0xfd400000 0x0 0x40000>, 682 <0x0 0xfd3d0000 0x0 0x1000>; 683 reg-names = "serdes", "siou"; 684 #phy-cells = <4>; 685 }; 686 687 rtc: rtc@ffa60000 { 688 compatible = "xlnx,zynqmp-rtc"; 689 status = "disabled"; 690 reg = <0x0 0xffa60000 0x0 0x100>; 691 interrupt-parent = <&gic>; 692 interrupts = <0 26 4>, <0 27 4>; 693 interrupt-names = "alarm", "sec"; 694 calibration = <0x7FFF>; 695 }; 696 697 sata: ahci@fd0c0000 { 698 compatible = "ceva,ahci-1v84"; 699 status = "disabled"; 700 reg = <0x0 0xfd0c0000 0x0 0x2000>; 701 interrupt-parent = <&gic>; 702 interrupts = <0 133 4>; 703 power-domains = <&zynqmp_firmware PD_SATA>; 704 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 705 #stream-id-cells = <4>; 706 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 707 <&smmu 0x4c2>, <&smmu 0x4c3>; 708 /* dma-coherent; */ 709 }; 710 711 sdhci0: mmc@ff160000 { 712 u-boot,dm-pre-reloc; 713 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 714 status = "disabled"; 715 interrupt-parent = <&gic>; 716 interrupts = <0 48 4>; 717 reg = <0x0 0xff160000 0x0 0x1000>; 718 clock-names = "clk_xin", "clk_ahb"; 719 xlnx,device_id = <0>; 720 #stream-id-cells = <1>; 721 iommus = <&smmu 0x870>; 722 #clock-cells = <1>; 723 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 724 power-domains = <&zynqmp_firmware PD_SD_0>; 725 }; 726 727 sdhci1: mmc@ff170000 { 728 u-boot,dm-pre-reloc; 729 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 730 status = "disabled"; 731 interrupt-parent = <&gic>; 732 interrupts = <0 49 4>; 733 reg = <0x0 0xff170000 0x0 0x1000>; 734 clock-names = "clk_xin", "clk_ahb"; 735 xlnx,device_id = <1>; 736 #stream-id-cells = <1>; 737 iommus = <&smmu 0x871>; 738 #clock-cells = <1>; 739 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 740 power-domains = <&zynqmp_firmware PD_SD_1>; 741 }; 742 743 smmu: iommu@fd800000 { 744 compatible = "arm,mmu-500"; 745 reg = <0x0 0xfd800000 0x0 0x20000>; 746 #iommu-cells = <1>; 747 status = "disabled"; 748 #global-interrupts = <1>; 749 interrupt-parent = <&gic>; 750 interrupts = <0 155 4>, 751 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 752 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 753 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 754 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 755 }; 756 757 spi0: spi@ff040000 { 758 compatible = "cdns,spi-r1p6"; 759 status = "disabled"; 760 interrupt-parent = <&gic>; 761 interrupts = <0 19 4>; 762 reg = <0x0 0xff040000 0x0 0x1000>; 763 clock-names = "ref_clk", "pclk"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 power-domains = <&zynqmp_firmware PD_SPI_0>; 767 }; 768 769 spi1: spi@ff050000 { 770 compatible = "cdns,spi-r1p6"; 771 status = "disabled"; 772 interrupt-parent = <&gic>; 773 interrupts = <0 20 4>; 774 reg = <0x0 0xff050000 0x0 0x1000>; 775 clock-names = "ref_clk", "pclk"; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 power-domains = <&zynqmp_firmware PD_SPI_1>; 779 }; 780 781 ttc0: timer@ff110000 { 782 compatible = "cdns,ttc"; 783 status = "disabled"; 784 interrupt-parent = <&gic>; 785 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 786 reg = <0x0 0xff110000 0x0 0x1000>; 787 timer-width = <32>; 788 power-domains = <&zynqmp_firmware PD_TTC_0>; 789 }; 790 791 ttc1: timer@ff120000 { 792 compatible = "cdns,ttc"; 793 status = "disabled"; 794 interrupt-parent = <&gic>; 795 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 796 reg = <0x0 0xff120000 0x0 0x1000>; 797 timer-width = <32>; 798 power-domains = <&zynqmp_firmware PD_TTC_1>; 799 }; 800 801 ttc2: timer@ff130000 { 802 compatible = "cdns,ttc"; 803 status = "disabled"; 804 interrupt-parent = <&gic>; 805 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 806 reg = <0x0 0xff130000 0x0 0x1000>; 807 timer-width = <32>; 808 power-domains = <&zynqmp_firmware PD_TTC_2>; 809 }; 810 811 ttc3: timer@ff140000 { 812 compatible = "cdns,ttc"; 813 status = "disabled"; 814 interrupt-parent = <&gic>; 815 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 816 reg = <0x0 0xff140000 0x0 0x1000>; 817 timer-width = <32>; 818 power-domains = <&zynqmp_firmware PD_TTC_3>; 819 }; 820 821 uart0: serial@ff000000 { 822 u-boot,dm-pre-reloc; 823 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 824 status = "disabled"; 825 interrupt-parent = <&gic>; 826 interrupts = <0 21 4>; 827 reg = <0x0 0xff000000 0x0 0x1000>; 828 clock-names = "uart_clk", "pclk"; 829 power-domains = <&zynqmp_firmware PD_UART_0>; 830 }; 831 832 uart1: serial@ff010000 { 833 u-boot,dm-pre-reloc; 834 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 835 status = "disabled"; 836 interrupt-parent = <&gic>; 837 interrupts = <0 22 4>; 838 reg = <0x0 0xff010000 0x0 0x1000>; 839 clock-names = "uart_clk", "pclk"; 840 power-domains = <&zynqmp_firmware PD_UART_1>; 841 }; 842 843 usb0: usb0@ff9d0000 { 844 #address-cells = <2>; 845 #size-cells = <2>; 846 status = "disabled"; 847 compatible = "xlnx,zynqmp-dwc3"; 848 reg = <0x0 0xff9d0000 0x0 0x100>; 849 clock-names = "bus_clk", "ref_clk"; 850 power-domains = <&zynqmp_firmware PD_USB_0>; 851 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 852 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 853 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 854 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 855 ranges; 856 857 dwc3_0: dwc3@fe200000 { 858 compatible = "snps,dwc3"; 859 status = "disabled"; 860 reg = <0x0 0xfe200000 0x0 0x40000>; 861 interrupt-parent = <&gic>; 862 interrupt-names = "dwc_usb3", "otg", "hiber"; 863 interrupts = <0 65 4>, <0 69 4>, <0 75 4>; 864 #stream-id-cells = <1>; 865 iommus = <&smmu 0x860>; 866 snps,quirk-frame-length-adjustment = <0x20>; 867 snps,refclk_fladj; 868 snps,enable_guctl1_resume_quirk; 869 snps,enable_guctl1_ipd_quirk; 870 snps,xhci-stream-quirk; 871 /* dma-coherent; */ 872 }; 873 }; 874 875 usb1: usb1@ff9e0000 { 876 #address-cells = <2>; 877 #size-cells = <2>; 878 status = "disabled"; 879 compatible = "xlnx,zynqmp-dwc3"; 880 reg = <0x0 0xff9e0000 0x0 0x100>; 881 clock-names = "bus_clk", "ref_clk"; 882 power-domains = <&zynqmp_firmware PD_USB_1>; 883 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 884 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 885 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 886 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 887 ranges; 888 889 dwc3_1: dwc3@fe300000 { 890 compatible = "snps,dwc3"; 891 status = "disabled"; 892 reg = <0x0 0xfe300000 0x0 0x40000>; 893 interrupt-parent = <&gic>; 894 interrupt-names = "dwc_usb3", "otg", "hiber"; 895 interrupts = <0 70 4>, <0 74 4>, <0 76 4>; 896 #stream-id-cells = <1>; 897 iommus = <&smmu 0x861>; 898 snps,quirk-frame-length-adjustment = <0x20>; 899 snps,refclk_fladj; 900 snps,enable_guctl1_resume_quirk; 901 snps,enable_guctl1_ipd_quirk; 902 snps,xhci-stream-quirk; 903 /* dma-coherent; */ 904 }; 905 }; 906 907 watchdog0: watchdog@fd4d0000 { 908 compatible = "cdns,wdt-r1p2"; 909 status = "disabled"; 910 interrupt-parent = <&gic>; 911 interrupts = <0 113 1>; 912 reg = <0x0 0xfd4d0000 0x0 0x1000>; 913 timeout-sec = <60>; 914 reset-on-timeout; 915 }; 916 917 lpd_watchdog: watchdog@ff150000 { 918 compatible = "cdns,wdt-r1p2"; 919 status = "disabled"; 920 interrupt-parent = <&gic>; 921 interrupts = <0 52 1>; 922 reg = <0x0 0xff150000 0x0 0x1000>; 923 timeout-sec = <10>; 924 }; 925 926 xilinx_ams: ams@ffa50000 { 927 compatible = "xlnx,zynqmp-ams"; 928 status = "disabled"; 929 interrupt-parent = <&gic>; 930 interrupts = <0 56 4>; 931 interrupt-names = "ams-irq"; 932 reg = <0x0 0xffa50000 0x0 0x800>; 933 reg-names = "ams-base"; 934 #address-cells = <2>; 935 #size-cells = <2>; 936 #io-channel-cells = <1>; 937 ranges; 938 939 ams_ps: ams_ps@ffa50800 { 940 compatible = "xlnx,zynqmp-ams-ps"; 941 status = "disabled"; 942 reg = <0x0 0xffa50800 0x0 0x400>; 943 }; 944 945 ams_pl: ams_pl@ffa50c00 { 946 compatible = "xlnx,zynqmp-ams-pl"; 947 status = "disabled"; 948 reg = <0x0 0xffa50c00 0x0 0x400>; 949 }; 950 }; 951 952 zynqmp_dpdma: dma-controller@fd4c0000 { 953 compatible = "xlnx,zynqmp-dpdma"; 954 status = "disabled"; 955 reg = <0x0 0xfd4c0000 0x0 0x1000>; 956 interrupts = <0 122 4>; 957 interrupt-parent = <&gic>; 958 clock-names = "axi_clk"; 959 power-domains = <&zynqmp_firmware PD_DP>; 960 #dma-cells = <1>; 961 }; 962 963 zynqmp_dpsub: display@fd4a0000 { 964 compatible = "xlnx,zynqmp-dpsub-1.7"; 965 status = "disabled"; 966 reg = <0x0 0xfd4a0000 0x0 0x1000>, 967 <0x0 0xfd4aa000 0x0 0x1000>, 968 <0x0 0xfd4ab000 0x0 0x1000>, 969 <0x0 0xfd4ac000 0x0 0x1000>; 970 reg-names = "dp", "blend", "av_buf", "aud"; 971 interrupts = <0 119 4>; 972 interrupt-parent = <&gic>; 973 clock-names = "dp_apb_clk", "dp_aud_clk", 974 "dp_vtc_pixel_clk_in"; 975 power-domains = <&zynqmp_firmware PD_DP>; 976 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 977 dma-names = "vid0", "vid1", "vid2", "gfx0"; 978 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 979 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 980 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 981 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 982 }; 983 }; 984}; 985