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Searched refs:CACHE_CLR (Results 1 – 10 of 10) sorted by relevance

/AliOS-Things-master/components/csi/csi1/include/core/
A Dcore_ck807.h443 #define CACHE_CLR (1 << 5) macro
562 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
572 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
621 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
633 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_810.h469 #define CACHE_CLR (1 << 5) macro
588 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
598 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
647 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
659 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck810.h450 #define CACHE_CLR (1 << 5) macro
569 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
579 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
628 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
640 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck610.h469 #define CACHE_CLR (1 << 5) macro
582 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
593 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
642 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
654 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_807.h997 #define CACHE_CLR (1 << 5) macro
1244 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
1254 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
1303 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
1315 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
/AliOS-Things-master/components/csi/csi2/include/core/
A Dcore_ck807.h443 #define CACHE_CLR (1 << 5) macro
562 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
572 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
621 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
633 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_810.h469 #define CACHE_CLR (1 << 5) macro
588 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
598 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
647 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
659 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck810.h450 #define CACHE_CLR (1 << 5) macro
569 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
579 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
628 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
640 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_ck610.h469 #define CACHE_CLR (1 << 5) macro
582 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
593 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
642 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
654 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()
A Dcore_807.h997 #define CACHE_CLR (1 << 5) macro
1244 __set_CFR(DATA_CACHE | CACHE_CLR); in csi_dcache_clean()
1254 __set_CFR(DATA_CACHE | CACHE_CLR | CACHE_INV); in csi_dcache_clean_invalid()
1303 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR)); in csi_dcache_clean_range()
1315 set_cache_range((uint32_t)addr, (uint32_t)addr + dsize, (DATA_CACHE | CACHE_CLR | CACHE_INV)); in csi_dcache_clean_invalid_range()

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