1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_crs.h
4 * @author MCD Application Team
5 * @brief Header file of CRS LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F0xx_LL_CRS_H
38 #define __STM32F0xx_LL_CRS_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f0xx.h"
46
47 /** @addtogroup STM32F0xx_LL_Driver
48 * @{
49 */
50
51 #if defined(CRS)
52
53 /** @defgroup CRS_LL CRS
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
65 * @{
66 */
67
68 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
69 * @brief Flags defines which can be used with LL_CRS_ReadReg function
70 * @{
71 */
72 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
73 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
74 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
75 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
76 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
77 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
78 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
79 /**
80 * @}
81 */
82
83 /** @defgroup CRS_LL_EC_IT IT Defines
84 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
85 * @{
86 */
87 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
88 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
89 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
90 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
91 /**
92 * @}
93 */
94
95 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
96 * @{
97 */
98 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
99 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
100 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
101 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
102 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
103 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
104 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
105 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
106 /**
107 * @}
108 */
109
110 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
111 * @{
112 */
113 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
114 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
115 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
116 /**
117 * @}
118 */
119
120 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
121 * @{
122 */
123 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
124 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
125 /**
126 * @}
127 */
128
129 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
130 * @{
131 */
132 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
133 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
134 /**
135 * @}
136 */
137
138 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
139 * @{
140 */
141 /**
142 * @brief Reset value of the RELOAD field
143 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
144 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
145 */
146 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
147
148 /**
149 * @brief Reset value of Frequency error limit.
150 */
151 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
152
153 /**
154 * @brief Reset value of the HSI48 Calibration field
155 * @note The default value is 32, which corresponds to the middle of the trimming interval.
156 * The trimming step is around 67 kHz between two consecutive TRIM steps.
157 * A higher TRIM value corresponds to a higher output frequency
158 */
159 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
160 /**
161 * @}
162 */
163
164 /**
165 * @}
166 */
167
168 /* Exported macro ------------------------------------------------------------*/
169 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
170 * @{
171 */
172
173 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
174 * @{
175 */
176
177 /**
178 * @brief Write a value in CRS register
179 * @param __INSTANCE__ CRS Instance
180 * @param __REG__ Register to be written
181 * @param __VALUE__ Value to be written in the register
182 * @retval None
183 */
184 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
185
186 /**
187 * @brief Read a value in CRS register
188 * @param __INSTANCE__ CRS Instance
189 * @param __REG__ Register to be read
190 * @retval Register value
191 */
192 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
193 /**
194 * @}
195 */
196
197 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
198 * @{
199 */
200
201 /**
202 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
203 * @note The RELOAD value should be selected according to the ratio between
204 * the target frequency and the frequency of the synchronization source after
205 * prescaling. It is then decreased by one in order to reach the expected
206 * synchronization on the zero value. The formula is the following:
207 * RELOAD = (fTARGET / fSYNC) -1
208 * @param __FTARGET__ Target frequency (value in Hz)
209 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
210 * @retval Reload value (in Hz)
211 */
212 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
213
214 /**
215 * @}
216 */
217
218 /**
219 * @}
220 */
221
222 /* Exported functions --------------------------------------------------------*/
223 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
224 * @{
225 */
226
227 /** @defgroup CRS_LL_EF_Configuration Configuration
228 * @{
229 */
230
231 /**
232 * @brief Enable Frequency error counter
233 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
234 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
235 * @retval None
236 */
LL_CRS_EnableFreqErrorCounter(void)237 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
238 {
239 SET_BIT(CRS->CR, CRS_CR_CEN);
240 }
241
242 /**
243 * @brief Disable Frequency error counter
244 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
245 * @retval None
246 */
LL_CRS_DisableFreqErrorCounter(void)247 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
248 {
249 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
250 }
251
252 /**
253 * @brief Check if Frequency error counter is enabled or not
254 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
255 * @retval State of bit (1 or 0).
256 */
LL_CRS_IsEnabledFreqErrorCounter(void)257 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
258 {
259 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
260 }
261
262 /**
263 * @brief Enable Automatic trimming counter
264 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
265 * @retval None
266 */
LL_CRS_EnableAutoTrimming(void)267 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
268 {
269 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
270 }
271
272 /**
273 * @brief Disable Automatic trimming counter
274 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
275 * @retval None
276 */
LL_CRS_DisableAutoTrimming(void)277 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
278 {
279 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
280 }
281
282 /**
283 * @brief Check if Automatic trimming is enabled or not
284 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
285 * @retval State of bit (1 or 0).
286 */
LL_CRS_IsEnabledAutoTrimming(void)287 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
288 {
289 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
290 }
291
292 /**
293 * @brief Set HSI48 oscillator smooth trimming
294 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
295 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
296 * @param Value a number between Min_Data = 0 and Max_Data = 63
297 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
298 * @retval None
299 */
LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)300 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
301 {
302 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
303 }
304
305 /**
306 * @brief Get HSI48 oscillator smooth trimming
307 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
308 * @retval a number between Min_Data = 0 and Max_Data = 63
309 */
LL_CRS_GetHSI48SmoothTrimming(void)310 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
311 {
312 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
313 }
314
315 /**
316 * @brief Set counter reload value
317 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
318 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
319 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
320 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
321 * @retval None
322 */
LL_CRS_SetReloadCounter(uint32_t Value)323 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
324 {
325 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
326 }
327
328 /**
329 * @brief Get counter reload value
330 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
331 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
332 */
LL_CRS_GetReloadCounter(void)333 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
334 {
335 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
336 }
337
338 /**
339 * @brief Set frequency error limit
340 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
341 * @param Value a number between Min_Data = 0 and Max_Data = 255
342 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
343 * @retval None
344 */
LL_CRS_SetFreqErrorLimit(uint32_t Value)345 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
346 {
347 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
348 }
349
350 /**
351 * @brief Get frequency error limit
352 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
353 * @retval A number between Min_Data = 0 and Max_Data = 255
354 */
LL_CRS_GetFreqErrorLimit(void)355 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
356 {
357 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
358 }
359
360 /**
361 * @brief Set division factor for SYNC signal
362 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
363 * @param Divider This parameter can be one of the following values:
364 * @arg @ref LL_CRS_SYNC_DIV_1
365 * @arg @ref LL_CRS_SYNC_DIV_2
366 * @arg @ref LL_CRS_SYNC_DIV_4
367 * @arg @ref LL_CRS_SYNC_DIV_8
368 * @arg @ref LL_CRS_SYNC_DIV_16
369 * @arg @ref LL_CRS_SYNC_DIV_32
370 * @arg @ref LL_CRS_SYNC_DIV_64
371 * @arg @ref LL_CRS_SYNC_DIV_128
372 * @retval None
373 */
LL_CRS_SetSyncDivider(uint32_t Divider)374 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
375 {
376 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
377 }
378
379 /**
380 * @brief Get division factor for SYNC signal
381 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
382 * @retval Returned value can be one of the following values:
383 * @arg @ref LL_CRS_SYNC_DIV_1
384 * @arg @ref LL_CRS_SYNC_DIV_2
385 * @arg @ref LL_CRS_SYNC_DIV_4
386 * @arg @ref LL_CRS_SYNC_DIV_8
387 * @arg @ref LL_CRS_SYNC_DIV_16
388 * @arg @ref LL_CRS_SYNC_DIV_32
389 * @arg @ref LL_CRS_SYNC_DIV_64
390 * @arg @ref LL_CRS_SYNC_DIV_128
391 */
LL_CRS_GetSyncDivider(void)392 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
393 {
394 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
395 }
396
397 /**
398 * @brief Set SYNC signal source
399 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
400 * @param Source This parameter can be one of the following values:
401 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
402 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
403 * @arg @ref LL_CRS_SYNC_SOURCE_USB
404 * @retval None
405 */
LL_CRS_SetSyncSignalSource(uint32_t Source)406 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
407 {
408 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
409 }
410
411 /**
412 * @brief Get SYNC signal source
413 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
414 * @retval Returned value can be one of the following values:
415 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
416 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
417 * @arg @ref LL_CRS_SYNC_SOURCE_USB
418 */
LL_CRS_GetSyncSignalSource(void)419 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
420 {
421 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
422 }
423
424 /**
425 * @brief Set input polarity for the SYNC signal source
426 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
427 * @param Polarity This parameter can be one of the following values:
428 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
429 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
430 * @retval None
431 */
LL_CRS_SetSyncPolarity(uint32_t Polarity)432 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
433 {
434 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
435 }
436
437 /**
438 * @brief Get input polarity for the SYNC signal source
439 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
440 * @retval Returned value can be one of the following values:
441 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
442 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
443 */
LL_CRS_GetSyncPolarity(void)444 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
445 {
446 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
447 }
448
449 /**
450 * @brief Configure CRS for the synchronization
451 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
452 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
453 * CFGR FELIM LL_CRS_ConfigSynchronization\n
454 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
455 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
456 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
457 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
458 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
459 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
460 * @param Settings This parameter can be a combination of the following values:
461 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
462 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
463 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
464 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
465 * @retval None
466 */
LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue,uint32_t ErrorLimitValue,uint32_t ReloadValue,uint32_t Settings)467 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
468 {
469 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos);
470 MODIFY_REG(CRS->CFGR,
471 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
472 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
473 }
474
475 /**
476 * @}
477 */
478
479 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
480 * @{
481 */
482
483 /**
484 * @brief Generate software SYNC event
485 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
486 * @retval None
487 */
LL_CRS_GenerateEvent_SWSYNC(void)488 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
489 {
490 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
491 }
492
493 /**
494 * @brief Get the frequency error direction latched in the time of the last
495 * SYNC event
496 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
497 * @retval Returned value can be one of the following values:
498 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
499 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
500 */
LL_CRS_GetFreqErrorDirection(void)501 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
502 {
503 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
504 }
505
506 /**
507 * @brief Get the frequency error counter value latched in the time of the last SYNC event
508 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
509 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
510 */
LL_CRS_GetFreqErrorCapture(void)511 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
512 {
513 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
514 }
515
516 /**
517 * @}
518 */
519
520 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
521 * @{
522 */
523
524 /**
525 * @brief Check if SYNC event OK signal occurred or not
526 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
527 * @retval State of bit (1 or 0).
528 */
LL_CRS_IsActiveFlag_SYNCOK(void)529 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
530 {
531 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
532 }
533
534 /**
535 * @brief Check if SYNC warning signal occurred or not
536 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
537 * @retval State of bit (1 or 0).
538 */
LL_CRS_IsActiveFlag_SYNCWARN(void)539 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
540 {
541 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
542 }
543
544 /**
545 * @brief Check if Synchronization or trimming error signal occurred or not
546 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
547 * @retval State of bit (1 or 0).
548 */
LL_CRS_IsActiveFlag_ERR(void)549 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
550 {
551 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
552 }
553
554 /**
555 * @brief Check if Expected SYNC signal occurred or not
556 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
557 * @retval State of bit (1 or 0).
558 */
LL_CRS_IsActiveFlag_ESYNC(void)559 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
560 {
561 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
562 }
563
564 /**
565 * @brief Check if SYNC error signal occurred or not
566 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
567 * @retval State of bit (1 or 0).
568 */
LL_CRS_IsActiveFlag_SYNCERR(void)569 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
570 {
571 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
572 }
573
574 /**
575 * @brief Check if SYNC missed error signal occurred or not
576 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
577 * @retval State of bit (1 or 0).
578 */
LL_CRS_IsActiveFlag_SYNCMISS(void)579 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
580 {
581 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
582 }
583
584 /**
585 * @brief Check if Trimming overflow or underflow occurred or not
586 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
587 * @retval State of bit (1 or 0).
588 */
LL_CRS_IsActiveFlag_TRIMOVF(void)589 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
590 {
591 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
592 }
593
594 /**
595 * @brief Clear the SYNC event OK flag
596 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
597 * @retval None
598 */
LL_CRS_ClearFlag_SYNCOK(void)599 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
600 {
601 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
602 }
603
604 /**
605 * @brief Clear the SYNC warning flag
606 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
607 * @retval None
608 */
LL_CRS_ClearFlag_SYNCWARN(void)609 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
610 {
611 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
612 }
613
614 /**
615 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
616 * the ERR flag
617 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
618 * @retval None
619 */
LL_CRS_ClearFlag_ERR(void)620 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
621 {
622 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
623 }
624
625 /**
626 * @brief Clear Expected SYNC flag
627 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
628 * @retval None
629 */
LL_CRS_ClearFlag_ESYNC(void)630 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
631 {
632 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
633 }
634
635 /**
636 * @}
637 */
638
639 /** @defgroup CRS_LL_EF_IT_Management IT_Management
640 * @{
641 */
642
643 /**
644 * @brief Enable SYNC event OK interrupt
645 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
646 * @retval None
647 */
LL_CRS_EnableIT_SYNCOK(void)648 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
649 {
650 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
651 }
652
653 /**
654 * @brief Disable SYNC event OK interrupt
655 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
656 * @retval None
657 */
LL_CRS_DisableIT_SYNCOK(void)658 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
659 {
660 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
661 }
662
663 /**
664 * @brief Check if SYNC event OK interrupt is enabled or not
665 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
666 * @retval State of bit (1 or 0).
667 */
LL_CRS_IsEnabledIT_SYNCOK(void)668 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
669 {
670 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
671 }
672
673 /**
674 * @brief Enable SYNC warning interrupt
675 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
676 * @retval None
677 */
LL_CRS_EnableIT_SYNCWARN(void)678 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
679 {
680 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
681 }
682
683 /**
684 * @brief Disable SYNC warning interrupt
685 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
686 * @retval None
687 */
LL_CRS_DisableIT_SYNCWARN(void)688 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
689 {
690 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
691 }
692
693 /**
694 * @brief Check if SYNC warning interrupt is enabled or not
695 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
696 * @retval State of bit (1 or 0).
697 */
LL_CRS_IsEnabledIT_SYNCWARN(void)698 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
699 {
700 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
701 }
702
703 /**
704 * @brief Enable Synchronization or trimming error interrupt
705 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
706 * @retval None
707 */
LL_CRS_EnableIT_ERR(void)708 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
709 {
710 SET_BIT(CRS->CR, CRS_CR_ERRIE);
711 }
712
713 /**
714 * @brief Disable Synchronization or trimming error interrupt
715 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
716 * @retval None
717 */
LL_CRS_DisableIT_ERR(void)718 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
719 {
720 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
721 }
722
723 /**
724 * @brief Check if Synchronization or trimming error interrupt is enabled or not
725 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
726 * @retval State of bit (1 or 0).
727 */
LL_CRS_IsEnabledIT_ERR(void)728 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
729 {
730 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
731 }
732
733 /**
734 * @brief Enable Expected SYNC interrupt
735 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
736 * @retval None
737 */
LL_CRS_EnableIT_ESYNC(void)738 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
739 {
740 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
741 }
742
743 /**
744 * @brief Disable Expected SYNC interrupt
745 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
746 * @retval None
747 */
LL_CRS_DisableIT_ESYNC(void)748 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
749 {
750 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
751 }
752
753 /**
754 * @brief Check if Expected SYNC interrupt is enabled or not
755 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
756 * @retval State of bit (1 or 0).
757 */
LL_CRS_IsEnabledIT_ESYNC(void)758 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
759 {
760 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
761 }
762
763 /**
764 * @}
765 */
766
767 #if defined(USE_FULL_LL_DRIVER)
768 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
769 * @{
770 */
771
772 ErrorStatus LL_CRS_DeInit(void);
773
774 /**
775 * @}
776 */
777 #endif /* USE_FULL_LL_DRIVER */
778
779 /**
780 * @}
781 */
782
783 /**
784 * @}
785 */
786
787 #endif /* defined(CRS) */
788
789 /**
790 * @}
791 */
792
793 #ifdef __cplusplus
794 }
795 #endif
796
797 #endif /* __STM32F0xx_LL_CRS_H */
798
799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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