1 /**
2 ******************************************************************************
3 * @file stm32f0xx_ll_tim.h
4 * @author MCD Application Team
5 * @brief Header file of TIM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F0xx_LL_TIM_H
38 #define __STM32F0xx_LL_TIM_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f0xx.h"
46
47 /** @addtogroup STM32F0xx_LL_Driver
48 * @{
49 */
50
51 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7)
52
53 /** @defgroup TIM_LL TIM
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
60 * @{
61 */
62 static const uint8_t OFFSET_TAB_CCMRx[] =
63 {
64 0x00U, /* 0: TIMx_CH1 */
65 0x00U, /* 1: TIMx_CH1N */
66 0x00U, /* 2: TIMx_CH2 */
67 0x00U, /* 3: TIMx_CH2N */
68 0x04U, /* 4: TIMx_CH3 */
69 0x04U, /* 5: TIMx_CH3N */
70 0x04U /* 6: TIMx_CH4 */
71 };
72
73 static const uint8_t SHIFT_TAB_OCxx[] =
74 {
75 0U, /* 0: OC1M, OC1FE, OC1PE */
76 0U, /* 1: - NA */
77 8U, /* 2: OC2M, OC2FE, OC2PE */
78 0U, /* 3: - NA */
79 0U, /* 4: OC3M, OC3FE, OC3PE */
80 0U, /* 5: - NA */
81 8U /* 6: OC4M, OC4FE, OC4PE */
82 };
83
84 static const uint8_t SHIFT_TAB_ICxx[] =
85 {
86 0U, /* 0: CC1S, IC1PSC, IC1F */
87 0U, /* 1: - NA */
88 8U, /* 2: CC2S, IC2PSC, IC2F */
89 0U, /* 3: - NA */
90 0U, /* 4: CC3S, IC3PSC, IC3F */
91 0U, /* 5: - NA */
92 8U /* 6: CC4S, IC4PSC, IC4F */
93 };
94
95 static const uint8_t SHIFT_TAB_CCxP[] =
96 {
97 0U, /* 0: CC1P */
98 2U, /* 1: CC1NP */
99 4U, /* 2: CC2P */
100 6U, /* 3: CC2NP */
101 8U, /* 4: CC3P */
102 10U, /* 5: CC3NP */
103 12U /* 6: CC4P */
104 };
105
106 static const uint8_t SHIFT_TAB_OISx[] =
107 {
108 0U, /* 0: OIS1 */
109 1U, /* 1: OIS1N */
110 2U, /* 2: OIS2 */
111 3U, /* 3: OIS2N */
112 4U, /* 4: OIS3 */
113 5U, /* 5: OIS3N */
114 6U /* 6: OIS4 */
115 };
116 /**
117 * @}
118 */
119
120
121 /* Private constants ---------------------------------------------------------*/
122 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
123 * @{
124 */
125
126
127 #define TIMx_OR_RMP_SHIFT 16U
128 #define TIMx_OR_RMP_MASK 0x0000FFFFU
129 #define TIM14_OR_RMP_MASK (TIM14_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
130
131 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
132 #define DT_DELAY_1 ((uint8_t)0x7FU)
133 #define DT_DELAY_2 ((uint8_t)0x3FU)
134 #define DT_DELAY_3 ((uint8_t)0x1FU)
135 #define DT_DELAY_4 ((uint8_t)0x1FU)
136
137 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
138 #define DT_RANGE_1 ((uint8_t)0x00U)
139 #define DT_RANGE_2 ((uint8_t)0x80U)
140 #define DT_RANGE_3 ((uint8_t)0xC0U)
141 #define DT_RANGE_4 ((uint8_t)0xE0U)
142
143
144 /**
145 * @}
146 */
147
148 /* Private macros ------------------------------------------------------------*/
149 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
150 * @{
151 */
152 /** @brief Convert channel id into channel index.
153 * @param __CHANNEL__ This parameter can be one of the following values:
154 * @arg @ref LL_TIM_CHANNEL_CH1
155 * @arg @ref LL_TIM_CHANNEL_CH1N
156 * @arg @ref LL_TIM_CHANNEL_CH2
157 * @arg @ref LL_TIM_CHANNEL_CH2N
158 * @arg @ref LL_TIM_CHANNEL_CH3
159 * @arg @ref LL_TIM_CHANNEL_CH3N
160 * @arg @ref LL_TIM_CHANNEL_CH4
161 * @retval none
162 */
163 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
164 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
165 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
166 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
167 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U)
170
171 /** @brief Calculate the deadtime sampling period(in ps).
172 * @param __TIMCLK__ timer input clock frequency (in Hz).
173 * @param __CKD__ This parameter can be one of the following values:
174 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
175 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
176 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
177 * @retval none
178 */
179 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
180 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
181 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
182 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
183 /**
184 * @}
185 */
186
187
188 /* Exported types ------------------------------------------------------------*/
189 #if defined(USE_FULL_LL_DRIVER)
190 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
191 * @{
192 */
193
194 /**
195 * @brief TIM Time Base configuration structure definition.
196 */
197 typedef struct
198 {
199 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
200 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
201
202 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
203
204 uint32_t CounterMode; /*!< Specifies the counter mode.
205 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
206
207 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
208
209 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
210 Auto-Reload Register at the next update event.
211 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
212 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
213
214 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
215
216 uint32_t ClockDivision; /*!< Specifies the clock division.
217 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
218
219 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
220
221 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
222 reaches zero, an update event is generated and counting restarts
223 from the RCR value (N).
224 This means in PWM mode that (N+1) corresponds to:
225 - the number of PWM periods in edge-aligned mode
226 - the number of half PWM period in center-aligned mode
227 This parameter must be a number between 0x00 and 0xFF.
228
229 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
230 } LL_TIM_InitTypeDef;
231
232 /**
233 * @brief TIM Output Compare configuration structure definition.
234 */
235 typedef struct
236 {
237 uint32_t OCMode; /*!< Specifies the output mode.
238 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
239
240 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
241
242 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
243 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
244
245 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
246
247 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
248 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
249
250 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
251
252 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
253 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
254
255 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
256
257 uint32_t OCPolarity; /*!< Specifies the output polarity.
258 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
259
260 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
261
262 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
263 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
264
265 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
266
267
268 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
269 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
270
271 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
272
273 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
274 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
275
276 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
277 } LL_TIM_OC_InitTypeDef;
278
279 /**
280 * @brief TIM Input Capture configuration structure definition.
281 */
282
283 typedef struct
284 {
285
286 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
287 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
288
289 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
290
291 uint32_t ICActiveInput; /*!< Specifies the input.
292 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
293
294 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
295
296 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
297 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
298
299 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
300
301 uint32_t ICFilter; /*!< Specifies the input capture filter.
302 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
303
304 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
305 } LL_TIM_IC_InitTypeDef;
306
307
308 /**
309 * @brief TIM Encoder interface configuration structure definition.
310 */
311 typedef struct
312 {
313 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
314 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
315
316 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
317
318 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
319 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
320
321 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
322
323 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
324 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
325
326 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
327
328 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
329 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
330
331 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
332
333 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
334 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
335
336 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
337
338 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
339 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
340
341 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
342
343 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
344 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
345
346 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
347
348 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
349 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
350
351 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
352
353 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
354 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
355
356 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
357
358 } LL_TIM_ENCODER_InitTypeDef;
359
360 /**
361 * @brief TIM Hall sensor interface configuration structure definition.
362 */
363 typedef struct
364 {
365
366 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
367 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
368
369 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
370
371 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
372 Prescaler must be set to get a maximum counter period longer than the
373 time interval between 2 consecutive changes on the Hall inputs.
374 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
375
376 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
377
378 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
379 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
380
381 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
382
383 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
384 A positive pulse (TRGO event) is generated with a programmable delay every time
385 a change occurs on the Hall inputs.
386 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
387
388 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
389 } LL_TIM_HALLSENSOR_InitTypeDef;
390
391 /**
392 * @brief BDTR (Break and Dead Time) structure definition
393 */
394 typedef struct
395 {
396 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
397 This parameter can be a value of @ref TIM_LL_EC_OSSR
398
399 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
400
401 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
402
403 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
404 This parameter can be a value of @ref TIM_LL_EC_OSSI
405
406 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
407
408 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
409
410 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
411 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
412
413 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
414 has been written, their content is frozen until the next reset.*/
415
416 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
417 switching-on of the outputs.
418 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
419
420 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
421
422 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
423
424 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
425 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
426
427 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
428
429 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
430
431 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
432 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
433
434 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
435
436 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
437
438 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
439 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
440
441 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
442
443 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
444 } LL_TIM_BDTR_InitTypeDef;
445
446 /**
447 * @}
448 */
449 #endif /* USE_FULL_LL_DRIVER */
450
451 /* Exported constants --------------------------------------------------------*/
452 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
453 * @{
454 */
455
456 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
457 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
458 * @{
459 */
460 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
461 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
462 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
463 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
464 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
465 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
466 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
467 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
468 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
469 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
470 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
471 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
472 /**
473 * @}
474 */
475
476 #if defined(USE_FULL_LL_DRIVER)
477 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
478 * @{
479 */
480 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
481 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
482 /**
483 * @}
484 */
485
486 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
487 * @{
488 */
489 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
490 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
491 /**
492 * @}
493 */
494 #endif /* USE_FULL_LL_DRIVER */
495
496 /** @defgroup TIM_LL_EC_IT IT Defines
497 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
498 * @{
499 */
500 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
501 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
502 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
503 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
504 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
505 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
506 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
507 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
508 /**
509 * @}
510 */
511
512 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
513 * @{
514 */
515 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
516 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
517 /**
518 * @}
519 */
520
521 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
522 * @{
523 */
524 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
525 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
526 /**
527 * @}
528 */
529
530 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
531 * @{
532 */
533 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
534 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
535 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
536 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
537 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
538 /**
539 * @}
540 */
541
542 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
543 * @{
544 */
545 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
546 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
547 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
548 /**
549 * @}
550 */
551
552 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
553 * @{
554 */
555 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
556 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
557 /**
558 * @}
559 */
560
561 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
562 * @{
563 */
564 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
565 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
566 /**
567 * @}
568 */
569
570 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
571 * @{
572 */
573 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
574 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
575 /**
576 * @}
577 */
578
579 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
580 * @{
581 */
582 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
583 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
584 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
585 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
586 /**
587 * @}
588 */
589
590 /** @defgroup TIM_LL_EC_CHANNEL Channel
591 * @{
592 */
593 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
594 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
595 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
596 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
597 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
598 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
599 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
600 /**
601 * @}
602 */
603
604 #if defined(USE_FULL_LL_DRIVER)
605 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
606 * @{
607 */
608 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
609 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
610 /**
611 * @}
612 */
613 #endif /* USE_FULL_LL_DRIVER */
614
615 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
616 * @{
617 */
618 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
619 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
620 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
621 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
622 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
623 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
624 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
625 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
626 /**
627 * @}
628 */
629
630 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
631 * @{
632 */
633 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
634 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
635 /**
636 * @}
637 */
638
639 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
640 * @{
641 */
642 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
643 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
644 /**
645 * @}
646 */
647
648
649 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
650 * @{
651 */
652 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
653 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
654 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
655 /**
656 * @}
657 */
658
659 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
660 * @{
661 */
662 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
663 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
664 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
665 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
666 /**
667 * @}
668 */
669
670 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
671 * @{
672 */
673 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
674 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
675 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
676 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
677 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
678 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
679 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
680 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
681 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
682 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
683 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
684 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
685 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
686 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
687 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
688 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
689 /**
690 * @}
691 */
692
693 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
694 * @{
695 */
696 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
697 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
698 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
699 /**
700 * @}
701 */
702
703 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
704 * @{
705 */
706 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
707 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
708 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
709 /**
710 * @}
711 */
712
713 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
714 * @{
715 */
716 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
717 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
718 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
719 /**
720 * @}
721 */
722
723 /** @defgroup TIM_LL_EC_TRGO Trigger Output
724 * @{
725 */
726 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
727 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
728 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
729 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
730 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
731 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
732 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
733 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
734 /**
735 * @}
736 */
737
738
739 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
740 * @{
741 */
742 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
743 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
744 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
745 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
746 /**
747 * @}
748 */
749
750 /** @defgroup TIM_LL_EC_TS Trigger Selection
751 * @{
752 */
753 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
754 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
755 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
756 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
757 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
758 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
759 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
760 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
761 /**
762 * @}
763 */
764
765 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
766 * @{
767 */
768 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
769 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
770 /**
771 * @}
772 */
773
774 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
775 * @{
776 */
777 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
778 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
779 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
780 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
781 /**
782 * @}
783 */
784
785 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
786 * @{
787 */
788 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
789 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
790 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
791 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
792 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
793 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
794 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
795 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
796 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
797 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
798 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
799 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
800 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
801 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
802 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
803 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
804 /**
805 * @}
806 */
807
808
809 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
810 * @{
811 */
812 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
813 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
814 /**
815 * @}
816 */
817
818
819
820
821 /** @defgroup TIM_LL_EC_OSSI OSSI
822 * @{
823 */
824 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
825 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
826 /**
827 * @}
828 */
829
830 /** @defgroup TIM_LL_EC_OSSR OSSR
831 * @{
832 */
833 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
834 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
835 /**
836 * @}
837 */
838
839
840 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
841 * @{
842 */
843 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
844 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
845 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
846 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
847 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
848 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
849 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
850 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
851 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
852 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
853 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
854 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
855 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
856 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
857 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
858 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
859 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
860 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
861
862
863 /**
864 * @}
865 */
866
867 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
868 * @{
869 */
870 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
871 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
872 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
873 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
874 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
875 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
876 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
877 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
878 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
879 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
880 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
881 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
882 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
883 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
884 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
885 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
886 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
887 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
888 /**
889 * @}
890 */
891
892
893 #define LL_TIM_TIM14_TI1_RMP_GPIO TIM14_OR_RMP_MASK /*!< TIM14_TI1 is connected to Ored GPIO */
894 #define LL_TIM_TIM14_TI1_RMP_RTC_CLK (TIM14_OR_TI1_RMP_0 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to RTC clock */
895 #define LL_TIM_TIM14_TI1_RMP_HSE (TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to HSE/32 clock */
896 #define LL_TIM_TIM14_TI1_RMP_MCO (TIM14_OR_TI1_RMP_0 | TIM14_OR_TI1_RMP_1 | TIM14_OR_RMP_MASK) /*!< TIM14_TI1 is connected to MCO */
897
898
899 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
900 * @{
901 */
902 #define LL_TIM_OCREF_CLR_INT_OCREF_CLR 0x00000000U /*!< OCREF_CLR_INT is connected to the OCREF_CLR input */
903 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */
904 /**
905 * @}
906 */
907
908 /**
909 * @}
910 */
911
912 /* Exported macro ------------------------------------------------------------*/
913 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
914 * @{
915 */
916
917 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
918 * @{
919 */
920 /**
921 * @brief Write a value in TIM register.
922 * @param __INSTANCE__ TIM Instance
923 * @param __REG__ Register to be written
924 * @param __VALUE__ Value to be written in the register
925 * @retval None
926 */
927 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
928
929 /**
930 * @brief Read a value in TIM register.
931 * @param __INSTANCE__ TIM Instance
932 * @param __REG__ Register to be read
933 * @retval Register value
934 */
935 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
936 /**
937 * @}
938 */
939
940 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
941 * @{
942 */
943
944 /**
945 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
946 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
947 * @param __TIMCLK__ timer input clock frequency (in Hz)
948 * @param __CKD__ This parameter can be one of the following values:
949 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
950 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
951 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
952 * @param __DT__ deadtime duration (in ns)
953 * @retval DTG[0:7]
954 */
955 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
956 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
957 (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
958 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
959 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
960 0U)
961
962 /**
963 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
964 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
965 * @param __TIMCLK__ timer input clock frequency (in Hz)
966 * @param __CNTCLK__ counter clock frequency (in Hz)
967 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
968 */
969 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
970 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
971
972 /**
973 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
974 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
975 * @param __TIMCLK__ timer input clock frequency (in Hz)
976 * @param __PSC__ prescaler
977 * @param __FREQ__ output signal frequency (in Hz)
978 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
979 */
980 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
981 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
982
983 /**
984 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
985 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
986 * @param __TIMCLK__ timer input clock frequency (in Hz)
987 * @param __PSC__ prescaler
988 * @param __DELAY__ timer output compare active/inactive delay (in us)
989 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
990 */
991 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
992 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
993 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
994
995 /**
996 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
997 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
998 * @param __TIMCLK__ timer input clock frequency (in Hz)
999 * @param __PSC__ prescaler
1000 * @param __DELAY__ timer output compare active/inactive delay (in us)
1001 * @param __PULSE__ pulse duration (in us)
1002 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1003 */
1004 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1005 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1006 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1007
1008 /**
1009 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1010 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1011 * @param __ICPSC__ This parameter can be one of the following values:
1012 * @arg @ref LL_TIM_ICPSC_DIV1
1013 * @arg @ref LL_TIM_ICPSC_DIV2
1014 * @arg @ref LL_TIM_ICPSC_DIV4
1015 * @arg @ref LL_TIM_ICPSC_DIV8
1016 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1017 */
1018 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1019 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1020
1021
1022 /**
1023 * @}
1024 */
1025
1026
1027 /**
1028 * @}
1029 */
1030
1031 /* Exported functions --------------------------------------------------------*/
1032 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1033 * @{
1034 */
1035
1036 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1037 * @{
1038 */
1039 /**
1040 * @brief Enable timer counter.
1041 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1042 * @param TIMx Timer instance
1043 * @retval None
1044 */
LL_TIM_EnableCounter(TIM_TypeDef * TIMx)1045 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1046 {
1047 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1048 }
1049
1050 /**
1051 * @brief Disable timer counter.
1052 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1053 * @param TIMx Timer instance
1054 * @retval None
1055 */
LL_TIM_DisableCounter(TIM_TypeDef * TIMx)1056 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1057 {
1058 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1059 }
1060
1061 /**
1062 * @brief Indicates whether the timer counter is enabled.
1063 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1064 * @param TIMx Timer instance
1065 * @retval State of bit (1 or 0).
1066 */
LL_TIM_IsEnabledCounter(TIM_TypeDef * TIMx)1067 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1068 {
1069 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
1070 }
1071
1072 /**
1073 * @brief Enable update event generation.
1074 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1075 * @param TIMx Timer instance
1076 * @retval None
1077 */
LL_TIM_EnableUpdateEvent(TIM_TypeDef * TIMx)1078 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1079 {
1080 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1081 }
1082
1083 /**
1084 * @brief Disable update event generation.
1085 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1086 * @param TIMx Timer instance
1087 * @retval None
1088 */
LL_TIM_DisableUpdateEvent(TIM_TypeDef * TIMx)1089 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1090 {
1091 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1092 }
1093
1094 /**
1095 * @brief Indicates whether update event generation is enabled.
1096 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1097 * @param TIMx Timer instance
1098 * @retval Inverted state of bit (0 or 1).
1099 */
LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef * TIMx)1100 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1101 {
1102 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
1103 }
1104
1105 /**
1106 * @brief Set update event source
1107 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1108 * generate an update interrupt or DMA request if enabled:
1109 * - Counter overflow/underflow
1110 * - Setting the UG bit
1111 * - Update generation through the slave mode controller
1112 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1113 * overflow/underflow generates an update interrupt or DMA request if enabled.
1114 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1115 * @param TIMx Timer instance
1116 * @param UpdateSource This parameter can be one of the following values:
1117 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1118 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1119 * @retval None
1120 */
LL_TIM_SetUpdateSource(TIM_TypeDef * TIMx,uint32_t UpdateSource)1121 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1122 {
1123 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1124 }
1125
1126 /**
1127 * @brief Get actual event update source
1128 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1129 * @param TIMx Timer instance
1130 * @retval Returned value can be one of the following values:
1131 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1132 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1133 */
LL_TIM_GetUpdateSource(TIM_TypeDef * TIMx)1134 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1135 {
1136 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1137 }
1138
1139 /**
1140 * @brief Set one pulse mode (one shot v.s. repetitive).
1141 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1142 * @param TIMx Timer instance
1143 * @param OnePulseMode This parameter can be one of the following values:
1144 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1145 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1146 * @retval None
1147 */
LL_TIM_SetOnePulseMode(TIM_TypeDef * TIMx,uint32_t OnePulseMode)1148 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1149 {
1150 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1151 }
1152
1153 /**
1154 * @brief Get actual one pulse mode.
1155 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1156 * @param TIMx Timer instance
1157 * @retval Returned value can be one of the following values:
1158 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1159 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1160 */
LL_TIM_GetOnePulseMode(TIM_TypeDef * TIMx)1161 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1162 {
1163 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1164 }
1165
1166 /**
1167 * @brief Set the timer counter counting mode.
1168 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1169 * check whether or not the counter mode selection feature is supported
1170 * by a timer instance.
1171 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1172 * CR1 CMS LL_TIM_SetCounterMode
1173 * @param TIMx Timer instance
1174 * @param CounterMode This parameter can be one of the following values:
1175 * @arg @ref LL_TIM_COUNTERMODE_UP
1176 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1177 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1178 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1179 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1180 * @retval None
1181 */
LL_TIM_SetCounterMode(TIM_TypeDef * TIMx,uint32_t CounterMode)1182 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1183 {
1184 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
1185 }
1186
1187 /**
1188 * @brief Get actual counter mode.
1189 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1190 * check whether or not the counter mode selection feature is supported
1191 * by a timer instance.
1192 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1193 * CR1 CMS LL_TIM_GetCounterMode
1194 * @param TIMx Timer instance
1195 * @retval Returned value can be one of the following values:
1196 * @arg @ref LL_TIM_COUNTERMODE_UP
1197 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1198 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1199 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1200 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1201 */
LL_TIM_GetCounterMode(TIM_TypeDef * TIMx)1202 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1203 {
1204 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1205 }
1206
1207 /**
1208 * @brief Enable auto-reload (ARR) preload.
1209 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1210 * @param TIMx Timer instance
1211 * @retval None
1212 */
LL_TIM_EnableARRPreload(TIM_TypeDef * TIMx)1213 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1214 {
1215 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1216 }
1217
1218 /**
1219 * @brief Disable auto-reload (ARR) preload.
1220 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1221 * @param TIMx Timer instance
1222 * @retval None
1223 */
LL_TIM_DisableARRPreload(TIM_TypeDef * TIMx)1224 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1225 {
1226 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1227 }
1228
1229 /**
1230 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1231 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1232 * @param TIMx Timer instance
1233 * @retval State of bit (1 or 0).
1234 */
LL_TIM_IsEnabledARRPreload(TIM_TypeDef * TIMx)1235 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1236 {
1237 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
1238 }
1239
1240 /**
1241 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1242 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1243 * whether or not the clock division feature is supported by the timer
1244 * instance.
1245 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1246 * @param TIMx Timer instance
1247 * @param ClockDivision This parameter can be one of the following values:
1248 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1249 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1250 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1251 * @retval None
1252 */
LL_TIM_SetClockDivision(TIM_TypeDef * TIMx,uint32_t ClockDivision)1253 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1254 {
1255 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1256 }
1257
1258 /**
1259 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1260 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1261 * whether or not the clock division feature is supported by the timer
1262 * instance.
1263 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1264 * @param TIMx Timer instance
1265 * @retval Returned value can be one of the following values:
1266 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1267 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1268 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1269 */
LL_TIM_GetClockDivision(TIM_TypeDef * TIMx)1270 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1271 {
1272 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1273 }
1274
1275 /**
1276 * @brief Set the counter value.
1277 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1278 * whether or not a timer instance supports a 32 bits counter.
1279 * @rmtoll CNT CNT LL_TIM_SetCounter
1280 * @param TIMx Timer instance
1281 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1282 * @retval None
1283 */
LL_TIM_SetCounter(TIM_TypeDef * TIMx,uint32_t Counter)1284 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1285 {
1286 WRITE_REG(TIMx->CNT, Counter);
1287 }
1288
1289 /**
1290 * @brief Get the counter value.
1291 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1292 * whether or not a timer instance supports a 32 bits counter.
1293 * @rmtoll CNT CNT LL_TIM_GetCounter
1294 * @param TIMx Timer instance
1295 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1296 */
LL_TIM_GetCounter(TIM_TypeDef * TIMx)1297 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1298 {
1299 return (uint32_t)(READ_REG(TIMx->CNT));
1300 }
1301
1302 /**
1303 * @brief Get the current direction of the counter
1304 * @rmtoll CR1 DIR LL_TIM_GetDirection
1305 * @param TIMx Timer instance
1306 * @retval Returned value can be one of the following values:
1307 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1308 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1309 */
LL_TIM_GetDirection(TIM_TypeDef * TIMx)1310 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1311 {
1312 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1313 }
1314
1315 /**
1316 * @brief Set the prescaler value.
1317 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1318 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1319 * prescaler ratio is taken into account at the next update event.
1320 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1321 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1322 * @param TIMx Timer instance
1323 * @param Prescaler between Min_Data=0 and Max_Data=65535
1324 * @retval None
1325 */
LL_TIM_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Prescaler)1326 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1327 {
1328 WRITE_REG(TIMx->PSC, Prescaler);
1329 }
1330
1331 /**
1332 * @brief Get the prescaler value.
1333 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1334 * @param TIMx Timer instance
1335 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1336 */
LL_TIM_GetPrescaler(TIM_TypeDef * TIMx)1337 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1338 {
1339 return (uint32_t)(READ_REG(TIMx->PSC));
1340 }
1341
1342 /**
1343 * @brief Set the auto-reload value.
1344 * @note The counter is blocked while the auto-reload value is null.
1345 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1346 * whether or not a timer instance supports a 32 bits counter.
1347 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1348 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1349 * @param TIMx Timer instance
1350 * @param AutoReload between Min_Data=0 and Max_Data=65535
1351 * @retval None
1352 */
LL_TIM_SetAutoReload(TIM_TypeDef * TIMx,uint32_t AutoReload)1353 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1354 {
1355 WRITE_REG(TIMx->ARR, AutoReload);
1356 }
1357
1358 /**
1359 * @brief Get the auto-reload value.
1360 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1361 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1362 * whether or not a timer instance supports a 32 bits counter.
1363 * @param TIMx Timer instance
1364 * @retval Auto-reload value
1365 */
LL_TIM_GetAutoReload(TIM_TypeDef * TIMx)1366 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1367 {
1368 return (uint32_t)(READ_REG(TIMx->ARR));
1369 }
1370
1371 /**
1372 * @brief Set the repetition counter value.
1373 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1374 * whether or not a timer instance supports a repetition counter.
1375 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1376 * @param TIMx Timer instance
1377 * @param RepetitionCounter between Min_Data=0 and Max_Data=255
1378 * @retval None
1379 */
LL_TIM_SetRepetitionCounter(TIM_TypeDef * TIMx,uint32_t RepetitionCounter)1380 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1381 {
1382 WRITE_REG(TIMx->RCR, RepetitionCounter);
1383 }
1384
1385 /**
1386 * @brief Get the repetition counter value.
1387 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1388 * whether or not a timer instance supports a repetition counter.
1389 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1390 * @param TIMx Timer instance
1391 * @retval Repetition counter value
1392 */
LL_TIM_GetRepetitionCounter(TIM_TypeDef * TIMx)1393 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1394 {
1395 return (uint32_t)(READ_REG(TIMx->RCR));
1396 }
1397
1398 /**
1399 * @}
1400 */
1401
1402 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1403 * @{
1404 */
1405 /**
1406 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1407 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1408 * they are updated only when a commutation event (COM) occurs.
1409 * @note Only on channels that have a complementary output.
1410 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1411 * whether or not a timer instance is able to generate a commutation event.
1412 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1413 * @param TIMx Timer instance
1414 * @retval None
1415 */
LL_TIM_CC_EnablePreload(TIM_TypeDef * TIMx)1416 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1417 {
1418 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1419 }
1420
1421 /**
1422 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1423 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1424 * whether or not a timer instance is able to generate a commutation event.
1425 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1426 * @param TIMx Timer instance
1427 * @retval None
1428 */
LL_TIM_CC_DisablePreload(TIM_TypeDef * TIMx)1429 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1430 {
1431 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1432 }
1433
1434 /**
1435 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1436 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1437 * whether or not a timer instance is able to generate a commutation event.
1438 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1439 * @param TIMx Timer instance
1440 * @param CCUpdateSource This parameter can be one of the following values:
1441 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1442 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1443 * @retval None
1444 */
LL_TIM_CC_SetUpdate(TIM_TypeDef * TIMx,uint32_t CCUpdateSource)1445 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1446 {
1447 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1448 }
1449
1450 /**
1451 * @brief Set the trigger of the capture/compare DMA request.
1452 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1453 * @param TIMx Timer instance
1454 * @param DMAReqTrigger This parameter can be one of the following values:
1455 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1456 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1457 * @retval None
1458 */
LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef * TIMx,uint32_t DMAReqTrigger)1459 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1460 {
1461 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1462 }
1463
1464 /**
1465 * @brief Get actual trigger of the capture/compare DMA request.
1466 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1467 * @param TIMx Timer instance
1468 * @retval Returned value can be one of the following values:
1469 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1470 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1471 */
LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef * TIMx)1472 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1473 {
1474 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1475 }
1476
1477 /**
1478 * @brief Set the lock level to freeze the
1479 * configuration of several capture/compare parameters.
1480 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1481 * the lock mechanism is supported by a timer instance.
1482 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1483 * @param TIMx Timer instance
1484 * @param LockLevel This parameter can be one of the following values:
1485 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1486 * @arg @ref LL_TIM_LOCKLEVEL_1
1487 * @arg @ref LL_TIM_LOCKLEVEL_2
1488 * @arg @ref LL_TIM_LOCKLEVEL_3
1489 * @retval None
1490 */
LL_TIM_CC_SetLockLevel(TIM_TypeDef * TIMx,uint32_t LockLevel)1491 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1492 {
1493 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1494 }
1495
1496 /**
1497 * @brief Enable capture/compare channels.
1498 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1499 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1500 * CCER CC2E LL_TIM_CC_EnableChannel\n
1501 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1502 * CCER CC3E LL_TIM_CC_EnableChannel\n
1503 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1504 * CCER CC4E LL_TIM_CC_EnableChannel
1505 * @param TIMx Timer instance
1506 * @param Channels This parameter can be a combination of the following values:
1507 * @arg @ref LL_TIM_CHANNEL_CH1
1508 * @arg @ref LL_TIM_CHANNEL_CH1N
1509 * @arg @ref LL_TIM_CHANNEL_CH2
1510 * @arg @ref LL_TIM_CHANNEL_CH2N
1511 * @arg @ref LL_TIM_CHANNEL_CH3
1512 * @arg @ref LL_TIM_CHANNEL_CH3N
1513 * @arg @ref LL_TIM_CHANNEL_CH4
1514 * @retval None
1515 */
LL_TIM_CC_EnableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1516 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1517 {
1518 SET_BIT(TIMx->CCER, Channels);
1519 }
1520
1521 /**
1522 * @brief Disable capture/compare channels.
1523 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1524 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1525 * CCER CC2E LL_TIM_CC_DisableChannel\n
1526 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1527 * CCER CC3E LL_TIM_CC_DisableChannel\n
1528 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1529 * CCER CC4E LL_TIM_CC_DisableChannel
1530 * @param TIMx Timer instance
1531 * @param Channels This parameter can be a combination of the following values:
1532 * @arg @ref LL_TIM_CHANNEL_CH1
1533 * @arg @ref LL_TIM_CHANNEL_CH1N
1534 * @arg @ref LL_TIM_CHANNEL_CH2
1535 * @arg @ref LL_TIM_CHANNEL_CH2N
1536 * @arg @ref LL_TIM_CHANNEL_CH3
1537 * @arg @ref LL_TIM_CHANNEL_CH3N
1538 * @arg @ref LL_TIM_CHANNEL_CH4
1539 * @retval None
1540 */
LL_TIM_CC_DisableChannel(TIM_TypeDef * TIMx,uint32_t Channels)1541 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1542 {
1543 CLEAR_BIT(TIMx->CCER, Channels);
1544 }
1545
1546 /**
1547 * @brief Indicate whether channel(s) is(are) enabled.
1548 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1549 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1550 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1551 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1552 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1553 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1554 * CCER CC4E LL_TIM_CC_IsEnabledChannel
1555 * @param TIMx Timer instance
1556 * @param Channels This parameter can be a combination of the following values:
1557 * @arg @ref LL_TIM_CHANNEL_CH1
1558 * @arg @ref LL_TIM_CHANNEL_CH1N
1559 * @arg @ref LL_TIM_CHANNEL_CH2
1560 * @arg @ref LL_TIM_CHANNEL_CH2N
1561 * @arg @ref LL_TIM_CHANNEL_CH3
1562 * @arg @ref LL_TIM_CHANNEL_CH3N
1563 * @arg @ref LL_TIM_CHANNEL_CH4
1564 * @retval State of bit (1 or 0).
1565 */
LL_TIM_CC_IsEnabledChannel(TIM_TypeDef * TIMx,uint32_t Channels)1566 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1567 {
1568 return (READ_BIT(TIMx->CCER, Channels) == (Channels));
1569 }
1570
1571 /**
1572 * @}
1573 */
1574
1575 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1576 * @{
1577 */
1578 /**
1579 * @brief Configure an output channel.
1580 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1581 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1582 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1583 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1584 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1585 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1586 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1587 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1588 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1589 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1590 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1591 * CR2 OIS4 LL_TIM_OC_ConfigOutput
1592 * @param TIMx Timer instance
1593 * @param Channel This parameter can be one of the following values:
1594 * @arg @ref LL_TIM_CHANNEL_CH1
1595 * @arg @ref LL_TIM_CHANNEL_CH2
1596 * @arg @ref LL_TIM_CHANNEL_CH3
1597 * @arg @ref LL_TIM_CHANNEL_CH4
1598 * @param Configuration This parameter must be a combination of all the following values:
1599 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1600 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1601 * @retval None
1602 */
LL_TIM_OC_ConfigOutput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)1603 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1604 {
1605 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1606 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1607 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1608 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1609 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1610 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1611 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1612 }
1613
1614 /**
1615 * @brief Define the behavior of the output reference signal OCxREF from which
1616 * OCx and OCxN (when relevant) are derived.
1617 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1618 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1619 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1620 * CCMR2 OC4M LL_TIM_OC_SetMode
1621 * @param TIMx Timer instance
1622 * @param Channel This parameter can be one of the following values:
1623 * @arg @ref LL_TIM_CHANNEL_CH1
1624 * @arg @ref LL_TIM_CHANNEL_CH2
1625 * @arg @ref LL_TIM_CHANNEL_CH3
1626 * @arg @ref LL_TIM_CHANNEL_CH4
1627 * @param Mode This parameter can be one of the following values:
1628 * @arg @ref LL_TIM_OCMODE_FROZEN
1629 * @arg @ref LL_TIM_OCMODE_ACTIVE
1630 * @arg @ref LL_TIM_OCMODE_INACTIVE
1631 * @arg @ref LL_TIM_OCMODE_TOGGLE
1632 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1633 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1634 * @arg @ref LL_TIM_OCMODE_PWM1
1635 * @arg @ref LL_TIM_OCMODE_PWM2
1636 * @retval None
1637 */
LL_TIM_OC_SetMode(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Mode)1638 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1639 {
1640 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1641 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1642 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1643 }
1644
1645 /**
1646 * @brief Get the output compare mode of an output channel.
1647 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1648 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1649 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1650 * CCMR2 OC4M LL_TIM_OC_GetMode
1651 * @param TIMx Timer instance
1652 * @param Channel This parameter can be one of the following values:
1653 * @arg @ref LL_TIM_CHANNEL_CH1
1654 * @arg @ref LL_TIM_CHANNEL_CH2
1655 * @arg @ref LL_TIM_CHANNEL_CH3
1656 * @arg @ref LL_TIM_CHANNEL_CH4
1657 * @retval Returned value can be one of the following values:
1658 * @arg @ref LL_TIM_OCMODE_FROZEN
1659 * @arg @ref LL_TIM_OCMODE_ACTIVE
1660 * @arg @ref LL_TIM_OCMODE_INACTIVE
1661 * @arg @ref LL_TIM_OCMODE_TOGGLE
1662 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1663 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1664 * @arg @ref LL_TIM_OCMODE_PWM1
1665 * @arg @ref LL_TIM_OCMODE_PWM2
1666 */
LL_TIM_OC_GetMode(TIM_TypeDef * TIMx,uint32_t Channel)1667 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
1668 {
1669 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1670 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1671 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1672 }
1673
1674 /**
1675 * @brief Set the polarity of an output channel.
1676 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1677 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1678 * CCER CC2P LL_TIM_OC_SetPolarity\n
1679 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1680 * CCER CC3P LL_TIM_OC_SetPolarity\n
1681 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1682 * CCER CC4P LL_TIM_OC_SetPolarity
1683 * @param TIMx Timer instance
1684 * @param Channel This parameter can be one of the following values:
1685 * @arg @ref LL_TIM_CHANNEL_CH1
1686 * @arg @ref LL_TIM_CHANNEL_CH1N
1687 * @arg @ref LL_TIM_CHANNEL_CH2
1688 * @arg @ref LL_TIM_CHANNEL_CH2N
1689 * @arg @ref LL_TIM_CHANNEL_CH3
1690 * @arg @ref LL_TIM_CHANNEL_CH3N
1691 * @arg @ref LL_TIM_CHANNEL_CH4
1692 * @param Polarity This parameter can be one of the following values:
1693 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1694 * @arg @ref LL_TIM_OCPOLARITY_LOW
1695 * @retval None
1696 */
LL_TIM_OC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Polarity)1697 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
1698 {
1699 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1700 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
1701 }
1702
1703 /**
1704 * @brief Get the polarity of an output channel.
1705 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
1706 * CCER CC1NP LL_TIM_OC_GetPolarity\n
1707 * CCER CC2P LL_TIM_OC_GetPolarity\n
1708 * CCER CC2NP LL_TIM_OC_GetPolarity\n
1709 * CCER CC3P LL_TIM_OC_GetPolarity\n
1710 * CCER CC3NP LL_TIM_OC_GetPolarity\n
1711 * CCER CC4P LL_TIM_OC_GetPolarity
1712 * @param TIMx Timer instance
1713 * @param Channel This parameter can be one of the following values:
1714 * @arg @ref LL_TIM_CHANNEL_CH1
1715 * @arg @ref LL_TIM_CHANNEL_CH1N
1716 * @arg @ref LL_TIM_CHANNEL_CH2
1717 * @arg @ref LL_TIM_CHANNEL_CH2N
1718 * @arg @ref LL_TIM_CHANNEL_CH3
1719 * @arg @ref LL_TIM_CHANNEL_CH3N
1720 * @arg @ref LL_TIM_CHANNEL_CH4
1721 * @retval Returned value can be one of the following values:
1722 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1723 * @arg @ref LL_TIM_OCPOLARITY_LOW
1724 */
LL_TIM_OC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)1725 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
1726 {
1727 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1728 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
1729 }
1730
1731 /**
1732 * @brief Set the IDLE state of an output channel
1733 * @note This function is significant only for the timer instances
1734 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
1735 * can be used to check whether or not a timer instance provides
1736 * a break input.
1737 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
1738 * CR2 OIS1N LL_TIM_OC_SetIdleState\n
1739 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
1740 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
1741 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
1742 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
1743 * CR2 OIS4 LL_TIM_OC_SetIdleState
1744 * @param TIMx Timer instance
1745 * @param Channel This parameter can be one of the following values:
1746 * @arg @ref LL_TIM_CHANNEL_CH1
1747 * @arg @ref LL_TIM_CHANNEL_CH1N
1748 * @arg @ref LL_TIM_CHANNEL_CH2
1749 * @arg @ref LL_TIM_CHANNEL_CH2N
1750 * @arg @ref LL_TIM_CHANNEL_CH3
1751 * @arg @ref LL_TIM_CHANNEL_CH3N
1752 * @arg @ref LL_TIM_CHANNEL_CH4
1753 * @param IdleState This parameter can be one of the following values:
1754 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1755 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1756 * @retval None
1757 */
LL_TIM_OC_SetIdleState(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t IdleState)1758 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
1759 {
1760 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1761 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
1762 }
1763
1764 /**
1765 * @brief Get the IDLE state of an output channel
1766 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
1767 * CR2 OIS1N LL_TIM_OC_GetIdleState\n
1768 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
1769 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
1770 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
1771 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
1772 * CR2 OIS4 LL_TIM_OC_GetIdleState
1773 * @param TIMx Timer instance
1774 * @param Channel This parameter can be one of the following values:
1775 * @arg @ref LL_TIM_CHANNEL_CH1
1776 * @arg @ref LL_TIM_CHANNEL_CH1N
1777 * @arg @ref LL_TIM_CHANNEL_CH2
1778 * @arg @ref LL_TIM_CHANNEL_CH2N
1779 * @arg @ref LL_TIM_CHANNEL_CH3
1780 * @arg @ref LL_TIM_CHANNEL_CH3N
1781 * @arg @ref LL_TIM_CHANNEL_CH4
1782 * @retval Returned value can be one of the following values:
1783 * @arg @ref LL_TIM_OCIDLESTATE_LOW
1784 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
1785 */
LL_TIM_OC_GetIdleState(TIM_TypeDef * TIMx,uint32_t Channel)1786 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
1787 {
1788 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1789 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
1790 }
1791
1792 /**
1793 * @brief Enable fast mode for the output channel.
1794 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
1795 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
1796 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
1797 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
1798 * CCMR2 OC4FE LL_TIM_OC_EnableFast
1799 * @param TIMx Timer instance
1800 * @param Channel This parameter can be one of the following values:
1801 * @arg @ref LL_TIM_CHANNEL_CH1
1802 * @arg @ref LL_TIM_CHANNEL_CH2
1803 * @arg @ref LL_TIM_CHANNEL_CH3
1804 * @arg @ref LL_TIM_CHANNEL_CH4
1805 * @retval None
1806 */
LL_TIM_OC_EnableFast(TIM_TypeDef * TIMx,uint32_t Channel)1807 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1808 {
1809 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1810 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1811 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1812
1813 }
1814
1815 /**
1816 * @brief Disable fast mode for the output channel.
1817 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
1818 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
1819 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
1820 * CCMR2 OC4FE LL_TIM_OC_DisableFast
1821 * @param TIMx Timer instance
1822 * @param Channel This parameter can be one of the following values:
1823 * @arg @ref LL_TIM_CHANNEL_CH1
1824 * @arg @ref LL_TIM_CHANNEL_CH2
1825 * @arg @ref LL_TIM_CHANNEL_CH3
1826 * @arg @ref LL_TIM_CHANNEL_CH4
1827 * @retval None
1828 */
LL_TIM_OC_DisableFast(TIM_TypeDef * TIMx,uint32_t Channel)1829 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
1830 {
1831 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1832 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1833 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
1834
1835 }
1836
1837 /**
1838 * @brief Indicates whether fast mode is enabled for the output channel.
1839 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
1840 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
1841 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
1842 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
1843 * @param TIMx Timer instance
1844 * @param Channel This parameter can be one of the following values:
1845 * @arg @ref LL_TIM_CHANNEL_CH1
1846 * @arg @ref LL_TIM_CHANNEL_CH2
1847 * @arg @ref LL_TIM_CHANNEL_CH3
1848 * @arg @ref LL_TIM_CHANNEL_CH4
1849 * @retval State of bit (1 or 0).
1850 */
LL_TIM_OC_IsEnabledFast(TIM_TypeDef * TIMx,uint32_t Channel)1851 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
1852 {
1853 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1854 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1855 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
1856 return (READ_BIT(*pReg, bitfield) == bitfield);
1857 }
1858
1859 /**
1860 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
1861 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
1862 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
1863 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
1864 * CCMR2 OC4PE LL_TIM_OC_EnablePreload
1865 * @param TIMx Timer instance
1866 * @param Channel This parameter can be one of the following values:
1867 * @arg @ref LL_TIM_CHANNEL_CH1
1868 * @arg @ref LL_TIM_CHANNEL_CH2
1869 * @arg @ref LL_TIM_CHANNEL_CH3
1870 * @arg @ref LL_TIM_CHANNEL_CH4
1871 * @retval None
1872 */
LL_TIM_OC_EnablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1873 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1874 {
1875 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1876 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1877 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1878 }
1879
1880 /**
1881 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
1882 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
1883 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
1884 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
1885 * CCMR2 OC4PE LL_TIM_OC_DisablePreload
1886 * @param TIMx Timer instance
1887 * @param Channel This parameter can be one of the following values:
1888 * @arg @ref LL_TIM_CHANNEL_CH1
1889 * @arg @ref LL_TIM_CHANNEL_CH2
1890 * @arg @ref LL_TIM_CHANNEL_CH3
1891 * @arg @ref LL_TIM_CHANNEL_CH4
1892 * @retval None
1893 */
LL_TIM_OC_DisablePreload(TIM_TypeDef * TIMx,uint32_t Channel)1894 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
1895 {
1896 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1897 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1898 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
1899 }
1900
1901 /**
1902 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
1903 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
1904 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
1905 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
1906 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
1907 * @param TIMx Timer instance
1908 * @param Channel This parameter can be one of the following values:
1909 * @arg @ref LL_TIM_CHANNEL_CH1
1910 * @arg @ref LL_TIM_CHANNEL_CH2
1911 * @arg @ref LL_TIM_CHANNEL_CH3
1912 * @arg @ref LL_TIM_CHANNEL_CH4
1913 * @retval State of bit (1 or 0).
1914 */
LL_TIM_OC_IsEnabledPreload(TIM_TypeDef * TIMx,uint32_t Channel)1915 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
1916 {
1917 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1918 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1919 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
1920 return (READ_BIT(*pReg, bitfield) == bitfield);
1921 }
1922
1923 /**
1924 * @brief Enable clearing the output channel on an external event.
1925 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1926 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1927 * or not a timer instance can clear the OCxREF signal on an external event.
1928 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
1929 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
1930 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
1931 * CCMR2 OC4CE LL_TIM_OC_EnableClear
1932 * @param TIMx Timer instance
1933 * @param Channel This parameter can be one of the following values:
1934 * @arg @ref LL_TIM_CHANNEL_CH1
1935 * @arg @ref LL_TIM_CHANNEL_CH2
1936 * @arg @ref LL_TIM_CHANNEL_CH3
1937 * @arg @ref LL_TIM_CHANNEL_CH4
1938 * @retval None
1939 */
LL_TIM_OC_EnableClear(TIM_TypeDef * TIMx,uint32_t Channel)1940 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1941 {
1942 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1943 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1944 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1945 }
1946
1947 /**
1948 * @brief Disable clearing the output channel on an external event.
1949 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1950 * or not a timer instance can clear the OCxREF signal on an external event.
1951 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
1952 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
1953 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
1954 * CCMR2 OC4CE LL_TIM_OC_DisableClear
1955 * @param TIMx Timer instance
1956 * @param Channel This parameter can be one of the following values:
1957 * @arg @ref LL_TIM_CHANNEL_CH1
1958 * @arg @ref LL_TIM_CHANNEL_CH2
1959 * @arg @ref LL_TIM_CHANNEL_CH3
1960 * @arg @ref LL_TIM_CHANNEL_CH4
1961 * @retval None
1962 */
LL_TIM_OC_DisableClear(TIM_TypeDef * TIMx,uint32_t Channel)1963 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
1964 {
1965 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1966 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1967 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
1968 }
1969
1970 /**
1971 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
1972 * @note This function enables clearing the output channel on an external event.
1973 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
1974 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
1975 * or not a timer instance can clear the OCxREF signal on an external event.
1976 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
1977 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
1978 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
1979 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
1980 * @param TIMx Timer instance
1981 * @param Channel This parameter can be one of the following values:
1982 * @arg @ref LL_TIM_CHANNEL_CH1
1983 * @arg @ref LL_TIM_CHANNEL_CH2
1984 * @arg @ref LL_TIM_CHANNEL_CH3
1985 * @arg @ref LL_TIM_CHANNEL_CH4
1986 * @retval State of bit (1 or 0).
1987 */
LL_TIM_OC_IsEnabledClear(TIM_TypeDef * TIMx,uint32_t Channel)1988 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
1989 {
1990 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1991 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1992 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
1993 return (READ_BIT(*pReg, bitfield) == bitfield);
1994 }
1995
1996 /**
1997 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
1998 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1999 * dead-time insertion feature is supported by a timer instance.
2000 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2001 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2002 * @param TIMx Timer instance
2003 * @param DeadTime between Min_Data=0 and Max_Data=255
2004 * @retval None
2005 */
LL_TIM_OC_SetDeadTime(TIM_TypeDef * TIMx,uint32_t DeadTime)2006 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2007 {
2008 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2009 }
2010
2011 /**
2012 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2013 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2014 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2015 * whether or not a timer instance supports a 32 bits counter.
2016 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2017 * output channel 1 is supported by a timer instance.
2018 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2019 * @param TIMx Timer instance
2020 * @param CompareValue between Min_Data=0 and Max_Data=65535
2021 * @retval None
2022 */
LL_TIM_OC_SetCompareCH1(TIM_TypeDef * TIMx,uint32_t CompareValue)2023 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2024 {
2025 WRITE_REG(TIMx->CCR1, CompareValue);
2026 }
2027
2028 /**
2029 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2030 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2031 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2032 * whether or not a timer instance supports a 32 bits counter.
2033 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2034 * output channel 2 is supported by a timer instance.
2035 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2036 * @param TIMx Timer instance
2037 * @param CompareValue between Min_Data=0 and Max_Data=65535
2038 * @retval None
2039 */
LL_TIM_OC_SetCompareCH2(TIM_TypeDef * TIMx,uint32_t CompareValue)2040 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2041 {
2042 WRITE_REG(TIMx->CCR2, CompareValue);
2043 }
2044
2045 /**
2046 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2047 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2048 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2049 * whether or not a timer instance supports a 32 bits counter.
2050 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2051 * output channel is supported by a timer instance.
2052 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2053 * @param TIMx Timer instance
2054 * @param CompareValue between Min_Data=0 and Max_Data=65535
2055 * @retval None
2056 */
LL_TIM_OC_SetCompareCH3(TIM_TypeDef * TIMx,uint32_t CompareValue)2057 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2058 {
2059 WRITE_REG(TIMx->CCR3, CompareValue);
2060 }
2061
2062 /**
2063 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2064 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2065 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2066 * whether or not a timer instance supports a 32 bits counter.
2067 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2068 * output channel 4 is supported by a timer instance.
2069 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2070 * @param TIMx Timer instance
2071 * @param CompareValue between Min_Data=0 and Max_Data=65535
2072 * @retval None
2073 */
LL_TIM_OC_SetCompareCH4(TIM_TypeDef * TIMx,uint32_t CompareValue)2074 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2075 {
2076 WRITE_REG(TIMx->CCR4, CompareValue);
2077 }
2078
2079 /**
2080 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2081 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2082 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2083 * whether or not a timer instance supports a 32 bits counter.
2084 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2085 * output channel 1 is supported by a timer instance.
2086 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2087 * @param TIMx Timer instance
2088 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2089 */
LL_TIM_OC_GetCompareCH1(TIM_TypeDef * TIMx)2090 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2091 {
2092 return (uint32_t)(READ_REG(TIMx->CCR1));
2093 }
2094
2095 /**
2096 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2097 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2098 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2099 * whether or not a timer instance supports a 32 bits counter.
2100 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2101 * output channel 2 is supported by a timer instance.
2102 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2103 * @param TIMx Timer instance
2104 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2105 */
LL_TIM_OC_GetCompareCH2(TIM_TypeDef * TIMx)2106 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2107 {
2108 return (uint32_t)(READ_REG(TIMx->CCR2));
2109 }
2110
2111 /**
2112 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2113 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2114 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2115 * whether or not a timer instance supports a 32 bits counter.
2116 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2117 * output channel 3 is supported by a timer instance.
2118 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2119 * @param TIMx Timer instance
2120 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2121 */
LL_TIM_OC_GetCompareCH3(TIM_TypeDef * TIMx)2122 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2123 {
2124 return (uint32_t)(READ_REG(TIMx->CCR3));
2125 }
2126
2127 /**
2128 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2129 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2130 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2131 * whether or not a timer instance supports a 32 bits counter.
2132 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2133 * output channel 4 is supported by a timer instance.
2134 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2135 * @param TIMx Timer instance
2136 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2137 */
LL_TIM_OC_GetCompareCH4(TIM_TypeDef * TIMx)2138 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2139 {
2140 return (uint32_t)(READ_REG(TIMx->CCR4));
2141 }
2142
2143 /**
2144 * @}
2145 */
2146
2147 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2148 * @{
2149 */
2150 /**
2151 * @brief Configure input channel.
2152 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2153 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2154 * CCMR1 IC1F LL_TIM_IC_Config\n
2155 * CCMR1 CC2S LL_TIM_IC_Config\n
2156 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2157 * CCMR1 IC2F LL_TIM_IC_Config\n
2158 * CCMR2 CC3S LL_TIM_IC_Config\n
2159 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2160 * CCMR2 IC3F LL_TIM_IC_Config\n
2161 * CCMR2 CC4S LL_TIM_IC_Config\n
2162 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2163 * CCMR2 IC4F LL_TIM_IC_Config\n
2164 * CCER CC1P LL_TIM_IC_Config\n
2165 * CCER CC1NP LL_TIM_IC_Config\n
2166 * CCER CC2P LL_TIM_IC_Config\n
2167 * CCER CC2NP LL_TIM_IC_Config\n
2168 * CCER CC3P LL_TIM_IC_Config\n
2169 * CCER CC3NP LL_TIM_IC_Config\n
2170 * CCER CC4P LL_TIM_IC_Config\n
2171 * CCER CC4NP LL_TIM_IC_Config
2172 * @param TIMx Timer instance
2173 * @param Channel This parameter can be one of the following values:
2174 * @arg @ref LL_TIM_CHANNEL_CH1
2175 * @arg @ref LL_TIM_CHANNEL_CH2
2176 * @arg @ref LL_TIM_CHANNEL_CH3
2177 * @arg @ref LL_TIM_CHANNEL_CH4
2178 * @param Configuration This parameter must be a combination of all the following values:
2179 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2180 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2181 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2182 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2183 * @retval None
2184 */
LL_TIM_IC_Config(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t Configuration)2185 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2186 {
2187 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2188 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2189 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2190 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2191 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2192 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2193 }
2194
2195 /**
2196 * @brief Set the active input.
2197 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2198 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2199 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2200 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2201 * @param TIMx Timer instance
2202 * @param Channel This parameter can be one of the following values:
2203 * @arg @ref LL_TIM_CHANNEL_CH1
2204 * @arg @ref LL_TIM_CHANNEL_CH2
2205 * @arg @ref LL_TIM_CHANNEL_CH3
2206 * @arg @ref LL_TIM_CHANNEL_CH4
2207 * @param ICActiveInput This parameter can be one of the following values:
2208 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2209 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2210 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2211 * @retval None
2212 */
LL_TIM_IC_SetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICActiveInput)2213 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2214 {
2215 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2216 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2217 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2218 }
2219
2220 /**
2221 * @brief Get the current active input.
2222 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2223 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2224 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2225 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2226 * @param TIMx Timer instance
2227 * @param Channel This parameter can be one of the following values:
2228 * @arg @ref LL_TIM_CHANNEL_CH1
2229 * @arg @ref LL_TIM_CHANNEL_CH2
2230 * @arg @ref LL_TIM_CHANNEL_CH3
2231 * @arg @ref LL_TIM_CHANNEL_CH4
2232 * @retval Returned value can be one of the following values:
2233 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2234 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2235 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2236 */
LL_TIM_IC_GetActiveInput(TIM_TypeDef * TIMx,uint32_t Channel)2237 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2238 {
2239 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2240 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2241 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2242 }
2243
2244 /**
2245 * @brief Set the prescaler of input channel.
2246 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2247 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2248 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2249 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2250 * @param TIMx Timer instance
2251 * @param Channel This parameter can be one of the following values:
2252 * @arg @ref LL_TIM_CHANNEL_CH1
2253 * @arg @ref LL_TIM_CHANNEL_CH2
2254 * @arg @ref LL_TIM_CHANNEL_CH3
2255 * @arg @ref LL_TIM_CHANNEL_CH4
2256 * @param ICPrescaler This parameter can be one of the following values:
2257 * @arg @ref LL_TIM_ICPSC_DIV1
2258 * @arg @ref LL_TIM_ICPSC_DIV2
2259 * @arg @ref LL_TIM_ICPSC_DIV4
2260 * @arg @ref LL_TIM_ICPSC_DIV8
2261 * @retval None
2262 */
LL_TIM_IC_SetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPrescaler)2263 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2264 {
2265 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2266 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2267 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2268 }
2269
2270 /**
2271 * @brief Get the current prescaler value acting on an input channel.
2272 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2273 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2274 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2275 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2276 * @param TIMx Timer instance
2277 * @param Channel This parameter can be one of the following values:
2278 * @arg @ref LL_TIM_CHANNEL_CH1
2279 * @arg @ref LL_TIM_CHANNEL_CH2
2280 * @arg @ref LL_TIM_CHANNEL_CH3
2281 * @arg @ref LL_TIM_CHANNEL_CH4
2282 * @retval Returned value can be one of the following values:
2283 * @arg @ref LL_TIM_ICPSC_DIV1
2284 * @arg @ref LL_TIM_ICPSC_DIV2
2285 * @arg @ref LL_TIM_ICPSC_DIV4
2286 * @arg @ref LL_TIM_ICPSC_DIV8
2287 */
LL_TIM_IC_GetPrescaler(TIM_TypeDef * TIMx,uint32_t Channel)2288 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2289 {
2290 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2291 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2292 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2293 }
2294
2295 /**
2296 * @brief Set the input filter duration.
2297 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2298 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2299 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2300 * CCMR2 IC4F LL_TIM_IC_SetFilter
2301 * @param TIMx Timer instance
2302 * @param Channel This parameter can be one of the following values:
2303 * @arg @ref LL_TIM_CHANNEL_CH1
2304 * @arg @ref LL_TIM_CHANNEL_CH2
2305 * @arg @ref LL_TIM_CHANNEL_CH3
2306 * @arg @ref LL_TIM_CHANNEL_CH4
2307 * @param ICFilter This parameter can be one of the following values:
2308 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2309 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2310 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2311 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2312 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2313 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2314 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2315 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2316 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2317 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2318 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2319 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2320 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2321 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2322 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2323 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2324 * @retval None
2325 */
LL_TIM_IC_SetFilter(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICFilter)2326 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2327 {
2328 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2329 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2330 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2331 }
2332
2333 /**
2334 * @brief Get the input filter duration.
2335 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2336 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2337 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2338 * CCMR2 IC4F LL_TIM_IC_GetFilter
2339 * @param TIMx Timer instance
2340 * @param Channel This parameter can be one of the following values:
2341 * @arg @ref LL_TIM_CHANNEL_CH1
2342 * @arg @ref LL_TIM_CHANNEL_CH2
2343 * @arg @ref LL_TIM_CHANNEL_CH3
2344 * @arg @ref LL_TIM_CHANNEL_CH4
2345 * @retval Returned value can be one of the following values:
2346 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2347 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2348 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2349 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2350 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2351 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2352 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2353 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2354 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2355 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2356 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2357 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2358 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2359 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2360 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2361 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2362 */
LL_TIM_IC_GetFilter(TIM_TypeDef * TIMx,uint32_t Channel)2363 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2364 {
2365 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2366 register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2367 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2368 }
2369
2370 /**
2371 * @brief Set the input channel polarity.
2372 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2373 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2374 * CCER CC2P LL_TIM_IC_SetPolarity\n
2375 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2376 * CCER CC3P LL_TIM_IC_SetPolarity\n
2377 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2378 * CCER CC4P LL_TIM_IC_SetPolarity\n
2379 * CCER CC4NP LL_TIM_IC_SetPolarity
2380 * @param TIMx Timer instance
2381 * @param Channel This parameter can be one of the following values:
2382 * @arg @ref LL_TIM_CHANNEL_CH1
2383 * @arg @ref LL_TIM_CHANNEL_CH2
2384 * @arg @ref LL_TIM_CHANNEL_CH3
2385 * @arg @ref LL_TIM_CHANNEL_CH4
2386 * @param ICPolarity This parameter can be one of the following values:
2387 * @arg @ref LL_TIM_IC_POLARITY_RISING
2388 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2389 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2390 * @retval None
2391 */
LL_TIM_IC_SetPolarity(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ICPolarity)2392 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2393 {
2394 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2395 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2396 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2397 }
2398
2399 /**
2400 * @brief Get the current input channel polarity.
2401 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2402 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2403 * CCER CC2P LL_TIM_IC_GetPolarity\n
2404 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2405 * CCER CC3P LL_TIM_IC_GetPolarity\n
2406 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2407 * CCER CC4P LL_TIM_IC_GetPolarity\n
2408 * CCER CC4NP LL_TIM_IC_GetPolarity
2409 * @param TIMx Timer instance
2410 * @param Channel This parameter can be one of the following values:
2411 * @arg @ref LL_TIM_CHANNEL_CH1
2412 * @arg @ref LL_TIM_CHANNEL_CH2
2413 * @arg @ref LL_TIM_CHANNEL_CH3
2414 * @arg @ref LL_TIM_CHANNEL_CH4
2415 * @retval Returned value can be one of the following values:
2416 * @arg @ref LL_TIM_IC_POLARITY_RISING
2417 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2418 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2419 */
LL_TIM_IC_GetPolarity(TIM_TypeDef * TIMx,uint32_t Channel)2420 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2421 {
2422 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2423 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2424 SHIFT_TAB_CCxP[iChannel]);
2425 }
2426
2427 /**
2428 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2429 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2430 * a timer instance provides an XOR input.
2431 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2432 * @param TIMx Timer instance
2433 * @retval None
2434 */
LL_TIM_IC_EnableXORCombination(TIM_TypeDef * TIMx)2435 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2436 {
2437 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2438 }
2439
2440 /**
2441 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2442 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2443 * a timer instance provides an XOR input.
2444 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2445 * @param TIMx Timer instance
2446 * @retval None
2447 */
LL_TIM_IC_DisableXORCombination(TIM_TypeDef * TIMx)2448 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2449 {
2450 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2451 }
2452
2453 /**
2454 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2455 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2456 * a timer instance provides an XOR input.
2457 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2458 * @param TIMx Timer instance
2459 * @retval State of bit (1 or 0).
2460 */
LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef * TIMx)2461 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2462 {
2463 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
2464 }
2465
2466 /**
2467 * @brief Get captured value for input channel 1.
2468 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2469 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2470 * whether or not a timer instance supports a 32 bits counter.
2471 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2472 * input channel 1 is supported by a timer instance.
2473 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2474 * @param TIMx Timer instance
2475 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2476 */
LL_TIM_IC_GetCaptureCH1(TIM_TypeDef * TIMx)2477 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
2478 {
2479 return (uint32_t)(READ_REG(TIMx->CCR1));
2480 }
2481
2482 /**
2483 * @brief Get captured value for input channel 2.
2484 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2485 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2486 * whether or not a timer instance supports a 32 bits counter.
2487 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2488 * input channel 2 is supported by a timer instance.
2489 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2490 * @param TIMx Timer instance
2491 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2492 */
LL_TIM_IC_GetCaptureCH2(TIM_TypeDef * TIMx)2493 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
2494 {
2495 return (uint32_t)(READ_REG(TIMx->CCR2));
2496 }
2497
2498 /**
2499 * @brief Get captured value for input channel 3.
2500 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2501 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2502 * whether or not a timer instance supports a 32 bits counter.
2503 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2504 * input channel 3 is supported by a timer instance.
2505 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2506 * @param TIMx Timer instance
2507 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2508 */
LL_TIM_IC_GetCaptureCH3(TIM_TypeDef * TIMx)2509 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
2510 {
2511 return (uint32_t)(READ_REG(TIMx->CCR3));
2512 }
2513
2514 /**
2515 * @brief Get captured value for input channel 4.
2516 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2517 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2518 * whether or not a timer instance supports a 32 bits counter.
2519 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2520 * input channel 4 is supported by a timer instance.
2521 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2522 * @param TIMx Timer instance
2523 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2524 */
LL_TIM_IC_GetCaptureCH4(TIM_TypeDef * TIMx)2525 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
2526 {
2527 return (uint32_t)(READ_REG(TIMx->CCR4));
2528 }
2529
2530 /**
2531 * @}
2532 */
2533
2534 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2535 * @{
2536 */
2537 /**
2538 * @brief Enable external clock mode 2.
2539 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2540 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2541 * whether or not a timer instance supports external clock mode2.
2542 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2543 * @param TIMx Timer instance
2544 * @retval None
2545 */
LL_TIM_EnableExternalClock(TIM_TypeDef * TIMx)2546 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2547 {
2548 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2549 }
2550
2551 /**
2552 * @brief Disable external clock mode 2.
2553 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2554 * whether or not a timer instance supports external clock mode2.
2555 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2556 * @param TIMx Timer instance
2557 * @retval None
2558 */
LL_TIM_DisableExternalClock(TIM_TypeDef * TIMx)2559 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2560 {
2561 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2562 }
2563
2564 /**
2565 * @brief Indicate whether external clock mode 2 is enabled.
2566 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2567 * whether or not a timer instance supports external clock mode2.
2568 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2569 * @param TIMx Timer instance
2570 * @retval State of bit (1 or 0).
2571 */
LL_TIM_IsEnabledExternalClock(TIM_TypeDef * TIMx)2572 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
2573 {
2574 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
2575 }
2576
2577 /**
2578 * @brief Set the clock source of the counter clock.
2579 * @note when selected clock source is external clock mode 1, the timer input
2580 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
2581 * function. This timer input must be configured by calling
2582 * the @ref LL_TIM_IC_Config() function.
2583 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
2584 * whether or not a timer instance supports external clock mode1.
2585 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2586 * whether or not a timer instance supports external clock mode2.
2587 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
2588 * SMCR ECE LL_TIM_SetClockSource
2589 * @param TIMx Timer instance
2590 * @param ClockSource This parameter can be one of the following values:
2591 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
2592 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
2593 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
2594 * @retval None
2595 */
LL_TIM_SetClockSource(TIM_TypeDef * TIMx,uint32_t ClockSource)2596 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
2597 {
2598 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
2599 }
2600
2601 /**
2602 * @brief Set the encoder interface mode.
2603 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
2604 * whether or not a timer instance supports the encoder mode.
2605 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
2606 * @param TIMx Timer instance
2607 * @param EncoderMode This parameter can be one of the following values:
2608 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
2609 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
2610 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
2611 * @retval None
2612 */
LL_TIM_SetEncoderMode(TIM_TypeDef * TIMx,uint32_t EncoderMode)2613 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
2614 {
2615 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
2616 }
2617
2618 /**
2619 * @}
2620 */
2621
2622 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
2623 * @{
2624 */
2625 /**
2626 * @brief Set the trigger output (TRGO) used for timer synchronization .
2627 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
2628 * whether or not a timer instance can operate as a master timer.
2629 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
2630 * @param TIMx Timer instance
2631 * @param TimerSynchronization This parameter can be one of the following values:
2632 * @arg @ref LL_TIM_TRGO_RESET
2633 * @arg @ref LL_TIM_TRGO_ENABLE
2634 * @arg @ref LL_TIM_TRGO_UPDATE
2635 * @arg @ref LL_TIM_TRGO_CC1IF
2636 * @arg @ref LL_TIM_TRGO_OC1REF
2637 * @arg @ref LL_TIM_TRGO_OC2REF
2638 * @arg @ref LL_TIM_TRGO_OC3REF
2639 * @arg @ref LL_TIM_TRGO_OC4REF
2640 * @retval None
2641 */
LL_TIM_SetTriggerOutput(TIM_TypeDef * TIMx,uint32_t TimerSynchronization)2642 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
2643 {
2644 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
2645 }
2646
2647 /**
2648 * @brief Set the synchronization mode of a slave timer.
2649 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2650 * a timer instance can operate as a slave timer.
2651 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
2652 * @param TIMx Timer instance
2653 * @param SlaveMode This parameter can be one of the following values:
2654 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
2655 * @arg @ref LL_TIM_SLAVEMODE_RESET
2656 * @arg @ref LL_TIM_SLAVEMODE_GATED
2657 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
2658 * @retval None
2659 */
LL_TIM_SetSlaveMode(TIM_TypeDef * TIMx,uint32_t SlaveMode)2660 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
2661 {
2662 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
2663 }
2664
2665 /**
2666 * @brief Set the selects the trigger input to be used to synchronize the counter.
2667 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2668 * a timer instance can operate as a slave timer.
2669 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
2670 * @param TIMx Timer instance
2671 * @param TriggerInput This parameter can be one of the following values:
2672 * @arg @ref LL_TIM_TS_ITR0
2673 * @arg @ref LL_TIM_TS_ITR1
2674 * @arg @ref LL_TIM_TS_ITR2
2675 * @arg @ref LL_TIM_TS_ITR3
2676 * @arg @ref LL_TIM_TS_TI1F_ED
2677 * @arg @ref LL_TIM_TS_TI1FP1
2678 * @arg @ref LL_TIM_TS_TI2FP2
2679 * @arg @ref LL_TIM_TS_ETRF
2680 * @retval None
2681 */
LL_TIM_SetTriggerInput(TIM_TypeDef * TIMx,uint32_t TriggerInput)2682 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
2683 {
2684 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
2685 }
2686
2687 /**
2688 * @brief Enable the Master/Slave mode.
2689 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2690 * a timer instance can operate as a slave timer.
2691 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
2692 * @param TIMx Timer instance
2693 * @retval None
2694 */
LL_TIM_EnableMasterSlaveMode(TIM_TypeDef * TIMx)2695 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
2696 {
2697 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2698 }
2699
2700 /**
2701 * @brief Disable the Master/Slave mode.
2702 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2703 * a timer instance can operate as a slave timer.
2704 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
2705 * @param TIMx Timer instance
2706 * @retval None
2707 */
LL_TIM_DisableMasterSlaveMode(TIM_TypeDef * TIMx)2708 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
2709 {
2710 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
2711 }
2712
2713 /**
2714 * @brief Indicates whether the Master/Slave mode is enabled.
2715 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
2716 * a timer instance can operate as a slave timer.
2717 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
2718 * @param TIMx Timer instance
2719 * @retval State of bit (1 or 0).
2720 */
LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef * TIMx)2721 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
2722 {
2723 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
2724 }
2725
2726 /**
2727 * @brief Configure the external trigger (ETR) input.
2728 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
2729 * a timer instance provides an external trigger input.
2730 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
2731 * SMCR ETPS LL_TIM_ConfigETR\n
2732 * SMCR ETF LL_TIM_ConfigETR
2733 * @param TIMx Timer instance
2734 * @param ETRPolarity This parameter can be one of the following values:
2735 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
2736 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
2737 * @param ETRPrescaler This parameter can be one of the following values:
2738 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
2739 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
2740 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
2741 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
2742 * @param ETRFilter This parameter can be one of the following values:
2743 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
2744 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
2745 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
2746 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
2747 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
2748 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
2749 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
2750 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
2751 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
2752 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
2753 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
2754 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
2755 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
2756 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
2757 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
2758 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
2759 * @retval None
2760 */
LL_TIM_ConfigETR(TIM_TypeDef * TIMx,uint32_t ETRPolarity,uint32_t ETRPrescaler,uint32_t ETRFilter)2761 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
2762 uint32_t ETRFilter)
2763 {
2764 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
2765 }
2766
2767 /**
2768 * @}
2769 */
2770
2771 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
2772 * @{
2773 */
2774 /**
2775 * @brief Enable the break function.
2776 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2777 * a timer instance provides a break input.
2778 * @rmtoll BDTR BKE LL_TIM_EnableBRK
2779 * @param TIMx Timer instance
2780 * @retval None
2781 */
LL_TIM_EnableBRK(TIM_TypeDef * TIMx)2782 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
2783 {
2784 __IO uint32_t tmpreg;
2785
2786 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2787
2788 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2789 tmpreg = READ_REG(TIMx->BDTR);
2790 (void)(tmpreg);
2791 }
2792
2793 /**
2794 * @brief Disable the break function.
2795 * @rmtoll BDTR BKE LL_TIM_DisableBRK
2796 * @param TIMx Timer instance
2797 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2798 * a timer instance provides a break input.
2799 * @retval None
2800 */
LL_TIM_DisableBRK(TIM_TypeDef * TIMx)2801 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
2802 {
2803 __IO uint32_t tmpreg;
2804
2805 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
2806
2807 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2808 tmpreg = READ_REG(TIMx->BDTR);
2809 (void)(tmpreg);
2810 }
2811
2812 /**
2813 * @brief Configure the break input.
2814 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2815 * a timer instance provides a break input.
2816 * @rmtoll BDTR BKP LL_TIM_ConfigBRK
2817 * @param TIMx Timer instance
2818 * @param BreakPolarity This parameter can be one of the following values:
2819 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
2820 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
2821 * @retval None
2822 */
LL_TIM_ConfigBRK(TIM_TypeDef * TIMx,uint32_t BreakPolarity)2823 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity)
2824 {
2825 __IO uint32_t tmpreg;
2826
2827 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity);
2828
2829 /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */
2830 tmpreg = READ_REG(TIMx->BDTR);
2831 (void)(tmpreg);
2832 }
2833
2834 /**
2835 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
2836 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2837 * a timer instance provides a break input.
2838 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
2839 * BDTR OSSR LL_TIM_SetOffStates
2840 * @param TIMx Timer instance
2841 * @param OffStateIdle This parameter can be one of the following values:
2842 * @arg @ref LL_TIM_OSSI_DISABLE
2843 * @arg @ref LL_TIM_OSSI_ENABLE
2844 * @param OffStateRun This parameter can be one of the following values:
2845 * @arg @ref LL_TIM_OSSR_DISABLE
2846 * @arg @ref LL_TIM_OSSR_ENABLE
2847 * @retval None
2848 */
LL_TIM_SetOffStates(TIM_TypeDef * TIMx,uint32_t OffStateIdle,uint32_t OffStateRun)2849 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
2850 {
2851 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
2852 }
2853
2854 /**
2855 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
2856 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2857 * a timer instance provides a break input.
2858 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
2859 * @param TIMx Timer instance
2860 * @retval None
2861 */
LL_TIM_EnableAutomaticOutput(TIM_TypeDef * TIMx)2862 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
2863 {
2864 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2865 }
2866
2867 /**
2868 * @brief Disable automatic output (MOE can be set only by software).
2869 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2870 * a timer instance provides a break input.
2871 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
2872 * @param TIMx Timer instance
2873 * @retval None
2874 */
LL_TIM_DisableAutomaticOutput(TIM_TypeDef * TIMx)2875 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
2876 {
2877 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
2878 }
2879
2880 /**
2881 * @brief Indicate whether automatic output is enabled.
2882 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2883 * a timer instance provides a break input.
2884 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
2885 * @param TIMx Timer instance
2886 * @retval State of bit (1 or 0).
2887 */
LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef * TIMx)2888 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
2889 {
2890 return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
2891 }
2892
2893 /**
2894 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
2895 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2896 * software and is reset in case of break or break2 event
2897 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2898 * a timer instance provides a break input.
2899 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
2900 * @param TIMx Timer instance
2901 * @retval None
2902 */
LL_TIM_EnableAllOutputs(TIM_TypeDef * TIMx)2903 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
2904 {
2905 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2906 }
2907
2908 /**
2909 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
2910 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
2911 * software and is reset in case of break or break2 event.
2912 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2913 * a timer instance provides a break input.
2914 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
2915 * @param TIMx Timer instance
2916 * @retval None
2917 */
LL_TIM_DisableAllOutputs(TIM_TypeDef * TIMx)2918 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
2919 {
2920 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
2921 }
2922
2923 /**
2924 * @brief Indicates whether outputs are enabled.
2925 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2926 * a timer instance provides a break input.
2927 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
2928 * @param TIMx Timer instance
2929 * @retval State of bit (1 or 0).
2930 */
LL_TIM_IsEnabledAllOutputs(TIM_TypeDef * TIMx)2931 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
2932 {
2933 return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
2934 }
2935
2936 /**
2937 * @}
2938 */
2939
2940 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
2941 * @{
2942 */
2943 /**
2944 * @brief Configures the timer DMA burst feature.
2945 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
2946 * not a timer instance supports the DMA burst mode.
2947 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
2948 * DCR DBA LL_TIM_ConfigDMABurst
2949 * @param TIMx Timer instance
2950 * @param DMABurstBaseAddress This parameter can be one of the following values:
2951 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
2952 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
2953 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
2954 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
2955 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
2956 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
2957 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
2958 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
2959 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
2960 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
2961 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
2962 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
2963 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
2964 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
2965 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
2966 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
2967 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
2968 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
2969 * @param DMABurstLength This parameter can be one of the following values:
2970 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
2971 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
2972 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
2973 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
2974 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
2975 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
2976 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
2977 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
2978 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
2979 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
2980 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
2981 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
2982 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
2983 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
2984 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
2985 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
2986 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
2987 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
2988 * @retval None
2989 */
LL_TIM_ConfigDMABurst(TIM_TypeDef * TIMx,uint32_t DMABurstBaseAddress,uint32_t DMABurstLength)2990 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
2991 {
2992 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
2993 }
2994
2995 /**
2996 * @}
2997 */
2998
2999 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3000 * @{
3001 */
3002 /**
3003 * @brief Remap TIM inputs (input channel, internal/external triggers).
3004 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3005 * a some timer inputs can be remapped.
3006 * @rmtoll TIM14_OR TI1_RMP LL_TIM_SetRemap
3007 * @param TIMx Timer instance
3008 * @param Remap This parameter can be one of the following values:
3009 * @arg @ref LL_TIM_TIM14_TI1_RMP_GPIO
3010 * @arg @ref LL_TIM_TIM14_TI1_RMP_RTC_CLK
3011 * @arg @ref LL_TIM_TIM14_TI1_RMP_HSE
3012 * @arg @ref LL_TIM_TIM14_TI1_RMP_MCO
3013 *
3014 * @retval None
3015 */
LL_TIM_SetRemap(TIM_TypeDef * TIMx,uint32_t Remap)3016 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3017 {
3018 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3019 }
3020
3021 /**
3022 * @}
3023 */
3024
3025 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
3026 * @{
3027 */
3028 /**
3029 * @brief Set the OCREF clear input source
3030 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
3031 * @note This function can only be used in Output compare and PWM modes.
3032 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
3033 * @param TIMx Timer instance
3034 * @param OCRefClearInputSource This parameter can be one of the following values:
3035 * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR
3036 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR
3037 * @retval None
3038 */
LL_TIM_SetOCRefClearInputSource(TIM_TypeDef * TIMx,uint32_t OCRefClearInputSource)3039 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
3040 {
3041 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource);
3042 }
3043 /**
3044 * @}
3045 */
3046
3047 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3048 * @{
3049 */
3050 /**
3051 * @brief Clear the update interrupt flag (UIF).
3052 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3053 * @param TIMx Timer instance
3054 * @retval None
3055 */
LL_TIM_ClearFlag_UPDATE(TIM_TypeDef * TIMx)3056 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3057 {
3058 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3059 }
3060
3061 /**
3062 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3063 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3064 * @param TIMx Timer instance
3065 * @retval State of bit (1 or 0).
3066 */
LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef * TIMx)3067 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3068 {
3069 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
3070 }
3071
3072 /**
3073 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3074 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3075 * @param TIMx Timer instance
3076 * @retval None
3077 */
LL_TIM_ClearFlag_CC1(TIM_TypeDef * TIMx)3078 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3079 {
3080 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3081 }
3082
3083 /**
3084 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3085 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3086 * @param TIMx Timer instance
3087 * @retval State of bit (1 or 0).
3088 */
LL_TIM_IsActiveFlag_CC1(TIM_TypeDef * TIMx)3089 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3090 {
3091 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
3092 }
3093
3094 /**
3095 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3096 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3097 * @param TIMx Timer instance
3098 * @retval None
3099 */
LL_TIM_ClearFlag_CC2(TIM_TypeDef * TIMx)3100 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3101 {
3102 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3103 }
3104
3105 /**
3106 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3107 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3108 * @param TIMx Timer instance
3109 * @retval State of bit (1 or 0).
3110 */
LL_TIM_IsActiveFlag_CC2(TIM_TypeDef * TIMx)3111 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3112 {
3113 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
3114 }
3115
3116 /**
3117 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3118 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3119 * @param TIMx Timer instance
3120 * @retval None
3121 */
LL_TIM_ClearFlag_CC3(TIM_TypeDef * TIMx)3122 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3123 {
3124 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3125 }
3126
3127 /**
3128 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3129 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3130 * @param TIMx Timer instance
3131 * @retval State of bit (1 or 0).
3132 */
LL_TIM_IsActiveFlag_CC3(TIM_TypeDef * TIMx)3133 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
3134 {
3135 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
3136 }
3137
3138 /**
3139 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3140 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3141 * @param TIMx Timer instance
3142 * @retval None
3143 */
LL_TIM_ClearFlag_CC4(TIM_TypeDef * TIMx)3144 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3145 {
3146 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3147 }
3148
3149 /**
3150 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3151 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3152 * @param TIMx Timer instance
3153 * @retval State of bit (1 or 0).
3154 */
LL_TIM_IsActiveFlag_CC4(TIM_TypeDef * TIMx)3155 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
3156 {
3157 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
3158 }
3159
3160 /**
3161 * @brief Clear the commutation interrupt flag (COMIF).
3162 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3163 * @param TIMx Timer instance
3164 * @retval None
3165 */
LL_TIM_ClearFlag_COM(TIM_TypeDef * TIMx)3166 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3167 {
3168 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3169 }
3170
3171 /**
3172 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3173 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3174 * @param TIMx Timer instance
3175 * @retval State of bit (1 or 0).
3176 */
LL_TIM_IsActiveFlag_COM(TIM_TypeDef * TIMx)3177 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
3178 {
3179 return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
3180 }
3181
3182 /**
3183 * @brief Clear the trigger interrupt flag (TIF).
3184 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3185 * @param TIMx Timer instance
3186 * @retval None
3187 */
LL_TIM_ClearFlag_TRIG(TIM_TypeDef * TIMx)3188 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3189 {
3190 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3191 }
3192
3193 /**
3194 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3195 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3196 * @param TIMx Timer instance
3197 * @retval State of bit (1 or 0).
3198 */
LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef * TIMx)3199 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
3200 {
3201 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
3202 }
3203
3204 /**
3205 * @brief Clear the break interrupt flag (BIF).
3206 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3207 * @param TIMx Timer instance
3208 * @retval None
3209 */
LL_TIM_ClearFlag_BRK(TIM_TypeDef * TIMx)3210 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3211 {
3212 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3213 }
3214
3215 /**
3216 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3217 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3218 * @param TIMx Timer instance
3219 * @retval State of bit (1 or 0).
3220 */
LL_TIM_IsActiveFlag_BRK(TIM_TypeDef * TIMx)3221 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
3222 {
3223 return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
3224 }
3225
3226 /**
3227 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3228 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3229 * @param TIMx Timer instance
3230 * @retval None
3231 */
LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef * TIMx)3232 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3233 {
3234 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3235 }
3236
3237 /**
3238 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
3239 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3240 * @param TIMx Timer instance
3241 * @retval State of bit (1 or 0).
3242 */
LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef * TIMx)3243 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
3244 {
3245 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
3246 }
3247
3248 /**
3249 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3250 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3251 * @param TIMx Timer instance
3252 * @retval None
3253 */
LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef * TIMx)3254 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3255 {
3256 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3257 }
3258
3259 /**
3260 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
3261 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3262 * @param TIMx Timer instance
3263 * @retval State of bit (1 or 0).
3264 */
LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef * TIMx)3265 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
3266 {
3267 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
3268 }
3269
3270 /**
3271 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3272 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3273 * @param TIMx Timer instance
3274 * @retval None
3275 */
LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef * TIMx)3276 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3277 {
3278 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3279 }
3280
3281 /**
3282 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
3283 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3284 * @param TIMx Timer instance
3285 * @retval State of bit (1 or 0).
3286 */
LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef * TIMx)3287 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
3288 {
3289 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
3290 }
3291
3292 /**
3293 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3294 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3295 * @param TIMx Timer instance
3296 * @retval None
3297 */
LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef * TIMx)3298 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3299 {
3300 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3301 }
3302
3303 /**
3304 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
3305 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3306 * @param TIMx Timer instance
3307 * @retval State of bit (1 or 0).
3308 */
LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef * TIMx)3309 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
3310 {
3311 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
3312 }
3313
3314 /**
3315 * @}
3316 */
3317
3318 /** @defgroup TIM_LL_EF_IT_Management IT-Management
3319 * @{
3320 */
3321 /**
3322 * @brief Enable update interrupt (UIE).
3323 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
3324 * @param TIMx Timer instance
3325 * @retval None
3326 */
LL_TIM_EnableIT_UPDATE(TIM_TypeDef * TIMx)3327 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
3328 {
3329 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
3330 }
3331
3332 /**
3333 * @brief Disable update interrupt (UIE).
3334 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
3335 * @param TIMx Timer instance
3336 * @retval None
3337 */
LL_TIM_DisableIT_UPDATE(TIM_TypeDef * TIMx)3338 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
3339 {
3340 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
3341 }
3342
3343 /**
3344 * @brief Indicates whether the update interrupt (UIE) is enabled.
3345 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
3346 * @param TIMx Timer instance
3347 * @retval State of bit (1 or 0).
3348 */
LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef * TIMx)3349 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
3350 {
3351 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
3352 }
3353
3354 /**
3355 * @brief Enable capture/compare 1 interrupt (CC1IE).
3356 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
3357 * @param TIMx Timer instance
3358 * @retval None
3359 */
LL_TIM_EnableIT_CC1(TIM_TypeDef * TIMx)3360 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
3361 {
3362 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3363 }
3364
3365 /**
3366 * @brief Disable capture/compare 1 interrupt (CC1IE).
3367 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
3368 * @param TIMx Timer instance
3369 * @retval None
3370 */
LL_TIM_DisableIT_CC1(TIM_TypeDef * TIMx)3371 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
3372 {
3373 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
3374 }
3375
3376 /**
3377 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
3378 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
3379 * @param TIMx Timer instance
3380 * @retval State of bit (1 or 0).
3381 */
LL_TIM_IsEnabledIT_CC1(TIM_TypeDef * TIMx)3382 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
3383 {
3384 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
3385 }
3386
3387 /**
3388 * @brief Enable capture/compare 2 interrupt (CC2IE).
3389 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
3390 * @param TIMx Timer instance
3391 * @retval None
3392 */
LL_TIM_EnableIT_CC2(TIM_TypeDef * TIMx)3393 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
3394 {
3395 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3396 }
3397
3398 /**
3399 * @brief Disable capture/compare 2 interrupt (CC2IE).
3400 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
3401 * @param TIMx Timer instance
3402 * @retval None
3403 */
LL_TIM_DisableIT_CC2(TIM_TypeDef * TIMx)3404 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
3405 {
3406 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
3407 }
3408
3409 /**
3410 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
3411 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
3412 * @param TIMx Timer instance
3413 * @retval State of bit (1 or 0).
3414 */
LL_TIM_IsEnabledIT_CC2(TIM_TypeDef * TIMx)3415 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
3416 {
3417 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
3418 }
3419
3420 /**
3421 * @brief Enable capture/compare 3 interrupt (CC3IE).
3422 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
3423 * @param TIMx Timer instance
3424 * @retval None
3425 */
LL_TIM_EnableIT_CC3(TIM_TypeDef * TIMx)3426 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
3427 {
3428 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3429 }
3430
3431 /**
3432 * @brief Disable capture/compare 3 interrupt (CC3IE).
3433 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
3434 * @param TIMx Timer instance
3435 * @retval None
3436 */
LL_TIM_DisableIT_CC3(TIM_TypeDef * TIMx)3437 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
3438 {
3439 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
3440 }
3441
3442 /**
3443 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
3444 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
3445 * @param TIMx Timer instance
3446 * @retval State of bit (1 or 0).
3447 */
LL_TIM_IsEnabledIT_CC3(TIM_TypeDef * TIMx)3448 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
3449 {
3450 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
3451 }
3452
3453 /**
3454 * @brief Enable capture/compare 4 interrupt (CC4IE).
3455 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
3456 * @param TIMx Timer instance
3457 * @retval None
3458 */
LL_TIM_EnableIT_CC4(TIM_TypeDef * TIMx)3459 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
3460 {
3461 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3462 }
3463
3464 /**
3465 * @brief Disable capture/compare 4 interrupt (CC4IE).
3466 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
3467 * @param TIMx Timer instance
3468 * @retval None
3469 */
LL_TIM_DisableIT_CC4(TIM_TypeDef * TIMx)3470 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
3471 {
3472 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
3473 }
3474
3475 /**
3476 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
3477 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
3478 * @param TIMx Timer instance
3479 * @retval State of bit (1 or 0).
3480 */
LL_TIM_IsEnabledIT_CC4(TIM_TypeDef * TIMx)3481 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
3482 {
3483 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
3484 }
3485
3486 /**
3487 * @brief Enable commutation interrupt (COMIE).
3488 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
3489 * @param TIMx Timer instance
3490 * @retval None
3491 */
LL_TIM_EnableIT_COM(TIM_TypeDef * TIMx)3492 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
3493 {
3494 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
3495 }
3496
3497 /**
3498 * @brief Disable commutation interrupt (COMIE).
3499 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
3500 * @param TIMx Timer instance
3501 * @retval None
3502 */
LL_TIM_DisableIT_COM(TIM_TypeDef * TIMx)3503 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
3504 {
3505 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
3506 }
3507
3508 /**
3509 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
3510 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
3511 * @param TIMx Timer instance
3512 * @retval State of bit (1 or 0).
3513 */
LL_TIM_IsEnabledIT_COM(TIM_TypeDef * TIMx)3514 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
3515 {
3516 return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
3517 }
3518
3519 /**
3520 * @brief Enable trigger interrupt (TIE).
3521 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
3522 * @param TIMx Timer instance
3523 * @retval None
3524 */
LL_TIM_EnableIT_TRIG(TIM_TypeDef * TIMx)3525 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
3526 {
3527 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
3528 }
3529
3530 /**
3531 * @brief Disable trigger interrupt (TIE).
3532 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
3533 * @param TIMx Timer instance
3534 * @retval None
3535 */
LL_TIM_DisableIT_TRIG(TIM_TypeDef * TIMx)3536 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
3537 {
3538 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
3539 }
3540
3541 /**
3542 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
3543 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
3544 * @param TIMx Timer instance
3545 * @retval State of bit (1 or 0).
3546 */
LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef * TIMx)3547 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
3548 {
3549 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
3550 }
3551
3552 /**
3553 * @brief Enable break interrupt (BIE).
3554 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
3555 * @param TIMx Timer instance
3556 * @retval None
3557 */
LL_TIM_EnableIT_BRK(TIM_TypeDef * TIMx)3558 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
3559 {
3560 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
3561 }
3562
3563 /**
3564 * @brief Disable break interrupt (BIE).
3565 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
3566 * @param TIMx Timer instance
3567 * @retval None
3568 */
LL_TIM_DisableIT_BRK(TIM_TypeDef * TIMx)3569 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
3570 {
3571 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
3572 }
3573
3574 /**
3575 * @brief Indicates whether the break interrupt (BIE) is enabled.
3576 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
3577 * @param TIMx Timer instance
3578 * @retval State of bit (1 or 0).
3579 */
LL_TIM_IsEnabledIT_BRK(TIM_TypeDef * TIMx)3580 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
3581 {
3582 return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
3583 }
3584
3585 /**
3586 * @}
3587 */
3588
3589 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
3590 * @{
3591 */
3592 /**
3593 * @brief Enable update DMA request (UDE).
3594 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
3595 * @param TIMx Timer instance
3596 * @retval None
3597 */
LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef * TIMx)3598 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3599 {
3600 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
3601 }
3602
3603 /**
3604 * @brief Disable update DMA request (UDE).
3605 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
3606 * @param TIMx Timer instance
3607 * @retval None
3608 */
LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef * TIMx)3609 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
3610 {
3611 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
3612 }
3613
3614 /**
3615 * @brief Indicates whether the update DMA request (UDE) is enabled.
3616 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
3617 * @param TIMx Timer instance
3618 * @retval State of bit (1 or 0).
3619 */
LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef * TIMx)3620 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
3621 {
3622 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
3623 }
3624
3625 /**
3626 * @brief Enable capture/compare 1 DMA request (CC1DE).
3627 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
3628 * @param TIMx Timer instance
3629 * @retval None
3630 */
LL_TIM_EnableDMAReq_CC1(TIM_TypeDef * TIMx)3631 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
3632 {
3633 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3634 }
3635
3636 /**
3637 * @brief Disable capture/compare 1 DMA request (CC1DE).
3638 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
3639 * @param TIMx Timer instance
3640 * @retval None
3641 */
LL_TIM_DisableDMAReq_CC1(TIM_TypeDef * TIMx)3642 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
3643 {
3644 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
3645 }
3646
3647 /**
3648 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
3649 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
3650 * @param TIMx Timer instance
3651 * @retval State of bit (1 or 0).
3652 */
LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef * TIMx)3653 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
3654 {
3655 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
3656 }
3657
3658 /**
3659 * @brief Enable capture/compare 2 DMA request (CC2DE).
3660 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
3661 * @param TIMx Timer instance
3662 * @retval None
3663 */
LL_TIM_EnableDMAReq_CC2(TIM_TypeDef * TIMx)3664 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
3665 {
3666 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3667 }
3668
3669 /**
3670 * @brief Disable capture/compare 2 DMA request (CC2DE).
3671 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
3672 * @param TIMx Timer instance
3673 * @retval None
3674 */
LL_TIM_DisableDMAReq_CC2(TIM_TypeDef * TIMx)3675 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
3676 {
3677 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
3678 }
3679
3680 /**
3681 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
3682 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
3683 * @param TIMx Timer instance
3684 * @retval State of bit (1 or 0).
3685 */
LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef * TIMx)3686 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
3687 {
3688 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
3689 }
3690
3691 /**
3692 * @brief Enable capture/compare 3 DMA request (CC3DE).
3693 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
3694 * @param TIMx Timer instance
3695 * @retval None
3696 */
LL_TIM_EnableDMAReq_CC3(TIM_TypeDef * TIMx)3697 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
3698 {
3699 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3700 }
3701
3702 /**
3703 * @brief Disable capture/compare 3 DMA request (CC3DE).
3704 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
3705 * @param TIMx Timer instance
3706 * @retval None
3707 */
LL_TIM_DisableDMAReq_CC3(TIM_TypeDef * TIMx)3708 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
3709 {
3710 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
3711 }
3712
3713 /**
3714 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
3715 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
3716 * @param TIMx Timer instance
3717 * @retval State of bit (1 or 0).
3718 */
LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef * TIMx)3719 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
3720 {
3721 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
3722 }
3723
3724 /**
3725 * @brief Enable capture/compare 4 DMA request (CC4DE).
3726 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
3727 * @param TIMx Timer instance
3728 * @retval None
3729 */
LL_TIM_EnableDMAReq_CC4(TIM_TypeDef * TIMx)3730 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
3731 {
3732 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3733 }
3734
3735 /**
3736 * @brief Disable capture/compare 4 DMA request (CC4DE).
3737 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
3738 * @param TIMx Timer instance
3739 * @retval None
3740 */
LL_TIM_DisableDMAReq_CC4(TIM_TypeDef * TIMx)3741 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
3742 {
3743 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
3744 }
3745
3746 /**
3747 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
3748 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
3749 * @param TIMx Timer instance
3750 * @retval State of bit (1 or 0).
3751 */
LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef * TIMx)3752 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
3753 {
3754 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
3755 }
3756
3757 /**
3758 * @brief Enable commutation DMA request (COMDE).
3759 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
3760 * @param TIMx Timer instance
3761 * @retval None
3762 */
LL_TIM_EnableDMAReq_COM(TIM_TypeDef * TIMx)3763 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
3764 {
3765 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
3766 }
3767
3768 /**
3769 * @brief Disable commutation DMA request (COMDE).
3770 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
3771 * @param TIMx Timer instance
3772 * @retval None
3773 */
LL_TIM_DisableDMAReq_COM(TIM_TypeDef * TIMx)3774 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
3775 {
3776 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
3777 }
3778
3779 /**
3780 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
3781 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
3782 * @param TIMx Timer instance
3783 * @retval State of bit (1 or 0).
3784 */
LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef * TIMx)3785 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
3786 {
3787 return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
3788 }
3789
3790 /**
3791 * @brief Enable trigger interrupt (TDE).
3792 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
3793 * @param TIMx Timer instance
3794 * @retval None
3795 */
LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef * TIMx)3796 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
3797 {
3798 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
3799 }
3800
3801 /**
3802 * @brief Disable trigger interrupt (TDE).
3803 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
3804 * @param TIMx Timer instance
3805 * @retval None
3806 */
LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef * TIMx)3807 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
3808 {
3809 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
3810 }
3811
3812 /**
3813 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
3814 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
3815 * @param TIMx Timer instance
3816 * @retval State of bit (1 or 0).
3817 */
LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef * TIMx)3818 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
3819 {
3820 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
3821 }
3822
3823 /**
3824 * @}
3825 */
3826
3827 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
3828 * @{
3829 */
3830 /**
3831 * @brief Generate an update event.
3832 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
3833 * @param TIMx Timer instance
3834 * @retval None
3835 */
LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef * TIMx)3836 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
3837 {
3838 SET_BIT(TIMx->EGR, TIM_EGR_UG);
3839 }
3840
3841 /**
3842 * @brief Generate Capture/Compare 1 event.
3843 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
3844 * @param TIMx Timer instance
3845 * @retval None
3846 */
LL_TIM_GenerateEvent_CC1(TIM_TypeDef * TIMx)3847 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
3848 {
3849 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
3850 }
3851
3852 /**
3853 * @brief Generate Capture/Compare 2 event.
3854 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
3855 * @param TIMx Timer instance
3856 * @retval None
3857 */
LL_TIM_GenerateEvent_CC2(TIM_TypeDef * TIMx)3858 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
3859 {
3860 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
3861 }
3862
3863 /**
3864 * @brief Generate Capture/Compare 3 event.
3865 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
3866 * @param TIMx Timer instance
3867 * @retval None
3868 */
LL_TIM_GenerateEvent_CC3(TIM_TypeDef * TIMx)3869 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
3870 {
3871 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
3872 }
3873
3874 /**
3875 * @brief Generate Capture/Compare 4 event.
3876 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
3877 * @param TIMx Timer instance
3878 * @retval None
3879 */
LL_TIM_GenerateEvent_CC4(TIM_TypeDef * TIMx)3880 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
3881 {
3882 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
3883 }
3884
3885 /**
3886 * @brief Generate commutation event.
3887 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
3888 * @param TIMx Timer instance
3889 * @retval None
3890 */
LL_TIM_GenerateEvent_COM(TIM_TypeDef * TIMx)3891 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
3892 {
3893 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
3894 }
3895
3896 /**
3897 * @brief Generate trigger event.
3898 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
3899 * @param TIMx Timer instance
3900 * @retval None
3901 */
LL_TIM_GenerateEvent_TRIG(TIM_TypeDef * TIMx)3902 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
3903 {
3904 SET_BIT(TIMx->EGR, TIM_EGR_TG);
3905 }
3906
3907 /**
3908 * @brief Generate break event.
3909 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
3910 * @param TIMx Timer instance
3911 * @retval None
3912 */
LL_TIM_GenerateEvent_BRK(TIM_TypeDef * TIMx)3913 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
3914 {
3915 SET_BIT(TIMx->EGR, TIM_EGR_BG);
3916 }
3917
3918 /**
3919 * @}
3920 */
3921
3922 #if defined(USE_FULL_LL_DRIVER)
3923 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
3924 * @{
3925 */
3926
3927 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
3928 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
3929 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
3930 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3931 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
3932 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
3933 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
3934 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3935 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
3936 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3937 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
3938 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3939 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
3940 /**
3941 * @}
3942 */
3943 #endif /* USE_FULL_LL_DRIVER */
3944
3945 /**
3946 * @}
3947 */
3948
3949 /**
3950 * @}
3951 */
3952
3953 #endif /* TIM1 || TIM2 || TIM3 || TIM14 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */
3954
3955 /**
3956 * @}
3957 */
3958
3959 #ifdef __cplusplus
3960 }
3961 #endif
3962
3963 #endif /* __STM32F0xx_LL_TIM_H */
3964 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3965