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Searched refs:CLASS_CSR_BASE_ADDR (Results 1 – 2 of 2) sorted by relevance

/u-boot-v2022.01-rc1/include/net/pfe_eth/pfe/cbus/
A Dclass_csr.h16 #define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
17 #define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
18 #define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
20 #define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
94 #define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
96 #define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
98 #define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
100 #define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
102 #define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
110 #define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
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/u-boot-v2022.01-rc1/include/net/pfe_eth/pfe/
A Dcbus.h36 #define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000) macro

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