| /u-boot-v2022.01-rc1/arch/x86/cpu/queensbay/ |
| A D | Kconfig | 29 bool "Add a Chipset Micro Code state machine binary"
31 Select this option to add a Chipset Micro Code state machine binary
37 string "Chipset Micro Code state machine filename"
41 The filename of the file to use as Chipset Micro Code state machine
45 hex "Chipset Micro Code state machine binary location"
|
| /u-boot-v2022.01-rc1/doc/develop/ |
| A D | crash_dumps.rst | 43 Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb)
65 We can convert the instructions in the line starting with 'Code:' into mnemonics
69 $echo 'Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb)' | \
71 Code: b00003c0 912ad000 940029d6 17ffff52 (e7f7defb)
80 Code starting with the faulting instruction
|
| A D | menus.rst | 82 Example Code
|
| /u-boot-v2022.01-rc1/scripts/ |
| A D | decodecode | 29 *Code:*)
105 echo Code starting with the faulting instruction > $T.aa
|
| /u-boot-v2022.01-rc1/board/armltd/integrator/ |
| A D | README | 45 Code Hierarchy Applied :
47 Code specific to initialization of a particular ARM processor has been placed in
58 Code specific to the initialization of the CM, rather than the cpu, and initialization
|
| /u-boot-v2022.01-rc1/doc/board/google/ |
| A D | chromebook_link.rst | 11 * mrc.bin - Memory Reference Code, which sets up SDRAM
|
| A D | chromebook_samus.rst | 11 * mrc.bin - Memory Reference Code, which sets up SDRAM
|
| /u-boot-v2022.01-rc1/doc/imx/habv4/ |
| A D | introduction_habv4.txt | 64 authentication process, this is generated by the Code Signing Tool[1].
68 Details about the Secure Boot and Code Signing Tool (CST) can be found in
123 The Code Signing Tool automatically generates a random AES Data Encryption Key
149 The Code Signing Tools package contains an OpenSSL based key generation script
259 [1] CST: i.MX High Assurance Boot Reference Code Signing Tool.
|
| /u-boot-v2022.01-rc1/doc/ |
| A D | README.Heterogeneous-SoCs | 9 Code for DSP side awareness provides such functionality for Freescale
19 Code added in this file to print the DSP cores and other device's(CPRI,
|
| A D | README.s5p4418 | 61 [5] FriendlyArm LUbuntu 16.04 Source Code for NanoPi2:
|
| A D | README.unaligned-memory-access.txt | 70 Code that does not cause unaligned access
139 Code that causes unaligned access
|
| A D | README.ramboot-ppc85xx | 68 Necessary Code changes Required:
|
| /u-boot-v2022.01-rc1/arch/arm/mach-omap2/ |
| A D | lowlevel_init.S | 61 @ call ROM Code API for the service requested
|
| /u-boot-v2022.01-rc1/lib/zlib/ |
| A D | trees.c | 169 # define send_code(s, c, tree) send_bits(s, tree[c].Code, tree[c].Len)
175 send_bits(s, tree[c].Code, tree[c].Len); }
312 static_dtree[n].Code = bi_reverse((unsigned)n, 5); in tr_static_init()
345 fprintf(header, "{{%3u},{%3u}}%s", static_ltree[i].Code, in gen_trees_header()
351 fprintf(header, "{{%2u},{%2u}}%s", static_dtree[i].Code, in gen_trees_header()
609 tree[n].Code = bi_reverse(next_code[len]++, len);
612 n, (isgraph(n) ? n : ' '), len, tree[n].Code, next_code[len]-1));
|
| A D | deflate.h | 74 #define Code fc.code macro
|
| /u-boot-v2022.01-rc1/arch/powerpc/cpu/mpc85xx/ |
| A D | u-boot.lds | 108 * this is a temporary fix. Code to dynamically the fixup the bss
|
| /u-boot-v2022.01-rc1/drivers/fpga/ |
| A D | ivm_core.c | 297 static signed char ispVMShift(signed char Code);
298 static signed char ispVMAmble(signed char Code);
1719 signed char ispVMAmble(signed char Code) in ispVMAmble() argument
1744 switch (Code) { in ispVMAmble()
1866 Code = GetByte(); in ispVMAmble()
1867 if (Code == CONTINUE) { in ispVMAmble()
|
| /u-boot-v2022.01-rc1/doc/sphinx-static/ |
| A D | theme_overrides.css | 7 /* Interim: Code-blocks with line nos - lines and line numbers don't line up.
|
| /u-boot-v2022.01-rc1/doc/device-tree-bindings/input/ |
| A D | cros-ec-keyb.txt | 28 * RR=Row CC=Column KKKK=Key Code
|
| /u-boot-v2022.01-rc1/doc/imx/habv4/guides/ |
| A D | encrypted_boot.txt | 4 Encrypted Boot. The image is encrypted by i.MX Code Signing
|
| /u-boot-v2022.01-rc1/doc/board/intel/ |
| A D | crownbay.rst | 14 also requires a Chipset Micro Code (CMC) state machine binary to be present in
|
| /u-boot-v2022.01-rc1/arch/arm/dts/ |
| A D | exynos5420-peach-pit.dts | 187 * DPCD40A, Initial Code major revision
191 /* DPCD40B Initial Code minor revision '05' */
|
| A D | exynos5250-spring.dts | 659 /* DPCD40A Initial Code major revision '01' */
661 /* DPCD40B Initial Code minor revision '05' */
|
| /u-boot-v2022.01-rc1/doc/device-tree-bindings/gpio/ |
| A D | nvidia,tegra186-gpio.txt | 19 Access to this set of registers is not necessary in all circumstances. Code
21 registers to do so. Code which simply wishes to read or write GPIO data does not
|
| /u-boot-v2022.01-rc1/doc/imx/ahab/guides/ |
| A D | mx8_mx8x_encrypted_boot.txt | 93 The encryption feature is not enabled by default in Code Signing tools (CST).
145 The image is encrypted using the Code Signing Tool. The tool generates the
|