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Searched refs:PLLE_MISC_SETUP_BASE (Results 1 – 2 of 2) sorted by relevance

/u-boot-v2022.01-rc1/arch/arm/mach-tegra/tegra20/
A Dclock.c640 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) macro
694 value &= ~PLLE_MISC_SETUP_BASE(0xffff); in tegra_plle_enable()
708 value |= PLLE_MISC_SETUP_BASE(0x7); in tegra_plle_enable()
/u-boot-v2022.01-rc1/arch/arm/mach-tegra/tegra30/
A Dclock.c669 #define PLLE_MISC_SETUP_BASE(x) (((x) & 0xffff) << 16) macro
723 value &= ~PLLE_MISC_SETUP_BASE(0xffff); in tegra_plle_enable()
754 value |= PLLE_MISC_SETUP_BASE(0x7); in tegra_plle_enable()

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