Searched refs:REG_SDRAM_CONFIG_ADDR (Results 1 – 6 of 6) sorted by relevance
| /u-boot-v2022.01-rc1/drivers/ddr/marvell/axp/ |
| A D | ddr3_dfs.c | 382 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
391 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
667 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
672 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
1039 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & in ddr3_dfs_low_2_high()
1042 tmp = reg_read(REG_SDRAM_CONFIG_ADDR) | in ddr3_dfs_low_2_high()
1045 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1056 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1065 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1400 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
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| A D | ddr3_init.c | 86 debug_print_reg(REG_SDRAM_CONFIG_ADDR); in print_dunit_setup()
471 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
473 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
493 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
641 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & in ddr3_init_main()
643 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_init_main()
659 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_init_main()
661 reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19)); in ddr3_init_main()
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| A D | ddr3_hw_training.c | 107 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
111 reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_hw_training()
116 reg = reg_read(REG_SDRAM_CONFIG_ADDR); in ddr3_hw_training()
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| A D | ddr3_axp.h | 81 #define REG_SDRAM_CONFIG_ADDR 0x1400 macro
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| A D | ddr3_spd.c | 714 REG_SDRAM_CONFIG_ADDR, REG_SDRAM_CONFIG_ECC_OFFS, 0x1, 0, 0);
758 stat_val = ddr3_get_static_mc_value(REG_SDRAM_CONFIG_ADDR, 0,
776 reg_write(REG_SDRAM_CONFIG_ADDR, reg);
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| /u-boot-v2022.01-rc1/arch/arm/mach-mvebu/ |
| A D | dram.c | 180 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
182 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
210 temp = reg_read(REG_SDRAM_CONFIG_ADDR); in dram_ecc_scrubbing()
212 reg_write(REG_SDRAM_CONFIG_ADDR, temp); in dram_ecc_scrubbing()
217 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS)) in ecc_enabled()
228 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) in bus_width()
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