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Searched refs:clk_ctrl (Results 1 – 6 of 6) sorted by relevance

/u-boot-v2022.01-rc1/drivers/clk/
A Dclk_zynq.c157 u32 clk_ctrl, srcsel; in zynq_clk_get_gem_rclk() local
174 u32 clk_621, clk_ctrl, div; in zynq_clk_get_cpu_rate() local
206 u32 clk_ctrl, div; in zynq_clk_get_ddr2x_rate() local
218 u32 clk_ctrl, div; in zynq_clk_get_ddr3x_rate() local
230 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
246 u32 clk_ctrl, div0; in zynq_clk_get_peripheral_rate() local
321 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
326 clk_ctrl = readl(reg); in zynq_clk_set_peripheral_rate()
330 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynq_clk_set_peripheral_rate()
332 clk_ctrl &= ~CLK_CTRL_DIV1_MASK; in zynq_clk_set_peripheral_rate()
[all …]
A Dclk_zynqmp.c354 u32 clk_ctrl, reset, mul; in zynqmp_clk_get_pll_rate() local
364 if (clk_ctrl & PLLCTRL_BYPASS_MASK) in zynqmp_clk_get_pll_rate()
377 if (clk_ctrl & (1 << 16)) in zynqmp_clk_get_pll_rate()
386 u32 clk_ctrl, div, srcsel; in zynqmp_clk_get_cpu_rate() local
410 u32 clk_ctrl, div, srcsel; in zynqmp_clk_get_ddr_rate() local
434 u32 clk_ctrl, srcsel; in zynqmp_clk_get_dll_rate() local
458 u32 clk_ctrl, div0, srcsel; in zynqmp_clk_get_peripheral_rate() local
498 u32 clk_ctrl, div0, srcsel; in zynqmp_clk_get_crf_crl_rate() local
605 u32 clk_ctrl, div0 = 0, div1 = 0; in zynqmp_clk_set_peripheral_rate() local
624 clk_ctrl &= ~CLK_CTRL_DIV0_MASK; in zynqmp_clk_set_peripheral_rate()
[all …]
/u-boot-v2022.01-rc1/arch/mips/mach-ath79/qca956x/
A Dclk.c314 u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl; in get_clocks() local
368 clk_ctrl = readl(regs + QCA956X_PLL_CLK_CTRL_REG); in get_clocks()
370 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) & in get_clocks()
373 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS) in get_clocks()
375 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL) in get_clocks()
380 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) & in get_clocks()
383 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS) in get_clocks()
385 else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL) in get_clocks()
390 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) & in get_clocks()
393 if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS) in get_clocks()
[all …]
/u-boot-v2022.01-rc1/arch/mips/mach-jz47xx/jz4780/
A Dpll.c387 u32 clk_ctrl; in cpu_mux_select() local
396 clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 | in cpu_mux_select()
403 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT; in cpu_mux_select()
405 clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT; in cpu_mux_select()
407 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); in cpu_mux_select()
413 clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) | in cpu_mux_select()
417 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT; in cpu_mux_select()
419 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT; in cpu_mux_select()
421 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); in cpu_mux_select()
/u-boot-v2022.01-rc1/arch/arm/cpu/armv8/fsl-layerscape/
A Dfsl_lsch3_speed.c36 struct ccsr_clk_ctrl __iomem *clk_ctrl = in get_sys_info() local
124 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) in get_sys_info()
/u-boot-v2022.01-rc1/drivers/spi/
A Dti_qspi.c82 u32 clk_ctrl; member
128 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_qspi_set_speed()
129 &priv->base->clk_ctrl); in ti_qspi_set_speed()
131 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_qspi_set_speed()

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