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Searched refs:data_width (Results 1 – 13 of 13) sorted by relevance

/u-boot-v2022.01-rc1/drivers/mtd/nand/raw/
A Dzynq_nand.c445 int data_width = 4; in zynq_nand_read_oob() local
452 p += mtd->oobsize - data_width; in zynq_nand_read_oob()
471 int status = 0, data_width = 4; in zynq_nand_write_oob() local
478 buf += mtd->oobsize - data_width; in zynq_nand_write_oob()
504 unsigned long data_width = 4; in zynq_nand_read_page_raw() local
512 p += (mtd->oobsize - data_width); in zynq_nand_read_page_raw()
552 unsigned long data_width = 4; in zynq_nand_write_page_raw() local
589 unsigned long data_width = 4; in zynq_nand_write_page_hwecc() local
597 p += eccsize - data_width; in zynq_nand_write_page_hwecc()
682 unsigned long data_width = 4; in zynq_nand_read_page_hwecc() local
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/u-boot-v2022.01-rc1/include/
A Dfsl_ddr_dimm_params.h24 unsigned int data_width; member
/u-boot-v2022.01-rc1/drivers/ddr/marvell/axp/
A Dddr3_spd.c146 u32 data_width; member
308 info->data_width = in ddr3_spd_init()
310 DEBUG_INIT_FULL_C("DRAM data_width ", info->data_width, 1); in ddr3_spd_init()
336 (info->data_width / info->sdram_width)) << 16; in ddr3_spd_init()
341 (info->data_width / info->sdram_width) * 0x2) << 16; in ddr3_spd_init()
348 ((info->data_width / info->sdram_width) * in ddr3_spd_init()
520 if (sum_info->data_width != info->data_width) { in ddr3_spd_sum_init()
737 if (ddr3_get_min_val(sum_info.data_width, dimm_num, BUS_WIDTH) == 64) {
/u-boot-v2022.01-rc1/drivers/spi/
A Dcadence_qspi.h43 u8 data_width; member
A Dcadence_qspi_apb.c238 rdreg |= plat->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cadence_qspi_calc_rdreg()
284 plat->data_width = ret; in cadence_qspi_set_protocol()
918 reg |= plat->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cadence_qspi_apb_write_setup()
/u-boot-v2022.01-rc1/drivers/ddr/fsl/
A Doptions.c926 if ((pdimm[0].data_width >= 64) && \ in populate_memctl_options()
927 (pdimm[0].data_width <= 72)) in populate_memctl_options()
929 else if ((pdimm[0].data_width >= 32) && \ in populate_memctl_options()
930 (pdimm[0].data_width <= 40)) in populate_memctl_options()
934 pdimm[0].data_width); in populate_memctl_options()
A Dddr1_dimm_params.c257 pdimm->data_width = spd->dataw_lsb; in ddr_compute_dimm_parameters()
A Dddr2_dimm_params.c240 pdimm->data_width = spd->dataw; in ddr_compute_dimm_parameters()
A Dddr3_dimm_params.c128 pdimm->data_width = pdimm->primary_sdram_width in ddr_compute_dimm_parameters()
A Dddr4_dimm_params.c181 pdimm->data_width = pdimm->primary_sdram_width in ddr_compute_dimm_parameters()
A Dmain.c351 dw = pinfo->dimm_params[i][j].data_width; in __step_assign_addresses()
A Dinteractive.c228 DIMM_PARM(data_width), in fsl_ddr_dimm_parameters_edit()
327 DIMM_PARM(data_width), in print_dimm_parameters()
/u-boot-v2022.01-rc1/doc/
A DREADME.fsl-ddr370 data_width = 64

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