Home
last modified time | relevance | path

Searched refs:ddr (Results 1 – 25 of 256) sorted by relevance

1234567891011

/u-boot-v2022.01-rc1/drivers/ddr/fsl/
A Dfsl_ddr_gen4.c57 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
124 ddr_out32(&ddr->cs0_bnds, in fsl_ddr_set_memctl_regs()
126 ddr_out32(&ddr->cs0_config, in fsl_ddr_set_memctl_regs()
137 ddr_out32(&ddr->cs1_bnds, in fsl_ddr_set_memctl_regs()
147 ddr_out32(&ddr->cs2_bnds, in fsl_ddr_set_memctl_regs()
157 ddr_out32(&ddr->cs3_bnds, in fsl_ddr_set_memctl_regs()
229 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
235 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
272 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
283 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen3.c30 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
163 out_be32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
169 out_be32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
219 out_be32(&ddr->mtcr, 0); in fsl_ddr_set_memctl_regs()
233 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
244 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
253 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
264 out_be32(&ddr->sdram_md_cntl, in fsl_ddr_set_memctl_regs()
420 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
506 in_be32(&ddr->sdram_cfg_2)); in fsl_ddr_set_memctl_regs()
[all …]
A Darm_ddr_gen3.c36 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
43 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
47 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
52 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
57 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
69 ddr_out32(&ddr->eor, regs->ddr_eor); in fsl_ddr_set_memctl_regs()
128 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); in fsl_ddr_set_memctl_regs()
131 ddr_out32(&ddr->sdram_cfg_2, in fsl_ddr_set_memctl_regs()
137 ddr_out32(&ddr->ddr_cdr2, in fsl_ddr_set_memctl_regs()
145 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); in fsl_ddr_set_memctl_regs()
[all …]
A Dmpc85xx_ddr_gen2.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
50 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
51 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
54 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
55 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
58 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
62 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
78 out_be32(&ddr->init_addr, regs->ddr_init_addr); in fsl_ddr_set_memctl_regs()
88 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
[all …]
A Dctrl_regs.c227 ddr->cs[i].config = (0 in set_csn_config()
440 ddr->timing_cfg_0 = (0 in set_timing_cfg_0()
493 ddr->timing_cfg_3 = (0 in set_timing_cfg_3()
621 ddr->timing_cfg_1 = (0 in set_timing_cfg_1()
714 ddr->timing_cfg_2 = (0 in set_timing_cfg_2()
850 ddr->ddr_sdram_cfg = (0 in set_ddr_sdram_cfg()
1927 ddr->timing_cfg_4 = (0 in set_timing_cfg_4()
1957 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1975 ddr->timing_cfg_6 = (0 in set_timing_cfg_6()
2204 ddr->ddr_zq_cntl = (0 in set_ddr_zq_cntl()
[all …]
A Dmpc85xx_ddr_gen1.c20 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
30 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
31 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
59 out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); in fsl_ddr_set_memctl_regs()
73 struct ccsr_ddr __iomem *ddr = in ddr_enable_ecc() local
[all …]
A Dutil.c31 struct ccsr_ddr __iomem *ddr; in fsl_ddr_get_version() local
36 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_get_version()
40 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_get_version()
45 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_get_version()
50 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_get_version()
179 struct ccsr_ddr __iomem *ddr = in print_ddr_info() local
195 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
202 sdram_cfg = ddr_in32(&ddr->sdram_cfg); in print_ddr_info()
347 struct ccsr_ddr __iomem *ddr; in fsl_ddr_sync_memctl_refresh() local
352 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_sync_memctl_refresh()
[all …]
/u-boot-v2022.01-rc1/post/cpu/mpc83xx/
A Decc.c29 __raw_writel(0, &ddr->capture_address); in ecc_clear()
30 __raw_writel(0, &ddr->capture_data_hi); in ecc_clear()
31 __raw_writel(0, &ddr->capture_data_lo); in ecc_clear()
32 __raw_writel(0, &ddr->capture_ecc); in ecc_clear()
33 __raw_writel(0, &ddr->capture_attributes); in ecc_clear()
53 ddr83xx_t *ddr = &((immap_t *)CONFIG_SYS_IMMR)->ddr; in ecc_post_test() local
78 ecc_clear(ddr); in ecc_post_test()
118 ddr->data_err_inject_hi, in ecc_post_test()
119 ddr->data_err_inject_lo, in ecc_post_test()
125 ddr->capture_data_hi, ddr->capture_data_lo); in ecc_post_test()
[all …]
/u-boot-v2022.01-rc1/arch/powerpc/cpu/mpc83xx/
A Decc.c18 struct ccsr_ddr __iomem *ddr = &immap->ddr; in ecc_print_status() local
20 ddr83xx_t *ddr = &immap->ddr; in ecc_print_status() local
46 ddr->data_err_inject_hi, ddr->data_err_inject_lo); in ecc_print_status()
77 ddr->capture_data_hi, ddr->capture_data_lo); in ecc_print_status()
102 struct ccsr_ddr __iomem *ddr = &immap->ddr; in do_ecc() local
104 ddr83xx_t *ddr = &immap->ddr; in do_ecc() local
133 ddr->capture_ecc = 0; in do_ecc()
150 ddr->err_sbe = val; in do_ecc()
163 ddr->err_sbe = val; in do_ecc()
198 val = ddr->err_detect; in do_ecc()
[all …]
A Dspd_sdram.c35 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() local
134 volatile ddr83xx_t *ddr = &immap->ddr; in spd_sdram() local
242 ddr->cs_config[1] = ( 1<<31 in spd_sdram()
267 ddr->cs_config[3] = ( 1<<31 in spd_sdram()
475 ddr->timing_cfg_0 = (0 in spd_sdram()
538 ddr->timing_cfg_1 = in spd_sdram()
630 ddr->timing_cfg_2 = (0 in spd_sdram()
693 ddr->sdram_mode = in spd_sdram()
711 ddr->sdram_mode2 = 0; in spd_sdram()
761 ddr->sdram_cfg2 = (0 in spd_sdram()
[all …]
/u-boot-v2022.01-rc1/board/freescale/ls1021atsn/
A Dls1021atsn.c34 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
36 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
37 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
48 out_be32(&ddr->sdram_cfg_2, in ddrmc_init()
51 out_be32(&ddr->init_ext_addr, (1 << 31)); in ddrmc_init()
54 out_be32(&ddr->ddr_cdr2, in ddrmc_init()
60 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
63 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
73 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
81 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot-v2022.01-rc1/board/freescale/ls1021aiot/
A Dls1021aiot.c56 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
58 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
59 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
61 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); in ddrmc_init()
68 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); in ddrmc_init()
69 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
71 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
81 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
84 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); in ddrmc_init()
89 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot-v2022.01-rc1/board/socrates/
A Dsdram.c28 struct ccsr_ddr __iomem *ddr = in fixed_sdram() local
34 ddr->cs0_config = 0; in fixed_sdram()
35 ddr->sdram_cfg = 0; in fixed_sdram()
37 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
38 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
39 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
40 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
41 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
42 ddr->sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
44 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2; in fixed_sdram()
[all …]
/u-boot-v2022.01-rc1/board/gdsys/mpc8308/
A Dsdram.c45 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
49 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
52 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
53 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
54 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
55 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
57 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
58 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
59 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
60 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
[all …]
/u-boot-v2022.01-rc1/board/ids/ids8313/
A Dids8313.c76 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); in fixed_sdram()
77 out_be32(&im->ddr.cs_config[0], config); in fixed_sdram()
80 out_be32(&im->ddr.cs_config[1], 0); in fixed_sdram()
81 out_be32(&im->ddr.cs_config[2], 0); in fixed_sdram()
82 out_be32(&im->ddr.cs_config[3], 0); in fixed_sdram()
84 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
89 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG); in fixed_sdram()
90 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2); in fixed_sdram()
92 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
93 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2); in fixed_sdram()
[all …]
/u-boot-v2022.01-rc1/board/freescale/ls1021atwr/
A Dls1021atwr.c150 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); in ddrmc_init()
152 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); in ddrmc_init()
153 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); in ddrmc_init()
164 out_be32(&ddr->sdram_cfg_2, in ddrmc_init()
167 out_be32(&ddr->init_ext_addr, (1 << 31)); in ddrmc_init()
170 out_be32(&ddr->ddr_cdr2, in ddrmc_init()
176 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); in ddrmc_init()
179 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); in ddrmc_init()
189 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); in ddrmc_init()
197 tmp = in_be32(&ddr->debug[28]); in ddrmc_init()
[all …]
/u-boot-v2022.01-rc1/arch/arm/mach-imx/mx6/
A Dddr.c747 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sl_dram_iocfg()
748 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sl_dram_iocfg()
774 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6sl_dram_iocfg()
775 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6sl_dram_iocfg()
804 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6dq_dram_iocfg()
805 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6dq_dram_iocfg()
846 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0; in mx6dq_dram_iocfg()
847 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1; in mx6dq_dram_iocfg()
882 mx6_ddr_iomux->dram_cas = ddr->dram_cas; in mx6sdl_dram_iocfg()
883 mx6_ddr_iomux->dram_ras = ddr->dram_ras; in mx6sdl_dram_iocfg()
[all …]
/u-boot-v2022.01-rc1/board/keymile/km83xx/
A Dkm83xx.c128 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
129 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
130 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
131 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
132 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
133 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
134 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); in fixed_sdram()
135 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); in fixed_sdram()
136 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); in fixed_sdram()
140 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); in fixed_sdram()
[all …]
/u-boot-v2022.01-rc1/board/freescale/mpc837xerdb/
A Dmpc837xerdb.c113 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
116 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; in fixed_sdram()
117 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
118 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
119 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; in fixed_sdram()
120 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; in fixed_sdram()
121 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; in fixed_sdram()
122 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; in fixed_sdram()
123 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; in fixed_sdram()
124 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; in fixed_sdram()
[all …]
/u-boot-v2022.01-rc1/doc/board/nxp/
A Dimx8mp_evk.rst26 Get the ddr firmware
43 $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem_202006.bin ./build/
44 $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem_202006.bin ./build/
45 $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem_202006.bin ./build/
46 $ cp ../firmware-imx-8.10/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem_202006.bin ./build/
/u-boot-v2022.01-rc1/drivers/ddr/imx/
A DKconfig1 source "drivers/ddr/imx/imx8m/Kconfig"
2 source "drivers/ddr/imx/imx8ulp/Kconfig"
/u-boot-v2022.01-rc1/arch/mips/mach-ath79/qca956x/
A DMakefile5 obj-y += ddr.o qca956x-ddr-tap.o
/u-boot-v2022.01-rc1/drivers/
A DMakefile45 obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR) += ddr/fsl/
46 obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/
47 obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/
48 obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/
49 obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/
50 obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/
68 obj-$(CONFIG_TPL_MPC8XXX_INIT_DDR) += ddr/fsl/
115 obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
/u-boot-v2022.01-rc1/arch/arm/mach-mvebu/
A DMakefile25 obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o
26 obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o
27 obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o
28 obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o
/u-boot-v2022.01-rc1/arch/mips/mach-mtmips/mt7628/
A Dinit.c52 u32 val, ver, eco, pkg, ddr, chipmode, ee; in print_cpuinfo() local
65 ddr = val & DRAM_TYPE; in print_cpuinfo()
72 ddr = DRAM_DDR1; in print_cpuinfo()
78 ddr ? "" : "2", chipmode & 0x01 ? 4 : 3, in print_cpuinfo()

Completed in 50 milliseconds

1234567891011