Searched refs:ddr3_read_pup_reg (Results 1 – 5 of 5) sorted by relevance
| /u-boot-v2022.01-rc1/drivers/ddr/marvell/axp/ |
| A D | ddr3_hw_training.c | 599 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup) in ddr3_read_pup_reg() function
731 val = ddr3_read_pup_reg( in ddr3_save_training()
742 val = ddr3_read_pup_reg( in ddr3_save_training()
753 val = ddr3_read_pup_reg( in ddr3_save_training()
1056 reg = ddr3_read_pup_reg(PUP_RL_MODE, cs, pup); in ddr3_get_min_max_rl_phase()
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| A D | ddr3_write_leveling.c | 117 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw()
128 ddr3_read_pup_reg(PUP_WL_MODE + 0x1, in ddr3_write_leveling_hw()
438 reg = ddr3_read_pup_reg(PUP_WL_MODE, cs, pup); in ddr3_wl_supplement()
540 ddr3_read_pup_reg(PUP_WL_MODE, cs, in ddr3_write_leveling_hw_reg_dimm()
564 ddr3_read_pup_reg(PUP_WL_MODE + 0x1, in ddr3_write_leveling_hw_reg_dimm()
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| A D | ddr3_read_leveling.c | 107 ddr3_read_pup_reg(PUP_RL_MODE, cs, in ddr3_read_leveling_hw()
121 ddr3_read_pup_reg(PUP_RL_MODE + 0x1, in ddr3_read_leveling_hw()
732 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_rl_mode()
1207 reg = ddr3_read_pup_reg(PUP_RL_MODE + 0x1, cs, pup); in ddr3_read_leveling_single_cs_window_mode()
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| A D | ddr3_hw_training.h | 327 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
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| A D | ddr3_pbs.c | 1512 reg = (ddr3_read_pup_reg(PUP_WL_MODE, cs, pup) & 0x3FF); in ddr3_pbs_write_pup_dqs_reg()
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