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Searched refs:ddr_pll_ctl (Results 1 – 2 of 2) sorted by relevance

/u-boot-v2022.01-rc1/drivers/ram/octeon/
A Docteon_ddr.c580 ddr_pll_ctl.cn78xx.reset_n = 0; in initialize_ddr_clock()
614 ddr_pll_ctl.u64); in initialize_ddr_clock()
843 ddr_pll_ctl.u64 = in initialize_ddr_clock()
846 i, ddr_pll_ctl.u64); in initialize_ddr_clock()
856 i, ddr_pll_ctl.u64); in initialize_ddr_clock()
887 ddr_pll_ctl.u64 = in initialize_ddr_clock()
936 ddr_pll_ctl.u64 = lmc_rd(priv, in initialize_ddr_clock()
947 ddr_pll_ctl.u64 = in initialize_ddr_clock()
2427 ddr_pll_ctl.u64 = in octeon_ddr_initialize()
2438 ddr_pll_ctl.u64); in octeon_ddr_initialize()
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A Docteon3_lmc.c10778 union cvmx_lmcx_ddr_pll_ctl ddr_pll_ctl; in cvmx_dbi_switchover_interface() local
10787 ddr_pll_ctl.u64 = lmc_rd(priv, CVMX_LMCX_DDR_PLL_CTL(0)); in cvmx_dbi_switchover_interface()
10795 if (ddr_pll_ctl.s.ddr4_mode == 0 || lmcx_config.s.mode_x4dev == 1) { in cvmx_dbi_switchover_interface()

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