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/u-boot-v2022.01-rc1/arch/mips/mach-octeon/include/mach/
A Dcvmx-pexp-defs.h12 #define CVMX_PEXP_NPEI_BAR1_INDEXX(offset) (0x00011F0000008000ull + ((offset) & 31) * 16) argument
24 #define CVMX_PEXP_NPEI_DMAX_COUNTS(offset) (0x00011F0000008450ull + ((offset) & 7) * 16) argument
25 #define CVMX_PEXP_NPEI_DMAX_DBELL(offset) (0x00011F00000083B0ull + ((offset) & 7) * 16) argument
26 #define CVMX_PEXP_NPEI_DMAX_IBUFF_SADDR(offset) (0x00011F0000008400ull + ((offset) & 7) * 16) argument
27 #define CVMX_PEXP_NPEI_DMAX_NADDR(offset) (0x00011F00000084A0ull + ((offset) & 7) * 16) argument
74 #define CVMX_PEXP_NPEI_PKTX_CNTS(offset) (0x00011F000000A400ull + ((offset) & 31) * 16) argument
79 #define CVMX_PEXP_NPEI_PKTX_IN_BP(offset) (0x00011F000000B800ull + ((offset) & 31) * 16) argument
142 #define CVMX_PEXP_SLITB_PFX_PKT_INT(offset) (0x00011F0000008300ull + ((offset) & 7) * 16) argument
143 #define CVMX_PEXP_SLITB_PFX_PKT_IN_INT(offset) (0x00011F0000008200ull + ((offset) & 7) * 16) argument
311 #define CVMX_PEXP_SLI_INT_ENB_PORTX(offset) (0x00011F0000010340ull + ((offset) & 3) * 16) argument
[all …]
A Dcvmx-dtx-defs.h14 #define CVMX_DTX_AGL_DATX(offset) (0x00011800FE700040ull + ((offset) & 1) * 8) argument
15 #define CVMX_DTX_AGL_ENAX(offset) (0x00011800FE700020ull + ((offset) & 1) * 8) argument
16 #define CVMX_DTX_AGL_SELX(offset) (0x00011800FE700000ull + ((offset) & 1) * 8) argument
19 #define CVMX_DTX_ASE_DATX(offset) (0x00011800FE6E8040ull + ((offset) & 1) * 8) argument
20 #define CVMX_DTX_ASE_ENAX(offset) (0x00011800FE6E8020ull + ((offset) & 1) * 8) argument
21 #define CVMX_DTX_ASE_SELX(offset) (0x00011800FE6E8000ull + ((offset) & 1) * 8) argument
24 #define CVMX_DTX_BBX1I_DATX(offset) (0x00011800FED78040ull + ((offset) & 1) * 8) argument
25 #define CVMX_DTX_BBX1I_ENAX(offset) (0x00011800FED78020ull + ((offset) & 1) * 8) argument
55 #define CVMX_DTX_BTS_DATX(offset) (0x00011800FE5B0040ull + ((offset) & 1) * 8) argument
56 #define CVMX_DTX_BTS_ENAX(offset) (0x00011800FE5B0020ull + ((offset) & 1) * 8) argument
[all …]
A Dcvmx-bgxx-defs.h102 #define CVMX_BGXX_CMR_BAD(offset) (0x00011800E0001020ull + ((offset) & 7) * 0x1000000ull) argument
106 #define CVMX_BGXX_CMR_ECO(offset) (0x00011800E0001028ull + ((offset) & 7) * 0x1000000ull) argument
108 #define CVMX_BGXX_CMR_MEM_CTRL(offset) (0x00011800E0000018ull + ((offset) & 7) * 0x1000000ull) argument
109 #define CVMX_BGXX_CMR_MEM_INT(offset) (0x00011800E0000010ull + ((offset) & 7) * 0x1000000ull) argument
110 #define CVMX_BGXX_CMR_NXC_ADR(offset) (0x00011800E0001018ull + ((offset) & 7) * 0x1000000ull) argument
113 #define CVMX_BGXX_CMR_RX_LMACS(offset) (0x00011800E0000308ull + ((offset) & 7) * 0x1000000ull) argument
114 #define CVMX_BGXX_CMR_RX_OVR_BP(offset) (0x00011800E0000318ull + ((offset) & 7) * 0x1000000ull) argument
115 #define CVMX_BGXX_CMR_TX_LMACS(offset) (0x00011800E0001000ull + ((offset) & 7) * 0x1000000ull) argument
162 #define CVMX_BGXX_GMP_GMI_TX_IFG(offset) (0x00011800E0039000ull + ((offset) & 7) * 0x1000000ull) argument
163 #define CVMX_BGXX_GMP_GMI_TX_JAM(offset) (0x00011800E0039008ull + ((offset) & 7) * 0x1000000ull) argument
[all …]
A Dcvmx-pciercx-defs.h900 #define CVMX_PCIERCX_CFG044(offset) (0x00000200000000B0ull + ((offset) & 3) * 0x100000000ull) argument
901 #define CVMX_PCIERCX_CFG045(offset) (0x00000200000000B4ull + ((offset) & 3) * 0x100000000ull) argument
902 #define CVMX_PCIERCX_CFG046(offset) (0x00000200000000B8ull + ((offset) & 3) * 0x100000000ull) argument
1239 #define CVMX_PCIERCX_CFG086(offset) (0x0000020000000158ull + ((offset) & 3) * 0x100000000ull) argument
1240 #define CVMX_PCIERCX_CFG087(offset) (0x000002000000015Cull + ((offset) & 3) * 0x100000000ull) argument
1241 #define CVMX_PCIERCX_CFG088(offset) (0x0000020000000160ull + ((offset) & 3) * 0x100000000ull) argument
1242 #define CVMX_PCIERCX_CFG089(offset) (0x0000020000000164ull + ((offset) & 3) * 0x100000000ull) argument
1243 #define CVMX_PCIERCX_CFG090(offset) (0x0000020000000168ull + ((offset) & 3) * 0x100000000ull) argument
1244 #define CVMX_PCIERCX_CFG091(offset) (0x000002000000016Cull + ((offset) & 3) * 0x100000000ull) argument
1245 #define CVMX_PCIERCX_CFG092(offset) (0x0000020000000170ull + ((offset) & 3) * 0x100000000ull) argument
[all …]
A Dcvmx-asxx-defs.h14 #define CVMX_ASXX_INT_EN(offset) (0x00011800B0000018ull + ((offset) & 1) * 0x8000000ull) argument
15 #define CVMX_ASXX_INT_REG(offset) (0x00011800B0000010ull + ((offset) & 1) * 0x8000000ull) argument
17 #define CVMX_ASXX_PRT_LOOP(offset) (0x00011800B0000040ull + ((offset) & 1) * 0x8000000ull) argument
18 #define CVMX_ASXX_RLD_BYPASS(offset) (0x00011800B0000248ull + ((offset) & 1) * 0x8000000ull) argument
20 #define CVMX_ASXX_RLD_COMP(offset) (0x00011800B0000220ull + ((offset) & 1) * 0x8000000ull) argument
30 #define CVMX_ASXX_RX_PRT_EN(offset) (0x00011800B0000000ull + ((offset) & 1) * 0x8000000ull) argument
31 #define CVMX_ASXX_RX_WOL(offset) (0x00011800B0000100ull + ((offset) & 1) * 0x8000000ull) argument
32 #define CVMX_ASXX_RX_WOL_MSK(offset) (0x00011800B0000108ull + ((offset) & 1) * 0x8000000ull) argument
33 #define CVMX_ASXX_RX_WOL_POWOK(offset) (0x00011800B0000118ull + ((offset) & 1) * 0x8000000ull) argument
37 #define CVMX_ASXX_TX_COMP_BYP(offset) (0x00011800B0000068ull + ((offset) & 1) * 0x8000000ull) argument
[all …]
A Dcvmx-pcsx-defs.h18 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
20 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
23 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x4000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
25 return 0x00011800B0001010ull + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_ADV_REG()
34 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
36 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
39 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x4000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
41 return 0x00011800B0001028ull + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_EXT_ST_REG()
50 return 0x00011800B0001018ull + ((offset) + (block_id) * 0x20000ull) * 1024; in CVMX_PCSX_ANX_LP_ABIL_REG()
55 return 0x00011800B0001018ull + ((offset) + (block_id) * 0x4000ull) * 1024; in CVMX_PCSX_ANX_LP_ABIL_REG()
[all …]
A Dcvmx-pcieepx-defs.h12 static inline u64 CVMX_PCIEEPX_CFG000(unsigned long offset) in CVMX_PCIEEPX_CFG000() argument
18 return 0x0000030000000000ull + (offset) * 0x100000000ull; in CVMX_PCIEEPX_CFG000()
21 return 0x0000030000000000ull + (offset) * 0x100000000ull; in CVMX_PCIEEPX_CFG000()
23 return 0x0000030000000000ull + (offset) * 0x100000000ull; in CVMX_PCIEEPX_CFG000()
26 return 0x0000030000000000ull + (offset) * 0x100000000ull; in CVMX_PCIEEPX_CFG000()
37 static inline u64 CVMX_PCIEEPX_CFG001(unsigned long offset) in CVMX_PCIEEPX_CFG001() argument
43 return 0x0000030000000004ull + (offset) * 0x100000000ull; in CVMX_PCIEEPX_CFG001()
46 return 0x0000030000000004ull + (offset) * 0x100000000ull; in CVMX_PCIEEPX_CFG001()
51 return 0x0000030000000004ull + (offset) * 0x100000000ull; in CVMX_PCIEEPX_CFG001()
62 static inline u64 CVMX_PCIEEPX_CFG002(unsigned long offset) in CVMX_PCIEEPX_CFG002() argument
[all …]
A Dcvmx-gserx-defs.h82 #define CVMX_GSERX_EQ_WAIT_TIME(offset) (0x00011800904E0000ull + ((offset) & 15) * 0x1000000ull) argument
90 #define CVMX_GSERX_RX_PWR_CTRL_P1(offset) (0x00011800904600B0ull + ((offset) & 15) * 0x1000000ull) argument
91 #define CVMX_GSERX_RX_PWR_CTRL_P2(offset) (0x00011800904600B8ull + ((offset) & 15) * 0x1000000ull) argument
92 #define CVMX_GSERX_RX_EIE_DETSTS(offset) (0x0001180090000150ull + ((offset) & 15) * 0x1000000ull) argument
94 #define CVMX_GSERX_LANE_MODE(offset) (0x0001180090000118ull + ((offset) & 15) * 0x1000000ull) argument
164 #define CVMX_GSERX_PLL_STAT(offset) (0x0001180090000010ull + ((offset) & 15) * 0x1000000ull) argument
165 #define CVMX_GSERX_QLM_STAT(offset) (0x00011800900000A0ull + ((offset) & 15) * 0x1000000ull) argument
172 #define CVMX_GSERX_SLICE_CFG(offset) (0x0001180090460060ull + ((offset) & 15) * 0x1000000ull) argument
183 #define CVMX_GSERX_REFCLK_SEL(offset) (0x0001180090000008ull + ((offset) & 15) * 0x1000000ull) argument
184 #define CVMX_GSERX_PHY_CTL(offset) (0x0001180090000000ull + ((offset) & 15) * 0x1000000ull) argument
[all …]
/u-boot-v2022.01-rc1/arch/x86/cpu/apollolake/
A Dfsp_bindings.c219 &cfg[fspb->offset]); in fsp_update_config_from_dtb()
223 (u16 *)&cfg[fspb->offset]); in fsp_update_config_from_dtb()
229 (u32 *)&cfg[fspb->offset]); in fsp_update_config_from_dtb()
233 (u64 *)&cfg[fspb->offset]); in fsp_update_config_from_dtb()
239 (char *)&cfg[fspb->offset]); in fsp_update_config_from_dtb()
243 &cfg[fspb->offset]); in fsp_update_config_from_dtb()
503 .offset = offsetof(struct fsp_m_config,
1172 .offset = offsetof(struct fsp_s_config,
1189 .offset = offsetof(struct fsp_s_config,
1229 .offset = offsetof(struct fsp_s_config,
[all …]
/u-boot-v2022.01-rc1/scripts/dtc/libfdt/
A Dfdt.c137 if (offset < 0) in fdt_offset_ptr()
189 offset += 4; in fdt_next_tag()
211 if ((offset < 0) || (offset % FDT_TAGSIZE) in fdt_check_node_offset_()
215 return offset; in fdt_check_node_offset_()
220 if ((offset < 0) || (offset % FDT_TAGSIZE) in fdt_check_prop_offset_()
221 || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP)) in fdt_check_prop_offset_()
224 return offset; in fdt_check_prop_offset_()
264 return offset; in fdt_next_node()
271 offset = fdt_next_node(fdt, offset, &depth); in fdt_first_subnode()
275 return offset; in fdt_first_subnode()
[all …]
A Dfdt_ro.c122 offset = fdt_next_node(fdt, offset, NULL); in fdt_find_max_phandle()
234 offset = fdt_next_node(fdt, offset, &depth)) in fdt_subnode_offset_namelen()
341 int offset; in fdt_first_property_offset() local
554 (offset >= 0) && (offset <= nodeoffset); in fdt_get_path()
555 offset = fdt_next_node(fdt, offset, &depth)) { in fdt_get_path()
586 if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0)) in fdt_get_path()
606 (offset >= 0) && (offset <= nodeoffset); in fdt_supernode_atdepth_offset()
607 offset = fdt_next_node(fdt, offset, &depth)) { in fdt_supernode_atdepth_offset()
670 offset = fdt_next_node(fdt, offset, NULL)) { in fdt_node_offset_by_prop_value()
697 offset = fdt_next_node(fdt, offset, NULL)) { in fdt_node_offset_by_phandle()
[all …]
/u-boot-v2022.01-rc1/drivers/pinctrl/rockchip/
A Dpinctrl-rockchip.h41 int offset; member
75 int offset; member
109 { .offset = -1 }, \
110 { .offset = -1 }, \
111 { .offset = -1 }, \
112 { .offset = -1 }, \
135 { .offset = -1 }, \
136 { .offset = -1 }, \
137 { .offset = -1 }, \
138 { .offset = -1 }, \
[all …]
/u-boot-v2022.01-rc1/drivers/misc/
A Dp2sb-uclass.c43 reg_addr += offset; in pcr_reg_address()
59 assert(IS_ALIGNED(offset, align)); in check_pcr_offset_align()
111 write_completion(dev, offset); in pcr_write32()
121 write_completion(dev, offset); in pcr_write16()
131 write_completion(dev, offset); in pcr_write8()
138 data32 = pcr_read32(dev, offset); in pcr_clrsetbits32()
141 pcr_write32(dev, offset, data32); in pcr_clrsetbits32()
148 data16 = pcr_read16(dev, offset); in pcr_clrsetbits16()
151 pcr_write16(dev, offset, data16); in pcr_clrsetbits16()
158 data8 = pcr_read8(dev, offset); in pcr_clrsetbits8()
[all …]
/u-boot-v2022.01-rc1/include/
A Dp2sb.h79 uint pcr_read32(struct udevice *dev, uint offset);
80 uint pcr_read16(struct udevice *dev, uint offset);
81 uint pcr_read8(struct udevice *dev, uint offset);
94 void pcr_write8(struct udevice *dev, uint offset, uint data);
116 return pcr_clrsetbits32(dev, offset, 0, set); in pcr_setbits32()
121 return pcr_clrsetbits16(dev, offset, 0, set); in pcr_setbits16()
126 return pcr_clrsetbits8(dev, offset, 0, set); in pcr_setbits8()
131 return pcr_clrsetbits32(dev, offset, clr, 0); in pcr_clrbits32()
136 return pcr_clrsetbits16(dev, offset, clr, 0); in pcr_clrbits16()
141 return pcr_clrsetbits8(dev, offset, clr, 0); in pcr_clrbits8()
[all …]
/u-boot-v2022.01-rc1/arch/arm/cpu/armv7/ls102xa/
A Dfsl_epu.c173 u32 offset; in fsl_epu_clean() local
177 for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE) in fsl_epu_clean()
178 out_be32(epu_base + offset, 0); in fsl_epu_clean()
181 for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE) in fsl_epu_clean()
182 out_be32(epu_base + offset, 0); in fsl_epu_clean()
188 for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE) in fsl_epu_clean()
192 for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE) in fsl_epu_clean()
196 for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE) in fsl_epu_clean()
200 for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE) in fsl_epu_clean()
204 for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE) in fsl_epu_clean()
[all …]
/u-boot-v2022.01-rc1/drivers/usb/musb-new/
A Dmusb_io.h46 { return __raw_readw(addr + offset); } in musb_readw()
49 { return __raw_readl(addr + offset); } in musb_readl()
53 { __raw_writew(data, addr + offset); } in musb_writew()
56 { __raw_writel(data, addr + offset); } in musb_writel()
69 tmp = __raw_readw(addr + (offset & ~1)); in musb_readb()
70 if (offset & 1) in musb_readb()
82 tmp = __raw_readw(addr + (offset & ~1)); in musb_writeb()
83 if (offset & 1) in musb_writeb()
88 __raw_writew(tmp, addr + (offset & ~1)); in musb_writeb()
94 { return __raw_readb(addr + offset); } in musb_readb()
[all …]
/u-boot-v2022.01-rc1/drivers/pinctrl/mscc/
A Dmscc-common.c30 if (offset < 32) in mscc_writel()
38 if (offset < 32) in mscc_readl()
46 if (offset < 32) in mscc_setbits()
54 if (offset < 32) in mscc_clrbits()
94 int f, offset, regoff; in mscc_pinmux_set_mux() local
106 offset = pin->pin; in mscc_pinmux_set_mux()
108 if (offset >= 32) { in mscc_pinmux_set_mux()
109 offset = offset % 32; in mscc_pinmux_set_mux()
185 BIT(offset % 32)) in mscc_gpio_get()
200 mscc_writel(offset, in mscc_gpio_set()
[all …]
/u-boot-v2022.01-rc1/arch/arm/cpu/armv8/
A Dspin_table.c13 int cpus_offset, offset; in spin_table_update_dt() local
24 for (offset = fdt_first_subnode(fdt, cpus_offset); in spin_table_update_dt()
25 offset >= 0; in spin_table_update_dt()
26 offset = fdt_next_subnode(fdt, offset)) { in spin_table_update_dt()
27 prop = fdt_getprop(fdt, offset, "device_type", NULL); in spin_table_update_dt()
36 prop = fdt_getprop(fdt, offset, "enable-method", NULL); in spin_table_update_dt()
41 for (offset = fdt_first_subnode(fdt, cpus_offset); in spin_table_update_dt()
42 offset >= 0; in spin_table_update_dt()
43 offset = fdt_next_subnode(fdt, offset)) { in spin_table_update_dt()
44 prop = fdt_getprop(fdt, offset, "device_type", NULL); in spin_table_update_dt()
[all …]
/u-boot-v2022.01-rc1/include/dt-bindings/clock/
A Dam3.h17 #define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) argument
23 #define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) argument
78 #define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) argument
94 #define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) argument
102 #define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) argument
114 #define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) argument
149 #define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) argument
158 #define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) argument
172 #define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) argument
185 #define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) argument
[all …]
/u-boot-v2022.01-rc1/drivers/gpio/
A Dsandbox.c33 if (offset >= uc_priv->gpio_count) { in get_gpio_state()
38 return &state[offset]; in get_gpio_state()
119 ulong flags = *get_gpio_flags(dev, offset); in sandbox_gpio_get_flags()
140 debug("%s: offset:%u\n", __func__, offset); in sb_gpio_direction_input()
167 debug("%s: offset:%u\n", __func__, offset); in sb_gpio_get_value()
169 return sandbox_gpio_get_value(dev, offset); in sb_gpio_get_value()
181 offset); in sb_gpio_set_value()
206 desc->offset = args->args[0]; in sb_gpio_xlate()
261 gpio->pins[0] = desc->offset; in sb_gpio_get_acpi()
269 gpio->pin0_addr = 0x80012 + desc->offset; in sb_gpio_get_acpi()
[all …]
A Dintel_ich6_gpio.c70 val |= (1UL << offset); in _ich6_gpio_set_value()
72 val &= ~(1UL << offset); in _ich6_gpio_set_value()
86 val |= (1UL << offset); in _ich6_gpio_set_direction()
90 val &= ~(1UL << offset); in _ich6_gpio_set_direction()
101 int offset; in gpio_ich6_of_to_plat() local
109 if (offset == -1) { in gpio_ich6_of_to_plat()
113 plat->offset = offset; in gpio_ich6_of_to_plat()
114 plat->base_addr = gpiobase + offset; in gpio_ich6_of_to_plat()
157 if (!(tmplong & (1UL << offset))) { in ich6_gpio_request()
159 offset); in ich6_gpio_request()
[all …]
A Dgpio-rcar.c48 const u32 bit = BIT(offset); in rcar_gpio_get_value()
86 clrbits_le32(regs + GPIO_POSNEG, BIT(offset)); in rcar_gpio_set_direction()
91 clrbits_le32(regs + GPIO_INEN, BIT(offset)); in rcar_gpio_set_direction()
93 setbits_le32(regs + GPIO_INEN, BIT(offset)); in rcar_gpio_set_direction()
97 clrbits_le32(regs + GPIO_IOINTSEL, BIT(offset)); in rcar_gpio_set_direction()
101 setbits_le32(regs + GPIO_INOUTSEL, BIT(offset)); in rcar_gpio_set_direction()
108 rcar_gpio_set_direction(dev, offset, false); in rcar_gpio_direction_input()
117 rcar_gpio_set_value(dev, offset, value); in rcar_gpio_direction_output()
118 rcar_gpio_set_direction(dev, offset, true); in rcar_gpio_direction_output()
136 return pinctrl_gpio_request(dev, offset); in rcar_gpio_request()
[all …]
A Dsifive-gpio.c41 u32 bit = BIT(offset); in sifive_update_gpio_reg()
55 if (offset > uc_priv->gpio_count) in sifive_gpio_direction_input()
71 if (offset > uc_priv->gpio_count) in sifive_gpio_direction_output()
91 if (offset > uc_priv->gpio_count) in sifive_gpio_get_value()
95 dir = !(readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset)); in sifive_gpio_get_value()
98 val = readl(plat->base + GPIO_INPUT_VAL) & BIT(offset); in sifive_gpio_get_value()
100 val = readl(plat->base + GPIO_OUTPUT_VAL) & BIT(offset); in sifive_gpio_get_value()
110 if (offset > uc_priv->gpio_count) in sifive_gpio_set_value()
124 if (offset > uc_priv->gpio_count) in sifive_gpio_get_function()
128 outdir = readl(plat->base + GPIO_OUTPUT_EN) & BIT(offset); in sifive_gpio_get_function()
[all …]
A Dintel_broadwell_gpio.c34 int offset; member
37 static int broadwell_gpio_request(struct udevice *dev, unsigned offset, in broadwell_gpio_request() argument
51 if (!(val & (1UL << offset))) { in broadwell_gpio_request()
65 setio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT); in broadwell_gpio_direction_input()
75 return inl(&regs->config[priv->offset + offset]) & CONFA_LEVEL_HIGH ? in broadwell_gpio_get_value()
87 clrsetio_32(&regs->config[priv->offset + offset], CONFA_OUTPUT_HIGH, in broadwell_gpio_set_value()
99 broadwell_gpio_set_value(dev, offset, value); in broadwell_gpio_direction_output()
100 clrio_32(&regs->config[priv->offset + offset], CONFA_DIR_INPUT); in broadwell_gpio_direction_output()
109 u32 mask = 1UL << offset; in broadwell_gpio_get_function()
113 if (inl(&regs->config[priv->offset + offset]) & CONFA_DIR_INPUT) in broadwell_gpio_get_function()
[all …]
/u-boot-v2022.01-rc1/drivers/pinctrl/
A Dpinctrl-stmfx.c59 #define get_reg(offset) ((offset) / NR_GPIOS_PER_REG) argument
60 #define get_shift(offset) ((offset) % NR_GPIOS_PER_REG) argument
61 #define get_mask(offset) (BIT(get_shift(offset))) argument
79 u8 reg = reg_base + get_reg(offset); in stmfx_read_reg()
80 u32 mask = get_mask(offset); in stmfx_read_reg()
93 u8 reg = reg_base + get_reg(offset); in stmfx_write_reg()
94 u32 mask = get_mask(offset); in stmfx_write_reg()
135 u32 mask = get_mask(offset); in stmfx_gpio_set()
211 ret = stmfx_conf_get_type(dev, offset); in stmfx_gpio_get_flags()
217 ret = stmfx_gpio_get(dev, offset); in stmfx_gpio_get_flags()
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