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Searched refs:pmc (Results 1 – 25 of 94) sorted by relevance

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/u-boot-v2022.01-rc1/arch/arm/mach-at91/
A Dclock.c28 writel(id, &pmc->pcr); in at91_periph_clk_enable()
30 div_value = readl(&pmc->pcr) & AT91_PMC_PCR_DIV; in at91_periph_clk_enable()
34 writel(regval, &pmc->pcr); in at91_periph_clk_enable()
36 writel(0x01 << id, &pmc->pcer); in at91_periph_clk_enable()
52 writel(regval, &pmc->pcr); in at91_periph_clk_disable()
54 writel(0x01 << id, &pmc->pcdr); in at91_periph_clk_disable()
62 writel(sys_clk, &pmc->scer); in at91_system_clk_enable()
69 writel(sys_clk, &pmc->scdr); in at91_system_clk_disable()
99 writel(readl(&pmc->uckr) & ~AT91_PMC_UPLLEN, &pmc->uckr); in at91_upll_clk_disable()
115 writel(value, &pmc->usb); in at91_usb_clk_init()
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A Dspl_atmel.c25 tmp = readl(&pmc->mor); in switch_to_main_crystal_osc()
31 writel(tmp, &pmc->mor); in switch_to_main_crystal_osc()
32 while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) in switch_to_main_crystal_osc()
37 tmp = readl(&pmc->mcfr); in switch_to_main_crystal_osc()
40 writel(tmp, &pmc->mcfr); in switch_to_main_crystal_osc()
49 tmp = readl(&pmc->mor); in switch_to_main_crystal_osc()
61 writel(tmp, &pmc->mor); in switch_to_main_crystal_osc()
63 tmp = readl(&pmc->mor); in switch_to_main_crystal_osc()
67 writel(tmp, &pmc->mor); in switch_to_main_crystal_osc()
79 tmp = readl(&pmc->mor); in switch_to_main_crystal_osc()
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A Dspl_at91.c36 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in lowlevel_clock_init() local
38 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { in lowlevel_clock_init()
40 writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); in lowlevel_clock_init()
43 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) in lowlevel_clock_init()
48 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { in lowlevel_clock_init()
51 tmp = readl(&pmc->mckr); in lowlevel_clock_init()
54 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
55 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
60 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
61 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
/u-boot-v2022.01-rc1/arch/arm/mach-at91/armv7/
A Dclock.c71 tmp = readl(&pmc->mcfr); in at91_clock_init()
86 mckr = readl(&pmc->mckr); in at91_clock_init()
131 tmp = readl(&pmc->mckr); in at91_mck_init()
148 writel(tmp, &pmc->mckr); in at91_mck_init()
165 tmp = readl(&pmc->mckr); in at91_mck_init_down()
168 writel(tmp, &pmc->mckr); in at91_mck_init_down()
174 tmp = readl(&pmc->mckr); in at91_mck_init_down()
177 writel(tmp, &pmc->mckr); in at91_mck_init_down()
180 tmp = readl(&pmc->mckr); in at91_mck_init_down()
213 writel(id, &pmc->pcr); in at91_enable_periph_generated_clk()
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/u-boot-v2022.01-rc1/arch/arm/mach-at91/arm926ejs/
A Dclock.c128 tmp = readl(&pmc->mcfr); in at91_clock_init()
156 mckr = readl(&pmc->mckr); in at91_clock_init()
225 tmp = readl(&pmc->mckr); in at91_mck_init()
228 writel(tmp, &pmc->mckr); in at91_mck_init()
232 tmp = readl(&pmc->mckr); in at91_mck_init()
235 writel(tmp, &pmc->mckr); in at91_mck_init()
239 tmp = readl(&pmc->mckr); in at91_mck_init()
242 writel(tmp, &pmc->mckr); in at91_mck_init()
246 tmp = readl(&pmc->mckr); in at91_mck_init()
249 writel(tmp, &pmc->mckr); in at91_mck_init()
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/u-boot-v2022.01-rc1/arch/arm/dts/
A Dsama7g5.dtsi50 clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
70 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
78 pmc: pmc@e0018000 { label
79 compatible = "microchip,sama7g5-pmc";
97 clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
108 clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
119 clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
127 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
145 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
153 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
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A Dsam9x60.dtsi60 clocks = <&pmc PMC_TYPE_CORE 19>, <&pmc PMC_TYPE_CORE 11>, <&main_xtal>;
74 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
76 assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
94 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 18>; /* ID_QSPI */
104 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>;
117 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
126 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
189 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
197 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
208 pmc: pmc@fffffc00 { label
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A Dsama5d3_tcb1.dtsi21 pmc: pmc@fffffc00 { label
A Dat91sam9g20.dtsi42 pmc: pmc@fffffc00 { label
/u-boot-v2022.01-rc1/arch/arm/mach-tegra/tegra124/
A Dcpu.c25 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
39 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
42 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()
43 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
170 val = readl(&pmc->pmc_osc_edpd_over); in tegra124_init_clocks()
173 writel(val, &pmc->pmc_osc_edpd_over); in tegra124_init_clocks()
176 setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); in tegra124_init_clocks()
239 reg = readl(&pmc->pmc_pwrgate_status); in is_partition_powered()
252 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); in unpower_partition()
291 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); in power_partition()
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/u-boot-v2022.01-rc1/arch/arm/mach-at91/arm920t/
A Dclock.c109 at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; in at91_clock_init() local
120 tmp = readl(&pmc->mcfr); in at91_clock_init()
129 gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); in at91_clock_init()
148 mckr = readl(&pmc->mckr); in at91_clock_init()
163 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; in at91_pllb_clk_enable() local
167 writel(pllbr, &pmc->pllbr); in at91_pllb_clk_enable()
168 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) { in at91_pllb_clk_enable()
181 struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; in at91_pllb_clk_disable() local
185 writel(0, &pmc->pllbr); in at91_pllb_clk_disable()
186 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) { in at91_pllb_clk_disable()
/u-boot-v2022.01-rc1/arch/x86/cpu/apollolake/
A Dcpu_spl.c97 struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc; in arch_cpu_init_tpl() local
100 ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc); in arch_cpu_init_tpl()
105 ret = pmc_global_reset_set_enable(pmc, false); in arch_cpu_init_tpl()
109 enable_pm_timer_emulation(pmc); in arch_cpu_init_tpl()
133 ret = pmc_disable_tco(pmc); in arch_cpu_init_tpl()
136 ret = pmc_gpe_init(pmc); in arch_cpu_init_tpl()
156 struct udevice *pmc, *p2sb; in arch_cpu_init_spl() local
159 ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc); in arch_cpu_init_spl()
170 ret = pmc_init(pmc); in arch_cpu_init_spl()
174 ret = pmc_prev_sleep_state(pmc); in arch_cpu_init_spl()
A Dpmc.c167 pci_dev_t pmc = priv->bdf; in enable_pmcbar() local
173 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_0, (ulong)upriv->pmc_bar0, in enable_pmcbar()
175 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32); in enable_pmcbar()
176 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_2, (ulong)upriv->pmc_bar2, in enable_pmcbar()
178 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32); in enable_pmcbar()
179 pci_x86_write_config(pmc, PCI_BASE_ADDRESS_4, upriv->acpi_base, in enable_pmcbar()
181 pci_x86_write_config(pmc, PCI_COMMAND, PCI_COMMAND_IO | in enable_pmcbar()
A Dcpu_common.c30 void enable_pm_timer_emulation(const struct udevice *pmc) in enable_pm_timer_emulation() argument
32 struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc); in enable_pm_timer_emulation()
A Dcpu.c141 struct udevice *pmc; in soc_core_init() local
154 ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc); in soc_core_init()
157 enable_pm_timer_emulation(pmc); in soc_core_init()
/u-boot-v2022.01-rc1/drivers/clk/at91/
A Dcompat.c321 &pmc->mckr); in at91_plladiv_clk_set_rate()
501 addr = &pmc->pcer; in periph_clk_enable()
503 addr = &pmc->pcer1; in periph_clk_enable()
508 setbits_le32(&pmc->pcr, in periph_clk_enable()
619 tmp = readl(&pmc->uckr); in utmi_clk_enable()
623 writel(tmp, &pmc->uckr); in utmi_clk_enable()
771 tmp = readl(&pmc->pcr); in generic_clk_get_rate()
841 tmp = readl(&pmc->pcr); in generic_clk_set_rate()
847 writel(tmp, &pmc->pcr); in generic_clk_set_rate()
910 tmp = readl(&pmc->pcr); in at91_usb_clk_get_rate()
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/u-boot-v2022.01-rc1/arch/arm/mach-tegra/tegra114/
A Dcpu.c22 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
37 writel(reg, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail()
40 clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL); in enable_cpu_power_rail()
41 setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE); in enable_cpu_power_rail()
190 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_partition_powered() local
194 reg = readl(&pmc->pmc_pwrgate_status); in is_partition_powered()
200 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in is_clamp_enabled() local
204 reg = readl(&pmc->pmc_clamp_status); in is_clamp_enabled()
210 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_partition() local
217 writel(START_CP | partid, &pmc->pmc_pwrgate_toggle); in power_partition()
/u-boot-v2022.01-rc1/arch/arm/mach-tegra/tegra20/
A Dcpu.c15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
18 reg = readl(&pmc->pmc_cntrl); in enable_cpu_power_rail()
20 writel(reg, &pmc->pmc_cntrl); in enable_cpu_power_rail()
A Dwarmboot_avp.c26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in wb_start() local
67 if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) { in wb_start()
69 writel(reg, &pmc->pmc_pwrgate_toggle); in wb_start()
70 while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) in wb_start()
75 reg = readl(&pmc->pmc_remove_clamping); in wb_start()
77 writel(reg, &pmc->pmc_remove_clamping); in wb_start()
99 reg = readl(&pmc->pmc_scratch41); in wb_start()
142 writel(reg, &pmc->pmc_scratch1); in wb_start()
146 scratch3.word = readl(&pmc->pmc_scratch3); in wb_start()
/u-boot-v2022.01-rc1/arch/arm/mach-tegra/
A Dsys_info.c15 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in get_reset_cause() local
17 switch (pmc->pmc_reset_status) { in get_reset_cause()
A Dap.c154 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in init_pmc_scratch() local
164 writel(0, &pmc->pmc_scratch1 + i); in init_pmc_scratch()
169 writel(odmdata, &pmc->pmc_scratch20); in init_pmc_scratch()
/u-boot-v2022.01-rc1/board/atmel/sama5d2_xplained/
A Dsama5d2_xplained.c147 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in mem_init() local
155 writel(AT91_PMC_DDR, &pmc->scer); in mem_init()
175 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in at91_pmc_init() local
194 writel(0x0 << 8, &pmc->pllicpr); in at91_pmc_init()
/u-boot-v2022.01-rc1/arch/arm/mach-tegra/tegra30/
A Dcpu.c52 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local
56 reg = readl(&pmc->pmc_cntrl); in enable_cpu_power_rail()
58 writel(reg, &pmc->pmc_cntrl); in enable_cpu_power_rail()
/u-boot-v2022.01-rc1/arch/arm/mach-at91/include/mach/
A Dclk.h63 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; in get_h32mxdiv() local
65 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV; in get_h32mxdiv()
/u-boot-v2022.01-rc1/board/st/stm32f746-disco/
A Dstm32f746-disco.c132 STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; in board_init()
135 STM32_SYSCFG->pmc &= ~SYSCFG_PMC_MII_RMII_SEL; in board_init()

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