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/u-boot-v2022.01-rc1/drivers/remoteproc/
A DKconfig26 bool "Support for Test processor for Sandbox"
31 Say 'y' here to add support for test processor which does dummy
51 Say y here to support TI's ARM64 processor subsystems
52 on various TI K3 family of SoCs through the remote processor
61 Say y here to support TI's C66/C71 remote processor subsystems
62 on various TI K3 family of SoCs through the remote processor
71 Say y here to support TI's R5F remote processor subsystems
72 on various TI K3 family of SoCs through the remote processor
76 bool "Support for TI Power processor"
/u-boot-v2022.01-rc1/doc/device-tree-bindings/remoteproc/
A Dti,k3-dsp-rproc.txt5 are used to offload some of the processor-intensive tasks or algorithms, for
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor cores in the
11 K3 SoCs is usually either a TMS320C66x CorePac processor or a TMS320C71x CorePac
12 processor.
18 host processor (Arm CorePac) to perform the device management of the remote
19 processor and to communicate with the remote processor.
48 contain the TI-SCI processor id for the DSP core device
50 which the processor control ownership should be
A Dremoteproc.txt9 - remoteproc-name: a string, used if provided to describe the processor.
12 processor has internal memory that it uses to execute code and store
A Dti,k3-r5f-rproc.txt1 TI K3 R5F processor subsystems
5 R5F processor subsystems/clusters (R5FSS). The dual core cluster can be
16 the OS running on the host processor to perform the device management of the
17 remote processor and to communicate with the remote processor.
52 address space for the processor.
76 contain the TI-SCI processor id for the R5F core device
78 which the processor control ownership should be
A Dk3-rproc.txt1 Texas Instruments' K3 Remote processor driver
35 - ti,sci-host-id: Host ID to which the processor control is transferred to
/u-boot-v2022.01-rc1/doc/develop/driver-model/
A Dremoteproc-framework.rst12 on various System on Chip(SoCs). The term remote processor is used to
13 indicate that this is not the processor on which U-Boot is operating
15 the processor on which we are functional.
62 NOTE: It depends on the remote processor as to the exact behavior
66 allow us to start the processor(image from a EEPROM/OTP) etc.
73 Remote processor can operate on a certain firmware that maybe loaded
88 {.compatible = "sandbox,test-processor"},
155 compatible = "sandbox,test-processor";
160 compatible = "sandbox,test-processor";
/u-boot-v2022.01-rc1/doc/
A DREADME.fsl-esdhc5 determined by ESDHC IP's endian mode or processor's endian mode.
8 by ESDHC IP's endian mode or processor's endian mode.
/u-boot-v2022.01-rc1/board/synopsys/hsdk/
A DKconfig20 ARC HS Development Kit based on quard core ARC HS38 processor
26 processor
/u-boot-v2022.01-rc1/board/freescale/ls1021aqds/
A DREADME7 The QorIQ LS1 family, which includes the LS1021A communications processor,
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
18 optimized peripheral features ever offered in a sub-3 W processor.
20 The QorIQ LS1021A processor features an integrated LCD controller,
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
32 - NEON Co-processor (per core)
/u-boot-v2022.01-rc1/board/freescale/ls1021atwr/
A DREADME7 The QorIQ LS1 family, which includes the LS1021A communications processor,
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
18 optimized peripheral features ever offered in a sub-3 W processor.
20 The QorIQ LS1021A processor features an integrated LCD controller,
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
32 - NEON Co-processor (per core)
/u-boot-v2022.01-rc1/doc/usage/
A Dscp03.rst19 Channel Protocol 03 stablished between the processor and the secure
22 This protocol encrypts all the communication between the processor and
/u-boot-v2022.01-rc1/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.soc16 The LS1043A integrated multicore processor combines four ARM Cortex-A53
17 processor cores with datapath acceleration optimized for L2/3 packet
54 The QorIQ LS1088A processor is built on the Layerscape
55 architecture combining eight ARM A53 processor cores
86 The LS2080A integrated multicore processor combines eight ARM Cortex-A57
131 A53 processor, with 32 KB of parity protected L1-I cache,
172 The LS1046A integrated multicore processor combines four ARM Cortex-A72
173 processor cores with datapath acceleration optimized for L2/3 packet
280 The QorIQ LX2160A processor is built in the 16FFC process on
281 the Layerscape architecture combining sixteen ARM A72 processor
[all …]
/u-boot-v2022.01-rc1/doc/arch/
A Dxtensa.rst9 Xtensa is a configurable processor architecture from Tensilica, Inc.
31 Adding support for an additional processor configuration
34 The header files for one particular processor configuration are inside
37 the name for the processor configuration, for example, arch-dc233c for
38 the Diamond DC233 processor.
76 the 'entry'. Decoding depends on the processor's endianness so uses the
/u-boot-v2022.01-rc1/drivers/sysreset/
A DKconfig143 bool "Enable support for x86 processor reboot driver"
146 Reboot support for generic x86 processor reset.
149 bool "Enable support for x86 processor reboot driver in SPL"
152 Reboot support for generic x86 processor reset in SPL.
155 bool "Enable support for x86 processor reboot driver in TPL"
158 Reboot support for generic x86 processor reset in TPL.
/u-boot-v2022.01-rc1/arch/x86/include/asm/arch-quark/acpi/
A Dglobal_nvs.asl11 PCNT, 8, /* processor count */
/u-boot-v2022.01-rc1/drivers/video/imx/
A DKconfig7 on the IPUv3(Image Processing Unit) internal graphic processor.
/u-boot-v2022.01-rc1/arch/x86/include/asm/arch-baytrail/acpi/
A Dglobal_nvs.asl11 PCNT, 8, /* processor count */
/u-boot-v2022.01-rc1/arch/x86/include/asm/arch-tangier/acpi/
A Dglobal_nvs.asl13 PCNT, 8, /* processor count */
/u-boot-v2022.01-rc1/arch/xtensa/include/asm/
A Dbyteorder.h79 # error processor byte order undefined!
/u-boot-v2022.01-rc1/board/armltd/integrator/
A DREADME15 Each CM consists of a ARM processor core and associated hardware e.g
47 Code specific to initialization of a particular ARM processor has been placed in
50 However, to avoid duplicating code through all processor files, a generic core
56 need placing in each CM processor file......
/u-boot-v2022.01-rc1/board/intel/
A DKconfig24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
57 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
58 single-core, single-thread, Intel Pentium processor instrunction set
69 processor in a small form factor with Ethernet, micro-SD, USB 2,
/u-boot-v2022.01-rc1/board/freescale/ls1012ardb/
A DREADME5 The LS1012ARDB board supports the QorIQ LS1012A processor and is
36 - The LS1012A processor consists of two UART controllers,
72 - The LS1012A processor consists of two UART controllers,
/u-boot-v2022.01-rc1/board/freescale/ls1043ardb/
A DREADME5 LayerScape Architecture processor. The LS1043ARDB provides SW development
6 platform for the Freescale LS1043A processor series, with a complete
/u-boot-v2022.01-rc1/disk/
A Dpart_mac.h73 uchar processor[16]; /* Type of Processor */ member
/u-boot-v2022.01-rc1/board/advantech/
A DKconfig14 Atom E3845 or Celeron N2920 processor.

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